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DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
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January 1995
Philips Semiconductors
Product specication
Hex inverter
DESCRIPTION The HEF4069UB is a general purpose hex inverter. Each of the six inverters is a single stage.
HEF4069UB gates
14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1)
FAMILY DATA, IDD LIMITS category GATES See Family Specifications for VIH/VIL unbuffered stages
January 1995
Philips Semiconductors
Product specication
Hex inverter
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays In On HIGH to LOW LOW to HIGH Output transition times HIGH to LOW 5 10 15 5 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL SYMBOL TYP. MAX. 45 20 15 40 20 15 60 30 20 60 30 20 90 ns 40 ns 25 ns 80 ns 40 ns 30 ns 120 ns 60 ns 40 ns 120 ns 60 ns 40 ns
HEF4069UB gates
TYPICAL EXTRAPOLATION FORMULA 18 ns + (0,55 ns/pF) CL 9 ns + (0,23 ns/pF) CL 7 ns + (0,16 ns/pF) CL 13 ns + (0,55 ns/pF) CL 9 ns + (0,23 ns/pF) CL 7 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL
TYPICAL FORMULA FOR P (W) 600 fi + (foCL) VDD2 4 000 fi + (foCL) 22 000 fi + (foCL) VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)
January 1995
Philips Semiconductors
Product specication
Hex inverter
HEF4069UB gates
Fig.4
Fig.5
Fig.6
January 1995
Philips Semiconductors
Product specication
Hex inverter
APPLICATION INFORMATION Some examples of applications for the HEF4069UB are shown below.
HEF4069UB gates
In Fig.7 an astable relaxation oscillator is given. The oscillation frequency is mainly determined by R1C1, provided R1 << R2 and R2C2 << R1C1.
(a)
(b)
The function of R2 is to minimize the influence of the forward voltage across the protection diodes on the frequency; C2 is a stray (parasitic) capacitance. The period Tp is given by Tp = T1 + T2, in which V DD + V ST 2 V DD V ST T 1 = R1C1 In ---------------------------- and T 2 = R1C1 In --------------------------------- where V ST V DD V ST VST is the signal threshold level of the inverter. The period is fairly independent of VDD, VST and temperature. The duty factor, however, is influenced by VST.
Fig.7
(a) Astable relaxation oscillator using two HEF4069UB inverters; the diodes may be BAW62; C2 is a parasitic capacitance. (b) Waveforms at the points marked A, B, C and D in the circuit diagram.
January 1995
Philips Semiconductors
Product specication
Hex inverter
HEF4069UB gates
(1) This inverter is added to amplify the oscillator output voltage to a level sufficient to drive other LOCMOS circuits.
Fig.8 Crystal oscillator for frequencies up to 10 MHz, using two HEF4069UB inverters.
Fig.9
January 1995
Philips Semiconductors
Product specication
Hex inverter
HEF4069UB gates
Fig.12 Test set-up for measuring forward transconductance gfs = dio/dvi at vo is constant (see also graph Fig.13).
Fig.13 Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 C.
January 1995