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The use of Optimization in Signal Integrity Performance Centric High Speed Digital Design Flow

Brahim Bensalem, Intel Corporation Lihua Wang, Agilent Technologies Sanjeev Gupta, Agilent Technologies

Eye Diagram Measurements in ADS Page 1

Agenda
Channel Complexity and Gaps in Current Design Flow Advantage of End to End Eye Centric Design Flow Why an Eye Diagram ? Eye Diagram Measurements in ADS. Optimization of DDR2 Channel. Introduction to Batch mode simulation ADS near term roadmap for DDR designs

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Gap in Channel Design Flow


Conventional Flow Desired Flow

Design Target
Eye Mask, TJ, SU/HD Margin, etc.

Design Target
Eye Mask, TJ, SU/HD Margin, etc.

Chanel Parameters
Impedance, Signal spacing, total length, Rtt, et.

Chanel Parameters
Impedance, Signal spacing, total length, Rtt, et.

Solution Space Exploration


DOE, Corner Ana., Monte Carlo TD and/or FD

Optimize Param. for Max. Eye Performance

No

Post Process/Convert to Design Target YES

Target Met?

End
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Advantage of Eye Centric Design Flow

Substantial gain in Channel Design Time (More than 3 weeks in our DDR2 case) Design is more robust since channel is optimized toward end to end channel performance Reduces risk of marginal design or opportunity loss due to over design

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Eye Diagram Functions In ADS

Why Eye Diagram is Important?

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Characterizing an Eye Diagram


Most commonly used eye diagram measurements

Eye level 1 & level 0 Eye rise/ fall time Eye opening Eye width Eye height Eye amplitude Peak to peak & RMS jitter
Delay Effect

Most of the measurements are statistical in nature


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Slice and Dice


Eye Binning

Eye Diagram

Binning Data

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Histogram Plots
Histogram can be created for any portion of eye diagram

Histogram across timing axis provide peak to peak jitter

Histogram across amplitude axis provide distribution around level one and zero

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Eye Delay
Why delay calculation is required

Delay calculation is required for automated eye parameter measurements Binning the eye diagram makes this calculation easy

Calculated Delay

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Automated Eye Crossing Detection

Mean value of horizontal histogram provide crossing time value Mean value of amplitude histogram provides crossing amplitude value

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Measurements of Eye Level One/Zero

Eye Amplitude

Eye Height

1 3 3 1

Eye Amplitude = Level One Level Zero Eye Height = (Eye level one- 3)- (Eye level zero+3) Eye S/N= (Eye level one-Eye level zero) 1 level one+1 level zero 0% 40% 60% 100%

Measurement boundaries

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Eye Measurements in ADS2008

Eye Diagram Measurements in ADS Page 12

Eye Measurements in ADS2009


Eye Probe (new addition to ADS2009)

Fast and Easy

How to select eye measurements

Any number of Eye probes could be used in a design

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DDR2 Simulation in ADS


IBIS drivers and triggers Memory Module & Eye Probe

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Memory Bus Simulation using ADS


X8 Un-buffered Memory Down Channel 8 SDRAM Devices per signal Signal Group : CMD/ADD

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Memory Performance at DRAM

How to improve channel performance?

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Introduction to Optimization Time domain Optimization and why it is difficult Optimization of DDR2 Channel

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Optimization in ADS
Modify your Designs Automatically to Achieve Required Performance

Why Optimization? Parameter sweep often doesnt lead to an optimized designs Parameter sweeps requires usually large number of simulation when number of variables are large The use of Optimizers in a design process
Automatically change design parameter to meet design goals Categorized by their error function formulation Coarse design stages: Random optimizer, Random Minimax optimizer and Simulated Annealing optimizer Fine design stages: Gradient optimizer, Gradient Minimax optimizer, Quasi-Newton optimizer and Minimax optimizer

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Issues with Time Domain Optimization

Time domain optimization goals are often difficult to define

Changes in any reactive component during optimization will effect channel delay and optimization goals may no longer be applicable

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DDR2 Channel Design


X8 Un-buffered Memory Down Channel 8 SDRAM Devices Signal Group to Optimize: CMD/ADD Design Parameters:
Leadin 2-4 in Escape W leadin S Breakout 3-5 mils Trace Spacing 8-15 mils Rtt 20-100 L Brkout 0.3-0.8in

0.3-0.8 in 3.5-5.5 mils

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Eye Diagram Optimization


ADS2009 makes it easy to perform eye optimization Any eye measurement could be used as an optimization expression Any number of eye probes, measurements & parameters could be optimized at the same time

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Optimized Eye Diagram Performance

Eye Diagram after Channel Optimization

Optimizer Type Number of iteration Optimization time

: Random : 20 : 25 minutes

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Performance Comparison
Before After

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Sweeping Corner Case


Batch simulation is used to sweep corner cases

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Batch Mode Simulation in ADS


Introduced in ADS2008 Update 2
BATCH SIMULATION
BatchSimController BatchSim1 Var= Start=1.0 Stop=10.0 Step=1.0 Lin= UseSweepPlan= Analysis[1]= UseSweepModule= SweepModuleArgument= SweepModule=

DataFileList

String List

The new palette will have four components: the batch simulation controller the DataFileList container the StringList container the NetlistIncludeList container

DataFileList DataFileList1 FileName[1]=

StringList StringList1 String[1]=

Netlist Include List


NetlistIncludeList NetlistIncludeList1 NetlistName[1]=

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Batch Simulation Controller Dialog

Eliminates requirement to write complex manual scripts Uses Sweep Plan or Sweep Module No limits on number of parameter sweep Allow sweeping of Touchstone files, connector models, netlist etc. Allow parameters to be defined in .csv format Enable complex measurements such as eye diagram under parameter sweep mode.
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Simulation Results

Here only Rx corner cases was swept. Batch mode allows simulation of any combination of Tx/Rx corner cases and IBIS models

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Time Domain Optimization Discussed


Works well even if the flight time delay is changed due to change in the reactive element value. Automatically calculates delay required for eye positioning Automatically detects eye crossing point and 40-60% region Optimize eye diagram performance Corner case simulation performance was determined Any eye diagram parameter such as eye opening factor, eye height, peak to peak jitter, rise time can be used as an optimization goal. Will make your design work without running 1000s of parameter sweep

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DDR Mesurements

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Near Term Roadmap

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Post ADS2009 Update 1: Memory Compliance Toolkits

vdd

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R R1 R=R_dq Ohm ML1CTL_C dq_TL0 Subs t="DIMMSUB" Length=3 mm W=W mil Lay er=1 ML1CTL_C dq_TL1 Subst="DIMMSUB" Length=14.3 mm W=W mil Lay er=1

IBIS_IO IBIS11 Ibis File="u37y_800.ibs" ComponentName="MT47H32M16BN_CLP_3_neg25" PinName="K8" ModelName="DQ_FULL_800" SetAllData=y es DataTy peSelec tor=Ty p Us ePk g=y es

Var Eqn

VAR VAR3 W=5.0

IBIS_IO IBIS26 Ibis File="u37y _800.ibs" ComponentName="MT47H32M16BN_CLP_3_neg25" PinName="K8" ModelName="DQ_FULL_800" SetAllData=y es DataTy peSelec tor=Ty p Us ePk g=y es

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IBIS_DIO IBIS8 Ibis File="u37y_800.ibs" ComponentName="MT47H32M16BN_CLP_3_neg25" PinName="E7" ModelName="DQ_FULL_800" SetAllData=y es DataTy peSelec tor=Ty p Us ePk g=y es

DQS_DRAM_1N IBIS_DIO IBIS27 Ibis File="u37y_800.ibs" ComponentName="MT47H32M16BN_CLP_3_neg25" PinName="E7" ModelName="DQ_FULL_800" SetAllData=y es DataTy peSelec tor=Ty p Us ePk g=y es
PD Dig O

ML2CTL_C dqs_TL2_2 Subs t="DIMMSUB" Length=2.9 mm W=W mil S=6.0 mil Layer=1 RLGC_File= Reus eRLGC=no

Page 31

PU

GC

PC

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VtPRBS VPRBS5 BitSequenc e="10101010" Vlow=0.0 V Vhigh=2 V EdgeShape=Linear Transition BitRate=0.75 GHz Ris eTime=10 ps ec FallTime=10 ps ec Delay =0 ps ec

IBIS_DIO IBIS24 Ibis File="v irtex5.ibs " ComponentName="VIRTEX-5_FF1136" PinName="20P" ModelName="SSTL18_I" SetAllData=y es DataTy peSelec tor=Ty p UsePk g=y es

ML2CTL_C dqs _TL0A1 Subs t="DIMMSUB" Length=3 in W=W mil S=6.0 mil Lay er=1 RLGC_File= Reus eRLGC=no

ML2CTL_C dqs _TL0 Subs t="DIMMSUB" Length=3 mm W=W mil S=6 mil Lay er=1 RLGC_File= Reus eRLGC=no

R R8 R=R_dqs Ohm

ML2CTL_C dqs_TL1 Subs t="DIMMSUB" Length=3 mm W=W mil S=6 mil Layer=1 RLGC_File= ReuseRLGC=no v dd DQS_DRAM_1P

PD

ML2CTL_C dqs _TL2_1 Subst="DIMMSUB" Length=2.9 mm W=W mil S=6.0 mil Lay er=1 RLGC_File= Reus eR LGC=no

PU

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PC

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IO_I

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ML1CTL_C dq_TL2_2 Subst="DIMMSUB" Length=2.9 mm W=W mil Lay er=1

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GC PC IO

PU

VtPRBS VPRBS4 Regis terLength=17 Vlow=0.0 V Vhigh=2 V EdgeShape=Linear Transition BitRate=0.75 GHz Ris eTime=10 ps ec FallTime=10 ps ec Delay =0 ps ec

ML1CTL_C PD Di gO dq_TL0A1 Subs t="D IMMSUB" IBIS_IO Length=3 in IBIS21 IbisFile="v irtex 5.ibs " W=W mil ComponentName="VIRTEX-5_FF1136" er=1 Lay PinName="12" ModelName="SSTL18_I" SetAllData=y es DataTy peSelec tor=Ty p Us ePkg=y es

v dd

PD

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DRAM_0 ML1CTL_C dq_TL2_1 Subs t="DIMMSUB" Length=2.9 mm W=W mil Layer=1

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VtPRBS VPRBS3 Regis terLength=17 Vlow=0.0 V Vhigh=2 V EdgeShape=Linear Transition BitRate=0.75 GHz Ris eTime=10 ps ec FallTime=10 ps ec Delay =0 ps ec

IBIS_IO IBIS17 IbisFile="v irtex 5.ibs " ComponentName="VIRTEX-5_FF1136" PinName="12" ModelName="SSTL18_I" SetAllData=y es DataTy peSelec tor=Ty p Us ePkg=y es

v dd

Eye Diagram Measurements in ADS

Memory Compliance Toolkits-Features


Comprehensive JEDEC measurement support

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Memory Compliance Toolkits-Features

Easy installation (ADS design kit format) and frequent updates

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Memory Compliance Toolkits-Features


Open-source memory measurements (C/C++) Easy to add new user-defined capability Automatic compilation of user-defined measurements for streamlined deployment Built-in, free compiler requires no additional software for user-defined functionality

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Memory Compliance Toolkits-Features

Comprehensive reporting
2.15 2.10

SlewRSetupFall

2.05

2.00

1.95

1.90 0 2 4 6 8 10 12 14 16 18 20 22

Index

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Conclusion
Time Domain optimization of eye diagram in ADS provides a powerful methodology to improve high speed memory design and to extract even fraction of the psec of timing margin buried in interconnects Substantial reduction in time needed to design and optimize of memory platform design is made (from weeks to hours) Guarantee maximal channel robustness Minimize Over/Under design risks Opportunities for future development Need to demonstrate IBIS model optimization such as driver strength, ODT etc.

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