Академический Документы
Профессиональный Документы
Культура Документы
Brahim Bensalem, Intel Corporation Lihua Wang, Agilent Technologies Sanjeev Gupta, Agilent Technologies
Agenda
Channel Complexity and Gaps in Current Design Flow Advantage of End to End Eye Centric Design Flow Why an Eye Diagram ? Eye Diagram Measurements in ADS. Optimization of DDR2 Channel. Introduction to Batch mode simulation ADS near term roadmap for DDR designs
Design Target
Eye Mask, TJ, SU/HD Margin, etc.
Design Target
Eye Mask, TJ, SU/HD Margin, etc.
Chanel Parameters
Impedance, Signal spacing, total length, Rtt, et.
Chanel Parameters
Impedance, Signal spacing, total length, Rtt, et.
No
Target Met?
End
Eye Diagram Measurements in ADS Page 3
Substantial gain in Channel Design Time (More than 3 weeks in our DDR2 case) Design is more robust since channel is optimized toward end to end channel performance Reduces risk of marginal design or opportunity loss due to over design
Eye level 1 & level 0 Eye rise/ fall time Eye opening Eye width Eye height Eye amplitude Peak to peak & RMS jitter
Delay Effect
Eye Diagram
Binning Data
Histogram Plots
Histogram can be created for any portion of eye diagram
Histogram across amplitude axis provide distribution around level one and zero
Eye Delay
Why delay calculation is required
Delay calculation is required for automated eye parameter measurements Binning the eye diagram makes this calculation easy
Calculated Delay
Mean value of horizontal histogram provide crossing time value Mean value of amplitude histogram provides crossing amplitude value
Eye Amplitude
Eye Height
1 3 3 1
Eye Amplitude = Level One Level Zero Eye Height = (Eye level one- 3)- (Eye level zero+3) Eye S/N= (Eye level one-Eye level zero) 1 level one+1 level zero 0% 40% 60% 100%
Measurement boundaries
Introduction to Optimization Time domain Optimization and why it is difficult Optimization of DDR2 Channel
Optimization in ADS
Modify your Designs Automatically to Achieve Required Performance
Why Optimization? Parameter sweep often doesnt lead to an optimized designs Parameter sweeps requires usually large number of simulation when number of variables are large The use of Optimizers in a design process
Automatically change design parameter to meet design goals Categorized by their error function formulation Coarse design stages: Random optimizer, Random Minimax optimizer and Simulated Annealing optimizer Fine design stages: Gradient optimizer, Gradient Minimax optimizer, Quasi-Newton optimizer and Minimax optimizer
Changes in any reactive component during optimization will effect channel delay and optimization goals may no longer be applicable
: Random : 20 : 25 minutes
Performance Comparison
Before After
DataFileList
String List
The new palette will have four components: the batch simulation controller the DataFileList container the StringList container the NetlistIncludeList container
Eliminates requirement to write complex manual scripts Uses Sweep Plan or Sweep Module No limits on number of parameter sweep Allow sweeping of Touchstone files, connector models, netlist etc. Allow parameters to be defined in .csv format Enable complex measurements such as eye diagram under parameter sweep mode.
Eye Diagram Measurements in ADS Page 26
Simulation Results
Here only Rx corner cases was swept. Batch mode allows simulation of any combination of Tx/Rx corner cases and IBIS models
DDR Mesurements
vdd
+
T E
PU PC GC PD
IO
Di gO
vdd
+
T E
PU PC GC IO
R R1 R=R_dq Ohm ML1CTL_C dq_TL0 Subs t="DIMMSUB" Length=3 mm W=W mil Lay er=1 ML1CTL_C dq_TL1 Subst="DIMMSUB" Length=14.3 mm W=W mil Lay er=1
IBIS_IO IBIS11 Ibis File="u37y_800.ibs" ComponentName="MT47H32M16BN_CLP_3_neg25" PinName="K8" ModelName="DQ_FULL_800" SetAllData=y es DataTy peSelec tor=Ty p Us ePk g=y es
Var Eqn
IBIS_IO IBIS26 Ibis File="u37y _800.ibs" ComponentName="MT47H32M16BN_CLP_3_neg25" PinName="K8" ModelName="DQ_FULL_800" SetAllData=y es DataTy peSelec tor=Ty p Us ePk g=y es
v dd DQS_DRAM_0P
GC
DQS_DRAM_0N
Dig O
v dd
+
T E
PU IO_ NI PC GC IO_ I PD Di gO
R R7 R=R_dqs Ohm
IBIS_DIO IBIS8 Ibis File="u37y_800.ibs" ComponentName="MT47H32M16BN_CLP_3_neg25" PinName="E7" ModelName="DQ_FULL_800" SetAllData=y es DataTy peSelec tor=Ty p Us ePk g=y es
DQS_DRAM_1N IBIS_DIO IBIS27 Ibis File="u37y_800.ibs" ComponentName="MT47H32M16BN_CLP_3_neg25" PinName="E7" ModelName="DQ_FULL_800" SetAllData=y es DataTy peSelec tor=Ty p Us ePk g=y es
PD Dig O
ML2CTL_C dqs_TL2_2 Subs t="DIMMSUB" Length=2.9 mm W=W mil S=6.0 mil Layer=1 RLGC_File= Reus eRLGC=no
Page 31
PU
GC
PC
IO_ NI
VtPRBS VPRBS5 BitSequenc e="10101010" Vlow=0.0 V Vhigh=2 V EdgeShape=Linear Transition BitRate=0.75 GHz Ris eTime=10 ps ec FallTime=10 ps ec Delay =0 ps ec
IBIS_DIO IBIS24 Ibis File="v irtex5.ibs " ComponentName="VIRTEX-5_FF1136" PinName="20P" ModelName="SSTL18_I" SetAllData=y es DataTy peSelec tor=Ty p UsePk g=y es
ML2CTL_C dqs _TL0A1 Subs t="DIMMSUB" Length=3 in W=W mil S=6.0 mil Lay er=1 RLGC_File= Reus eRLGC=no
ML2CTL_C dqs _TL0 Subs t="DIMMSUB" Length=3 mm W=W mil S=6 mil Lay er=1 RLGC_File= Reus eRLGC=no
R R8 R=R_dqs Ohm
ML2CTL_C dqs_TL1 Subs t="DIMMSUB" Length=3 mm W=W mil S=6 mil Layer=1 RLGC_File= ReuseRLGC=no v dd DQS_DRAM_1P
PD
ML2CTL_C dqs _TL2_1 Subst="DIMMSUB" Length=2.9 mm W=W mil S=6.0 mil Lay er=1 RLGC_File= Reus eR LGC=no
PU
PD
PC
IO_ NI
IO_I
IO_I
DigO
D RAM_1
GC PC IO
PU
VtPRBS VPRBS4 Regis terLength=17 Vlow=0.0 V Vhigh=2 V EdgeShape=Linear Transition BitRate=0.75 GHz Ris eTime=10 ps ec FallTime=10 ps ec Delay =0 ps ec
ML1CTL_C PD Di gO dq_TL0A1 Subs t="D IMMSUB" IBIS_IO Length=3 in IBIS21 IbisFile="v irtex 5.ibs " W=W mil ComponentName="VIRTEX-5_FF1136" er=1 Lay PinName="12" ModelName="SSTL18_I" SetAllData=y es DataTy peSelec tor=Ty p Us ePkg=y es
v dd
PD
GC PC
Dig O
IO
PU
VtPRBS VPRBS3 Regis terLength=17 Vlow=0.0 V Vhigh=2 V EdgeShape=Linear Transition BitRate=0.75 GHz Ris eTime=10 ps ec FallTime=10 ps ec Delay =0 ps ec
IBIS_IO IBIS17 IbisFile="v irtex 5.ibs " ComponentName="VIRTEX-5_FF1136" PinName="12" ModelName="SSTL18_I" SetAllData=y es DataTy peSelec tor=Ty p Us ePkg=y es
v dd
Comprehensive reporting
2.15 2.10
SlewRSetupFall
2.05
2.00
1.95
1.90 0 2 4 6 8 10 12 14 16 18 20 22
Index
Conclusion
Time Domain optimization of eye diagram in ADS provides a powerful methodology to improve high speed memory design and to extract even fraction of the psec of timing margin buried in interconnects Substantial reduction in time needed to design and optimize of memory platform design is made (from weeks to hours) Guarantee maximal channel robustness Minimize Over/Under design risks Opportunities for future development Need to demonstrate IBIS model optimization such as driver strength, ODT etc.