CIRCUITS AND SYSTEMS (CAS-OULU)

Professor Juha Kostamovaara and Professor Timo Rahkonen,

Electronics Laboratory, Department of Electrical and Information Engineering, University of Oulu
juha.kostamovaara@ee.oulu.fi, timo.rahkonen@ee.oulu.fi
http://www.infotech.oulu.fi/cas

Background and Mission High Speed Integrated Circuits and Devices

The Circuits and Systems group consists of about 30 re- Time-to-digital Conversion based on Delay Line
searchers working at the Electronics Laboratory of the De- Interpolation
partment of Electrical and Information Engineering at the A high-resolution time-to-digital converter (TDC) with ~1.2
University of Oulu. Its main activity is in the field of elec- ps resolution and ~327 ms dynamic range was developed
tronic and optoelectronic circuit and system design. The in this work. The conversion is based on a 15-bit counter
primary implementations are based on various ASIC tech- running at 100 MHz and 13-bit interpolation. The two-stage
nologies. The main interest of the group is devoted to cer- interpolation consists of a 5-bit coarse flash delay-locked
tain novel circuit topologies and functional units, although line interpolation with a resolution of 312.5 ps and an 8-bit
the group is also interested in applications, especially in fine interpolation based on a cyclic time domain successive
the field of telecommunications and electronic/optoelec- approximation (CTDSA) method that resolves the residue
tronic measurements. with a binary search. The resolution of ~1.2 ps is achieved
The group’s work concentrates particularly on the develop- by controlling the size of the unit capacitances connected
ment of high speed electronic (analogue, mixed mode and as the load of the delay cells, which in turn controls the
optoelectronic) circuits and systems. The main research propagation delay difference between logic gates. The block
fields are: diagram of the TDC architecture and the chip photomicro-
graph are presented below.
• time-to-digital and digital-to-time converters, i.e. time
interval measurement devices and controllable delay gen-
erators
• timing discriminators, especially optical receivers and tim-
ing detection of the received optical pulse
• picosecond laser diode transmitters and high-speed, high-
current switches
• development of an all-electronic, room temperature THz
radiation source
• development of laser radar techniques, especially for in-
dustrial measurements, using the results of the above re-
search activities
• frequency synthesis with the emphasis on the DS fre-
quency synthesis method
• radio receivers and receiver architectures based on se-
lective (filtering) sampling techniques
• radio telecommunications including linearization of power
amplifiers, AD/DA conversion and baseband blocks
• development of integrated circuit structures, methods and
Block diagram of the TDC based on the successive ap-
solutions for the embedded testing of electrical products proximation method.
• low power/low voltage analogue and mixed-mode signal
processing blocks and their integrated circuit realizations.
The group has created a well-functioning partnership with
some international research units working in the same or in
a complementary field. The group is mainly funded by the
Academy of Finland, Tekes and industry. It has one gradu-
ate school position in the Graduate School in Electronics,
Telecommunication and Automation (GETA) and two in
the Infotech Oulu Graduate School.

Scientific Progress
In the following, details and results of the work of the group
are given in some important research fields. Chip photomicrograph of the TDC.

INFOTECH OULU Annual Report 2007 11

The rms single-shot precision, i.e. the standard deviation
or random error, achieved with the realized TDC is 3.7 ps
using an INL-LUT containing the measured integral
nonlinearities of the interpolators. The effect of the INL-
LUT is illustrated in the next figure. Due to the INL of the
interpolators the LSB distribution is distorted. The stan-
dard deviation of the distribution, i.e. single-shot precision,
is 5.7 ps without the INL-LUT. With the INL-LUT correc-
tion the distribution is Gaussian with a single-shot preci-
sion of 3.5 ps. The power consumption is 33 mW. The
prototypes were fabricated in a 0.35 mm CMOS process.
The layout area is 4.45 mm2.
Single-shot precision s-value with and without INL-LUT
correction.
A time-to-digital converter, which is based on low refer-
ence frequency, has been tested and the results are ready to
be published. The TDC reaches 10.6 ps RMS measurement
precision at time intervals from 0.8 ns to 1.0 ms. Precision
of 6.0 ps can be reached when collected measurement
nonlinearity is used to improve the measurement accuracy
(see the figure below). The measurement resolution is 9.645
ps. The TDC circuit utilizes a low 6 MHz reference clock,
which is multiplied inside the circuit with a recycling tech-
nique. No external calibration is needed for proper TDC
operation, which was the disadvantage in previously de-
signed TDCs. Measurement nonlinearity is less than 10 ps
with time intervals from 0.8 ns to 10 ns. With longer time
intervals the nonlinearity is below 3 ps. Temperature drift
is below 0.4 ps/°C and power consumption is 35 mW with
3.3 V operating voltage. The time digitizer represents the
state-of-the-art among integrated time-to-digital converters.
Single-shot precision measured over the interpolation time
cycle (upper curve: without nonlinearity correction, lower
curve: with nonlinearity correction).
12 INFOTECH OULU Annual Report 2007
Timing Detection
A new receiver channel topology for a pulsed time-of-flight
laser range finder has been developed. The timing detec-
tion is based on leading edge detection in the receiver chan-
nel. The receiver channel has been realized in a 0.35 mm
SiGe BiCMOS process and the measurements will be ac-
complished during the spring of 2008.
Typically, the disadvantage of leading edge detection is the
large walk error induced by the finite rise time of the laser
pulse and bandwidth of the receiver. The walk error can be
larger than a few of nanoseconds without any compensa-
tion. However, the amount of walk error generated in the
leading edge receiver channel can be compensated for if
the amplitude or the length of the timing pulse is known. In
the latter configuration, the walk compensation is realized
by measuring the length of the timing pulse with a TDC
and using this information for compensation. Thus the com-
pensation range is much wider compared to the compensa-
tion based on amplitude measurement because measuring
the pulse length is possible even if the receiver front end is
saturated.
The construction of the channel is shown in the figure be-
low. The transimpedance preamplifier utilizes a two-stage
differential amplifier as the internal amplifier. Noise and
bandwidth are important parameters to be optimized. Over-
load properies are also important since they define the be-
havior of the circuit after preamplifier saturation. Stability
is an issue, too, due to the long feedback across the pream-
plifier. The postamplifier is also a two-stage differential con-
figuration. The comparator consists of four voltage gain
stages and a master-slave type latch, and it gives CMOS-
level output.
Based on the post-layout simulations, the walk error in a
dynamic range of 1:1000 can be compensated for. The er-
ror in the uncompensated range (1000 : 100 000) will be
about ±75 ps. The bandwidth of the amplifier channel is
about 250 MHz, the transimpedance is 10 kOhm and the
minimum detectable signal is about 0.9 mA with the mini-
mum SNR of 10.
Block diagram of the leading-edge receiver channel.
Integrated Laser Radar Chip
A CMOS laser radar chip, including an optical receiver chan-
nel and a time to digital converter (TDC) integrated onto
the same die and realized in a 0.13 µm CMOS technology,
has been fabricated and tested. The receiver channel uses
leading edge detection, which makes it possible to achieve
a wide dynamic range. The compensation technique devel-
oped in this work utilizes the TDC integrated into the same
chip to perform a time domain compensation of walk error.
The compensation technique is based on measuring the slew
rate of the front edge of the pulse by using two comparators
with a different threshold, resulting in two timing marks for
the TDC, and then uses the known relationship of the walk
and SR.
The time-to-digital converter shown below consists of a 16-
phase free running ring oscillator, three timing channels
(START, STOP and STOPtr used for walk compensation),
a 10-bit counter, an accurate time generator (ACCURATE
TIME BASE) and a delay locked loop (DLL). The time
interval measurement result is combined with the result of
a counter that counts full clock cycles in the ring oscillator
between a start and stop pulse, and the results of registers
storing the state of the ring oscillator by means of the tim-
ing signals interpolated by parallel sub-gate-delay elements
(τ+nτ2). The parallel sub-gate-delay elements consist of four
adjustable buffers locked to the delay between two adja-
cent phases of the ring oscillator by the DLL. The resolu-
tion of the TDC is derived by dividing the period of the
ring oscillator by the number of its phases (16) and the num-
ber of the timing signals (4), giving the resolution of Tclk/
4*16.
Block diagram of a TDC.
The frequency of the ring oscillator, and hence the resolu-
tion of the TDC, is dependent on absolute temperature and
supply voltage. This dependence can be compensated for
by using an accurate time base to measure the resolution of
the TDC before an actual time interval measurement. The
delays of parallel sub-gate-delay elements are, however,
adjusted to be correct with a DLL.
The size of the layout of the whole receiver, including the
pad ring, is 1300 µm x 1300 µm. The operation frequency
of the ring oscillator was 1.1 GHz, giving a resolution (LSB)
of 14 ps (Tclk/(16*4) for the TDC corresponding 2 mm in
distance, when the total power consumption of the receiver
was approximately 30 mΩ. The nonlinearity of the TDC
was measured to be less than ±7 ps (±1 mm) over the input
time range of 5 ns - 100 ns (0.75 m - 15 m).
The bandwidth and the transimpedance of the channel were
300 MHz and 23 kW, respectively. The input referred rms
noise current was 95nA (Cd=1.5 pF). The uncompensated
walk error was about 2.2 ns in the input current range of 2
µA to 20 mA, while the use of the compensation reduced it
to less than ±30 ps.
The total accuracy of the receiver is better than ±5.5 mm in
the distance range of 0.75 m - 15 m. The single-shot preci-
sion of the whole receiver, including the precision of the
TDC is approximately 150 ps (~20 mm in distance) at the
minimum usable signal corresponding to an SNR of 25.
Superfast High-Voltage Switch based on a
GaAs BJT Structure
Interesting new results have lately been achieved in the
course of experimental and theoretical investigation of the
switching transient in specially designed and fabricated
GaAs avalanche transistors. A superfast (~200 ps) switch-
ing transient was experimentally observed and an original
physical interpretation of the phenomenon was suggested.
The superfast switching originates from the switching chan-
nel of a comb of moving and avalanching field domains of
ultra-high amplitude (c.f. the figure below). These domains
cause fairly homogeneous and extremely powerful carrier
generation along the whole length of the switching chan-
nel. An increase in the carrier density causes drastic reduc-
tion (“collapsing”) in the domain width thus reducing the
voltage across the device, while the domain amplitude re-
mains extremely high (by a factor of 2 to 3 higher than the
ionization threshold) thus supporting a powerful ionization
rate even at a reduced voltage across the transistor.
(a) – measured and simulated voltage and current across
GaAs avalanche transistor, (b) - simulated electric field pro-
files at various instants across the structure (along the
switching channels in the direction of the current flux); the
instants shown in (b) correspond to the time scale in (a).
This train of the collapsing domains appears due to the pres-
ence of negative differential mobility (NDM) at extremely
high (ionizing) electric fields. The electron transport in GaAs
beyond the ionization threshold is an open question, and
existing theoretical data are contradictory. We have started
work on Monte Carlo simulations of the electron transport
at an extreme field and its experimental verification in a
GaAs BJT operating in avalanche mode (the first figure).
A possibility for further acceleration in the switching tran-
sient and significant reduction in the residual voltage was
predicted in our latest simulations for a modified geometry
of GaAs transistor chip (the second figure). These practical
and important results are currently at the stage of experi-
mental verification.
INFOTECH OULU Annual Report 2007 13

(1-4) Dependence of electron velocity on the electric field
in GaAs obtained using an analytical Monte Carlo model
for different doping levels 1015 - 5×1018 cm-3. The gray-col-
ored curves A-C show the change from negative to posi-
tive differential mobility predicted earlier with account for
the X7 valley of the second conduction band, and curve 5
represents our Full Band Monte Carlo simulation results
with X7 valley included.
The collector voltage waveform during the switching of a
GaAs transistor, 1 – measured (and confirmed by the simu-
lations), 2 – simulated for a transistor with increased emit-
ter area.
Picosecond Laser Diodes
A prototype of a GaAs avalanche transistor was used for
the pumping of commercial laser diodes operating in the
gain-switching mode. The generated electrical pulses of 2-
10 A in amplitude, with the duration in the sub-nanosecond
range allowed optical pulses of 5W / 40 ps or, alternatively,
45W / 70 ps to be obtained using commercial laser diodes
consisting of one chip (75 µm in width) or three chips
(250 µm in width) respectively.
Much more impressive, record power density in the pico-
second lasing mode was obtained from a specially designed
and fabricated laser diode structure based on heavily doped
layers of a GaAs /AlGaAs system (c.f. the figure below).
This laser diode requires a commercial Si avalanche tran-
sistor for pumping, which makes this result very interesting
for applications. The physical mechanism responsible for
the laser operation is not quite clear yet. It is believed, how-
ever, that the main mechanism responsible for high optical
A 50W / 30ps optical pulse generated near the trailing edge
of the pumping current pulse at room temperature. The area
of the laser diode chip is 400 µm × 20 µm (length × width).
The peak optical power density of ~0.1 GW/cm2 at the mir-
ror is something of a record for picosecond laser diodes.
14 INFOTECH OULU Annual Report 2007
gain is the “field-assisted gain control”, which we have dem-
onstrated and patented earlier. Another apparently impor-
tant issue is the transformation of the absorption spectra
depending on the local doping.
THz Emission from a GaAs BJT Structure dur-
ing Its Avalanche Switching
Another very promising application for the avalanche
switching mode in GaAs BJT is the generation of pulsed
broadband terahertz emission. Periodical nucleation and an-
nihilation of ultra-narrow, ionizing domains is believed to
cause the THz emission observed in our experiment. The
measured emission power observed in the BJT operating in
pulsed ( ~2 ns) mode was rather high (in the sub-milliwatt
range), while even much higher power was predicted in the
simulations, see details below.
(a) - schematic presentation of the transistor chip and ex-
perimental setup; (b) - oscillograms of Si bolometer re-
sponses with different band-pass filters: 1- f < 0.3 THz (emit-
ted by transistor peak power ~150 µW); 2- f < 1 THz (peak
power ~100 µW), 3-f < 9 THz ; 4-f < 25 THz. The signal
presented by curves 3 and 4 correspond to black-body ra-
diation, while curves 1 and two show the emission from the
switching channels, (c) - measured (1,2) and simulated (3-
5) peak power for a “low voltage” (100 V) transistor; Curves
6-7 show the simulated emission power in different spec-
tral bands for a “high voltage” (300V) transistor; (6) corre-
sponds to band f < 0.3 THz, (7) to f < 1 THz and (8) to f <
3 THz.
Proper design of the transistor chip for THz emission ap-
plications should result in drastic improvement in the cou-
pling between the emitting channels and free space for the
total emission band of 100 GHz-3 THz. This gives grounds
to believe that a compact, high-power THz source can be
developed on the base of GaAs BJT.
Voltage-to-Current Converters
Work in this research area has concentrated on investigat-
ing the design of such voltage-to-current converter (VIC)
topologies that possess both high linearity and bandwidth
and are able to produce good performance also with a low-
voltage, mixed-signal CMOS-process, where many of those
properties of CMOS-transistors that are essential for good
analogue performance are sacrificed to facilitate high-speed
and low power consumption of digital circuitry. The inter-
est for the studied circuits arises, for example, from the
possibility to use them as a part of such sub-sampling re-
ceiver structures in which an RF-signal is processed in the
current domain in such a way that some key requirements,
such as a low noise figure and high image rejection, are
met with a structure, whose requirements for semiconduc-
tor process are well in line with those set by the digital
circuitry that is now embedded in high-performance radio
receivers in massive quantities, and whose optimization thus
tends to dictate the process selection.
Besides noise level, current-mode sub-sampling receiver
structures set tight requirements on the linearity of the
needed gm-element. The high linearity and bandwidth of
the V-I conversion topologies studied here is achieved by
means of a highly linear, low-gain current mode feedback
loop. An example for a topology in which such an approach
to linearity improvement is used is shown in the figure be-
low. Due to the linearity of feedback, only a relatively low
amount of gain is needed at the feedback path to produce a
substantial reduction in distortion level. Since the gain is
realized in the current domain, the Miller-effect and the
resulting enhancement of certain nonlinear capacitive leak-
age currents that usually limit the performance of high-band-
width VIC’s are avoided to great extent. Hence, the property
of the applied feedback principle enables the realization of
very high conversion bandwidth. Apart from high band-
width, the reliance of the operation on current mode feed-
back also makes it possible to use various distortion
cancelling structures.
VIC with current mode feedback; topology and most es-
sential currents.
The topology enables the reduction of the second order dis-
tortion currents when the operating range is below 10 MHz,
by adding a resistor to the feedback loop. Another compen-
sation technique is to cancel the third order intermodulation
(IM3) distortion currents by adding a compensating circuit
that has the same amplitude of the IM3 distortion current
with the opposite phase.
To verify the functionality of the current feedback converter
topology, two converters with the different kinds of distor-
tion cancellation techniques mentioned above were manu-
factured in a 0.13 µm BiCMOS process. Also two refer-
ence converters without compensating circuits were added
to the chip. Measurement results show full functionality of
the developed circuit techniques. The Gm of the circuit is
125 µS and its OIP3im is -48 dBA up to 90 MHz. The
circuit was fabricated in 0.13 µm CMOS technology and
consumed 1.1 mA from a 1.2 V supply. The core area of the
Gm cell was 1.500 µm2.
Embedded RF Testing for Telecommunica-
tions
The work of the embedded testing research group at the
electronics laboratory can roughly be divided into two main
branches which deal with different phases of the life cycle
testing of electrical products. The first category of projects
deals with the testing issues encountered during the manu-
facturing of products. The second group of projects aims to
develop techniques and circuit structures needed to imple-
ment embedded testing at the system level and specifically
inside integrated circuits. These circuit structures embed-
ded inside the ICs may then be used to test the functionality
of the ICs themselves, the surrounding (discrete) electron-
ics and the whole system at any time during the life cycle of
the product.
Production Testing
The main idea in this group of projects has been the re-
placement of general-purpose and expensive RF measure-
ment instruments at the test station on the manufacturing
line by custom made low-cost measurement instruments.
For example, the developed simplified network analyzer
shown in the next figure, with its accompanying software,
will allow the testing of multi-band antennas for mobile
phones on the factory floor. This device offers RF magni-
tude response measurement capability from 600 MHz to
2.7 GHz, with high frequency and amplitude precision (the
coefficients of frequency and amplitude correlation between
the results obtained with the device and with the network
analyser were in the range 0.989 - 0.997). Measurements
with three-band antennas revealed that the device offers a
potential alternative to a network analyzer in the produc-
tion line. Although the absolute accuracy is not as good as
that of a network analyzer, the device gave comparable re-
sults to those of the latter in a production line context where
measurements are typically comparative in nature.
The developed simplified network analyser for antenna
measurements.
INFOTECH OULU Annual Report 2007 15
Life Cycle Testing
These projects have developed a number of basic building
blocks, which enable the integration of tests as part of IC
circuits. These IC blocks provide functions such as virtual
probes (switches), IEEE 1149.4-type high-frequency ana-
logue boundary modules (RF-ABM), integrated RF power
reference, supply quality and bypass monitoring and built-
in tests of AD and DA converters. These basic functions
serve many of the test needs encountered during the plan-
ning of individual projects. Some of the developed struc-
tures have been used to demonstrate the feasibility of
embedded testing (RF-ABM IC used to test an I/Q direct
modulation RF transmitter).
The REMTEST-project (in co-operation with the Optoelec-
tronics and Measurement Techniques Laboratory and the
Microelectronics and Materials Physics Laboratories) gath-
ers together the results and findings of the developed IC
building blocks in a real-life context. The aim of this project
is to build a real-life demonstration “product” with an em-
bedded test solution built using the developed IC building
blocks. This “product”, shown below, will include an em-
bedded test of low-frequency analog circuit, embedded test
of RF electronics and embedded testing of a micro com-
puter. The test solution will be built using the IEEE 1149.4
architecture with an embedded (PCB-level) test controller
and test equipment (ATE). The project also extends the idea
of life cycle testing to the realm of predictive diagnostics of
BGA joints and the 1st implementation of a Universal Test
Communication Standard (UTCS) compatible device. Pre-
dictive BGA joint diagnostics allows the detection of im-
minent solder joint failure under a ball grid array type IC
package and the UTCS allows test control and data com-
munication through a network using standardized command
language currently under development in the Oulu area.
REMTEST reference device and an example remote user
interface to embedded tests.
16 INFOTECH OULU Annual Report 2007
Development of BIST Techniques for AD Con-
verters
Traditional testing of analog-to-digital converters (ADCs)
with automatic test equipment is time-consuming and ex-
pensive, and a built-in self-test (BIST) can be one solution
to this problem. Most of the proposed BIST routines re-
quire a well-known test stimulus which is much more lin-
ear than the device under test. A stimulus error identification
and removal (SEIR) method that does not require a high-
linearity stimulus has been proposed recently, and it is evi-
dent that reliable test results could be achieved with stimulus
linearity lower than the required measurement accuracy. As
a result of the research carried out in the CAS group in this
field, a simple and easy-to-implement calculation algorithm
for use with the stimulus-identification method has been
developed. With this method it is possible to test the linear-
ity of ADCs without highly linear or pure test simulus. Simu-
lations predict that the INL of 16-b ADCs can be measured
with an accuracy of 0.5 LSB using only 75 dBc pure sinu-
soidal test stimulus, while a standardized histogram test
method requires over 105 dBc pure test stimulus.
Research on Linear RF Power Amplifiers
The group has for several years been doing basic research
to aid the design of high efficiency linear RF transmitters.
Recently, the emphasis has been on supply-modulated trans-
mitters based on envelope tracking (ET) and envelope elimi-
nation and restoration (EER).
Detailed Distortion Analysis Techniques
The group has previously developed two Volterra analysis
tools for detailed study of the contributions and cancella-
tion mechanisms that result in the total distortion in an ana-
log circuit: an in-house Matlab simulator using user-supplied
polynomial models, and a combined model fitting and
Volterra analysis tool implemented on top of the harmonic
balance simulation (VoHB, Volterra on Harmonic Balance)
and using the command language of a commercial circuit
simulator Aplac. Here normal nonlinear device models are
used to fit the polynomial models and calculate the various
mixing gains from one harmonic band to another. The former
is being reported as a licentiate thesis, the latter one formed
the doctoral thesis of Janne Aikio, who successfully de-
fended his thesis in May 2007. The next figure shows an
example of distortion contributions on the collector of an
HBT amplifier, when second harmonic impedance is tuned.
The mixing results from 2nd harmonic cancels IM3 better,
resulting in reduction of overall distortion.
Example of the effect of impedance tuning in an HBT. Left,
a non-optimised; right, optimised impedance at 2nd harmonic,
resulting in better cancellation of different distortion com-
ponents.
T. Rahkonen is a member of the FENICS (First European sion. Also, a drive aiming for maximum power efficiency
Network for Industrial Circuit Simulation) precompetitive at each given signal level was experimented. In all of these
consortium that during spring 2007 completed a STREP cases, most of the adjacent channel distortion was caused
proposal for FP7. This joint project of NXP Semiconduc- by strong AM-PM, which is caused as follows: normally,
tors, Qimonda, Magwel N.V., AWR-Aplac, Univerisity of the amplifier stays in compressing from the maximum sup-
Wuppertal, University of Köln, University of Oulu, and ply voltage down to the minimum supply voltage of ca. 1.5
Fachhochschule Öberösterreich was accepted, and a 30- V. Below this, the amplifier departs from compression, when
month project started in February 2008. The CAS group also a pronounced phase shift is seen. Hence, all the above
will continue to improve and refine the Volterra-on Har- supply drive techniques need AM-PM predistortion to clean
monic Balance simulation technique. up the output spectrum. The next figures show plots of the
power efficiency curves vs. signal amplitude and supply
Development of High Efficiency Transmitters voltage, and the output spectra obtained by the four differ-
The power efficiency of class A or AB linear amplifiers is ent supply drive functions, respectively.
modest, or even poor, if the ratio between peak power and
average power (so-called crest factor) is high – this is the
case in multi-carrier transmissions, for example. There are
two main methods for improving the power efficiency of
the transmitter: either to allow weak compression and can-
cel the generated nonlinearity using predistortion, or modu-
late the power supply according the signal amplitude. During
2007, research was funded by the Academy of Finland and
concentrated on studying supply-modulated transmitters.
The principle of such a transmitter is shown below. In an
EER transmitter, the power amplifier is a switch-mode am-
plifier, and all the amplitude information is set by the power
supply. In an ET transmitter, a linear amplifier is used.
Measured constant-efficiency (PAE %) contours vs. signal
Previous experiments on using a class E switch-mode am- amplitude and supply voltage in the envelope tracking am-
plifier in an EER transmitter were reported in 2007 in an plifier. Trajectories of two linear (red and square), constant
article accepted in the Springer journal on Analog Integrated gain (circles), and maximum efficiency (blue) supply drives
Circuits. To gain experience in ET transmitters, a 0.5W, are shown as an overlay.
6V, 1 GHz LDMOS RF power amplifier was designed and
implemented. Here a linear, class AB amplifier is held at
the edge of saturation at all amplitude levels. A design pro-
cedure for such an amplifier had to be devised: during the

Measured output spectra of a supply-modulated class AB

amplifier, showing the effects of various supply drive func-
tions and the importance of AM-PM correction.
Polar transmitter test setup.

design, the supply voltage, input level and input frequency
were constantly swept when iterating the design in a 1-tone
harmonic balance simulation. The strongly voltage depen-
dent output capacitance of the LDMOS caused consider-
able shift in the gain peak frequency, increasing the AM-AM
error of the amplifier.
Based on the simulations, the preliminary idea was to hold
the amplifier constantly in a 1-dB compression point down
to 1.5 V supply voltage. However, in the practical tests,
various supply drive functions were experimented. As the
amplifier had quite large AM-AM distortion (the gain was
expansive), a constant-gain drive appeared to be a much
better choice than staying in a constant degree of compres-
During 2007, completely non-formal co-operation with the
Technical University of Trondheim was begun. TUT has
access to the GaAs PHEMT process of Triquint, and a 3 W,
1.65 GHz inverted class E amplifier for Inmarsat satellite
telephone specifications was designed in December 2007 /
January 2008. Especially the integrated output parallel reso-
nator was somewhat difficult to design, as it has to with-
stand rms currents of 5 - 7 amperes. An additional interesting
design issue to be probed further is that the power efficiency
of a switched mode amplifier is very sensitive to any over-
lapping of voltage and current waveforms. Filtering on the
gate side, and careful layout techniques were used to avoid
overlapping.

INFOTECH OULU Annual Report 2007 17

Analysis of Switch-Mode Circuits
The need for efficient analysis techniques of switch-mode
power supplies arises when designing a supply modulator
for the polar transmitter setup. During 2007, a journal pa-
per on the developed quick simulation technique of a modu-
lated switcher was written and accepted to the Springer
journal on Analog Integrated Circuits. The technique is
based on linear state matrix presentation, where settling
within any sampling period can be calculated without itera-
tion. The design experience with switch-mode power sup-
plies was enhanced by writing Matlab software that takes a
description of any switched circuit and performs all the Multi-bit variable modulus quantizer.
normal averaged, transient and linearized open and closed-
loop analyses. The program was reported at the ECCTD The desired spectral purity has been guaranteed according
conference in Seville in August 2007. to our earlier method published in the IEEE TCAS II jour-
nal in 2005. The variable modulus DSM has been designed
Digital Delta-Sigma Modulation in Radio Fre- to produce output sequences of the desired length, for ev-
quency Synthesis ery DC input. This approach allows trading the amount of
the DSM hardware for the average level of noise. In effect,
The work in this field has been focused on modelling and
it allows selecting the most compact implementation for a
architectural innovations of digital delta sigma-modulators
given telecommunication standard. The figure below shows
(DSMs). In this work, a general family of digital DSMs
the variable modulus DSM spectrum for all DC inputs. The
which are particularly well suited for multi-standard radio
spectrum corresponds very closely to an idealized, linear
transmitters and receivers has been developed. They can be
DSM model.
used in PLL frequency synthesis to multiply a stable oscil-
lator frequency by any rational number. As a result, the fre-
quency synthesizer can generate precise sequences of
frequencies with absolute accuracy. Previous solutions only
approximate desired frequencies, with accuracy dependant
on the amount of DSM hardware.
In this study, we have generalized the concept of coarse
quantization in the fixed-point digital domain. This allowed
constructing a DSM with a variable modulus quantizer pre-
sented in the figure below.

Output signal spectra (variable modulus DSM simulated for

all DC inputs)

Low Voltage / Low Power Analogue Circuit

First order variable modulus DSM.
The presented first order DSM has two inputs: xn for the
data and Q for the modulus. The modulus Q can be changed
at any time during modulator operation. The input Q is used
to select a different series of frequencies for a different tel-
ecommunication standard. The proposed general modifi-
cation converts any digital DSM into a variable modulus
DSM. The solution easily scales to various DSM topolo-
gies. The next figure presents a multi-bit variable modulus
quantizer.
The variable modulus quantizer is parallel in nature, and
therefore adding more quantization steps does not affect
the maximum operating frequency. Variable modulus func-
tionality adds a certain amount of asynchronous hardware
to the construction of the quantizer, but allows implement-
ing the DSM with a much smaller bus width. The proposed
solution has been recently published in the IET Electronic
Letters journal.
Techniques
The work in this field has concentrated on developing low
power circuit blocks and systems for portable applications.
The focus has been on improving class AB amplifier con-
trol circuits and power supply noise rejection performance
for low-power low-voltage class AB operational amplifi-
ers, which is important when operational amplifiers are op-
erated in a noisy mixed signal environment or directly from
battery. The CAS group has been involved also in
nanotechnology related projects, where several measuring
instruments for low-level measurements have been designed
and built. These include a Faraday pail for measuring fixed
charge (e.g. in coating material for printing paper), a scan-
ning charge measurement circuit to study the spatial distri-
bution of fixed charges on paper (this was reported in the
Norchip conference, November 2007), and a force mea-
surement system based on controlling the oscillation am-
plitude of a mechanically loaded 32 kHz tuning fork shaped
crystal oscillator.

18 INFOTECH OULU Annual Report 2007

Personnel Borkowski M & Kostamovaara J (2007) Variable modulus delta-
sigma modulation in fractional-N frequency synthesis. Electron-
ics Letter 43(25), 2 p.
professors & doctors 9 Kursu O, Riikola M, Aikio J & Rahkonen T (2007) Polynomial
2.1 GHz RF predistorter IC with envelope injuction output. Ana-
graduate students 24 log Integrated Circuits and Signal Processing, 50:13-20.
others 7 Kostamovaara J & Määttä K (2007) Time interval measurement.
Wiley Encyclopedia of Electrical and Electronics Engineering.
total 40 Vainshtein S, Kostamovaara J, Shestak L & Sverdlov M (2007)
Method of generating optical radiation, and optical radiation
person years 30 source, Russian patent no. 2306650.
Harju H, Rautio T, Hietakangas S & Rahkonen T (2007) Enve-
lope tracking power amplifier with static predistortion lineariza-
External Funding tion. European Conference on Circuit Theory and Design, August
26-30, Sevilla, Spain, 388-391.
Hietakangas S, Rautio T & Rahkonen T (2007) Feedthrough can-
Source EU R cellation in a class E ampilied polar transmitter. European Con-
ference on Circuit Theory and Desing, August 26-30, Sevilla,
Academy of Finland 405 000 Spain, 591-594.
Ministry of Education 73 000 Korhonen E & Kostamovaara J (2007) Simple method for linear-
ity testing of ADCs using non-linear test stimuli. 13th IEEE In-
Tekes 272 000 ternational Mixed Signals Testing Workshop and 3rd Intgernational
GHz/Gbps Test Workshop (IMSTW/GTW 2007), June 18-20,
domestic private 184 000 Povoa de Varzim, Portugal, 184-189.
Loikkanen M & Kostamovaara J (2007) Capacitor-free CMOS
EU + other international 38 000 low-dropout regulator. IEEE International Symposium on Circuits
and Systems (ISCAS 2007), May 27-30, New Orleans, LA, USA,
total 972 000 1915-1918.
Rahkonen T (2007) Matlab tool for analysis of switch-mode power
supplies. European Conference on Circuit Theory and Design,
Doctoral Theses August 26-30, Sevilla, Spain, 902-905.
Rytky H, Rapakko H & Kostamovaara J (2007) Wide bandwidth
Aikio JS (2007) Frequency domain model fitting and Volterra
transconductor with current mode feedback. International Sym-
analysis implemented on top of harmonic balance simulation. Acta
posium on Integrated Circuits 2007 (ISIC 2007), September 26-
Universitatis Ouluensis C 272.
28, Singapore, 299-302.
Vainshtein S, Kostamovaara J, Lantratov V, Kaluzhniy N &
Selected Publications Mintairov S (2007) High-power picosecond laser diodes based
Rapakko H & Kostamovaara J (2007) On the performance and on different methods of fast gain control for high-precision radar
use of an improved source follower buffer. IEEE Transactions on applications. Microtechnologies for the New Millennium 2007,
Circuits and Systems - I: Fundamental Theory and Applications May 2-4, Gran Canaria, Spain, (Proc. of SPIE on CD-ROM), Vol.
54(3): 504-517. 6593, 8 p.
Binici H & Kostamovaara J (2007) Layout preferences concern- Kursu O, Riikola M, Aikio J & Rahkonen T (2007) Polynomial
ing matching in a fully differential DS modulator design. Analog 2.1 GHz predistorter IC with envelope injection output. Springer
Integrated Circuits and Signal Processing 50(2): 95-103. Journal on Analog integrated circuits and signal processing
50(1):13-20.
Vainshtein S, Kostamovaara J, Yuferev V, Knap W, Fatimy A &
Diakonova N (2007) Terahertz emission from collapsing field do- Rautio T, Harju H, Hietakangas S & Rahkonen T (2007) Effects
mains during switching of a gallium arsenide bipolar transistor. of different VDD-drives in ET and EER transmitters. 25th IEEE
Physical Review Letters, PRL 99 176601, 4 p. Norchip conference, November 19-20, Aalborg, Denmark, 4 p.
Lyöri V, Kilpelä A, Duan G, Mäntyniemi A & Kostamovaara J Kursu O, Kivijakola J, Pudas M & Rahkonen T (2007) Surface
(2007) Pulsed time-of-flight laser radar for fiber-ptic strain sens- charge detection probe. 25th IEEE Norchip conference, Novem-
ing. Rev. of Sci. Instr. 78 (024705), 8 p. ber 19-20, Aalborg, Denmark, 4 p.
Korhonen E, Häkkinen J & Kostamovaara J (2007) A robust al-
gorithm to identify the test stimulus in histogram-based A/D con-
verter testing”, IEEE Transactions on Instrumentation and
Measurement 56(6), 6 p.

INFOTECH OULU Annual Report 2007 19