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PART 2
Ms. S. Launders
Oct. 2004
www.mee.tcd.ie/~launders
Recommended Text:
http:/www.mhhe.com/engcs/electrical/rizzoni
Also,
Table of Contents
TABLE OF CONTENTS ............................................................................................... 52
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2E6 Digital Electronics
COMBINATIONAL ICs
There are several combinational circuits that are available as Integrated Circuits ( ICs ). These ICs
perform specific digital functions commonly needed in the design of digital systems. These include
Adders and Subtractors as well as Comparators, Decoders, Encoders, Multiplexers, and PROMs (
Programmable Read-Only Memory ). These ICs are used extensively as building blocks in most
digital systems.
The internal operation and the use of both Adder and Subtractor ICs has already been demonstrated.
This section will introduce standard Multiplexers, Demultiplexers and Memory devices. (ref: Section
13.5, Rizzoni)
MULTIPLEXER
A multiplexer (MUX) is a device which accepts data from a number of sources and selects one of
these sources to be switched to a single output line.
Ex. a number of remote sensors may be monitored sequentially using a MUX. This simplifies the
wiring which must be fed to the monitor. (ref: pg 651-652, Rizzoni)
A D0 D1 f
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1 f = AD 1 + AD0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
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2E6 Digital Electronics
'A' is an ADDRESS or CONTROL line and it's logic state determines whether data present at D0 or
D1 is passed to the output.
ADDRESS LINES
D3
The address lines A and B determine which data lines D0 .. D3 connected to the O/P.
f = ABD0 + ABD1 + A BD2 + ABD3
i.e. for each combination of A and B there is only one associated I/P line.
Step 1:
Choose your Select lines.
Factor out 2 variables using a 4 I/P MUX (say A, B are taken as the address or control variables).
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2E6 Digital Electronics
ENABLE
D0 00
f
D1 01
D2 10
f
D3 11
A B
Step 2 :
Find 'residues' by examining the given eqn. WRT each factor combination AB,
AB, AB, and AB.
I/P ADDRESS OTHER VARIABLES
D0 AB
D1 AB
D2 AB
D3 AB
Step 3 :
Simplify the 'residues'
Step 4:
Draw the circuit.
Implementation looks like E
1 00
f
4 I/P MUX
C 01
1 10
f
11
0
A B
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2E6 Digital Electronics
Ex 16
Step 2 :
Find the 'residues' for each combination of the Select lines.
I/P ADDRESS OTHER VARIABLES
Step 3 :
Simplify the 'residues'
Step 4 :
Draw the circuit.
En
000
001
f
010
011
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A B C
2E6 Digital Electronics
Comparing Devices :
Implement the following function using a 4 I/P MUX and compare how it may be realized using
NAND gates.
f = AC + BC + AB
(i) By expanding each term to the canonical form and omitting duplicated terms we obtain
(i.e Steps 1,2 & 3)
f = AC(B + B) + BC(A + A) + AB(C + C)
= AB(C) + AB(0) + AB(1) + AB(C)
A B
(ii) Nand/Nand cct:
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2E6 Digital Electronics
Note that implementation by conventional means necessitates the use of at least two packages, as 74
series packages are commonly available with either four 2-input gates or three 3-input gates. MUX
implementation requires only one package containing two 4-input MUXs. This represents a
reduction in cost despite the fact that the MUX package is more expensive than the NAND gate
package.
An example of how the simple MUX can be extended to provide 4-bit capability is shown below.
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2E6 Digital Electronics
DEMULTIPLEXER
A demultiplexer (DMUX) works in opposite fashion to a multiplexer. The circuit has a single input
that can be routed to any one of several outputs. Again, a set of data-select inputs are used to
determine which output is to receive the incoming data. A typical application of a DMUX used for
data routing is shown below.
D/A
Converter
Buffer
Ch 1
Data
Comm. Register
Port Ch 2
Bus
DMUX
Micro-
Controller 4-Ch
8-Bit Ch3
Address Interface
A1 A1
A0 A0 Ch4
Lines Adapter
Data
Memory
Sometimes it is necessary to send data from many different devices a considerable distance and have
the data arrive on separate lines. In this case, a multiplexer in conjunction with a demultiplexer is
useful. A practical example for multi-channel data routing is shown overleaf :
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Source Dest.
1 1
Ch 1 Ch1
Source Dest
MUX DMUX
2
2
Ch2 Data Ch2
OUT IN
Source Ch3 Link Ch3 Dest
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3 3
Ch4 Ch4
Source A A Dest
En A 1 A0 En 1 0
4 4
TXN RXN
Sync
Timing Timing
+Control Line +Control
2E6 Digital Electronics
MEMORY
MICROCOMPUTER SYSTEMS
All computers from the smallest micro to the largest mainframe consist of three main sections as
shown below.
Central
Memory processing Input/Output
Unit (CPU)
The CPU is the heart of the computer. It is responsible for executing instructions within a program
and for performing the logical and arithmetic operations that it involves.
MEMORY consists of a large number of registers which are used to store both PROGRAMS and
DATA. Each memory register is given its own unique identifying number or ADDRESS. Typical
small computers will have several thousands of such memory locations. Large mainframe computers
will have millions or thousands of millions.
Semiconductor memories
A digital computer will have some main storage medium such as magnetic disk or tape for storing
user software and files. However, for processing it will use electronic memories. These are classified
as ROMs (read-only memories) and RAMs (random-access memories).
Once programmed, a ROM can only be read from - data cannot be written into it. On the other hand
data can be both written into and read from a RAM.
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2E6 Digital Electronics
Semiconductor ROMs are manufactured with bipolar technology (such as TTL) or with MOS (metal
oxide semiconductor) technology. The various categories are shown below. The mask ROM is the
type in which data are permanently stored in the memory during the manufacturing process. The
PROM is the type in which the data are electrically stored by the user. Note that the EPROM
(erasable PROM) is strictly a MOS device.
(ref: pg 653, also EPROM pg 654, Rizzoni)
ROM
The ROM is realised in matrix form in which each crossover point may be joined by a
semiconductor device during the fabrication process. The figure below illustrates a 4x2 ROM in
which 4 of the 8 crossovers are joined by diodes. A0 – A1 are address lines. Columns D0 and D1
are the O/Ps.
00
A0 X
Address 01
A1 Y Decoder 10
11
D0 D1
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2E6 Digital Electronics
In practice ROMs are much larger than 4x2. A device such as a 1024 x 4 ROM is realised as shown
in the figure below. The address decoder has 10 I/P lines enabling 1024 (210) row lines to be
addressed.
A0
1024
Decoder
row
Adress
1024x4
lines ROM
(internal
to IC)
A9
D0 D1 D2 D3
Identical ROMs can be cascaded to provide an expanded memory. An example of how 2 off 32x4
ROMs may be connected to make a 32x8 ROM is given below.
A0
A1
32X4 32X4
A2 ROM ROM
A3
A4
D0 D1 D2 D3 D4 D5 D6 D7
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2E6 Digital Electronics
ROM applications:
Instead of using individual gates to realise Boolean sums of products, they can be generated using a
ROM. In the example below an 8x4 ROM has the capability of producing 4 words W0-W3, each
containing any or all of the 8 minterms associated with three I/P variables ABC. For example when
ABC =000, A BC = 1 and row 0, exclusively, will be at logical 1. With a diode at the crossover of
row 0 and column W0, then W0 = 1 when ABC = 000. Similarly there is a diode on row 5 of column
W0 so when ABC =101 (i.e. A BC = 1 ), Then W0 = 1. Therefore:
W 0 = A BC + ABC
In a similar manner W1, W2 and W3 can be made into sums of minterms. Benefits in using a ROM
in this manner include savings in the number of gates needed and ease of implementing changes in
logic requirements by simply replacing the ROM. This is a particularly attractive option if a PROM
is used.
A 1
3
B Address
Decoder
4
C 6
W0 W1 W2 W3
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2E6 Digital Electronics
Ex. 17 Design a BCD to Excess-3 code converter using 10 rows of a 16x4 ROM as
illustrated in the figure below.
2) Draw the circuit diagram (including both the ADDRESS DECODER and the FUSE MAP)
5) Place diodes ( or fusible links, or transistors ) connecting this output to each minterm associated
with it
6) Repeat steps 4 and 5 for each individual output until the design is complete
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2E6 Digital Electronics
0
B3 1
2
3
Address
B2
Decoder 4
5
6
B1 7
8
9
B0
E3 E2 E1 E0
** Repeat this design using Nand/Nand Logic, Nor/Nor Logic, and Multiplexers. Comment on the
relative efficiency of the 4 implementations. **
A ROM may be used as a LOOK-UP TABLE f or a trig or exponential function. A number at the
address I/P could be converted into a sine, square or other function of the number at the O/P.
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2E6 Digital Electronics
Vcc
ROW line
Fusible link
Column line
The fuses may be blown by passing a few milliamps of current through them (the same as in a
PROM). Shining UV light on them for 10 to 20 minutes can reconnect the fuse allowing the device
to be reprogrammed.
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2E6 Digital Electronics
RAM provides temporary storage of data and can be thought of as a scratch pad, while ROM can be
regarded as a look-up table. The figure below illustrates how parallel register can be operated as a
RAM. Data on the input lines Di0 – Di3, will only be written in when the MW (memory write)
terminal is set to 1. The data can only be read out when the MR (memory read) terminal is set to 1.
Di3 D
DO3
Ck
D i2 D
DO2
Ck
Di1 D
DO1
Ck
Di0 D
DO0
Ck
MW
MR
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2E6 Digital Electronics
ROW
COL/DATA
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2E6 Digital Electronics
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