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DATA SHEET
74HC4052; 74HCT4052
Dual 4-channel analog multiplexer,
demultiplexer
Product specification 2003 May 16
Supersedes data of 1997 Aug 27
Philips Semiconductors Product specification
FEATURES DESCRIPTION
• Wide analog input voltage range from −5 V to +5 V The 74HC4052/74HCT4052 are high-speed Si-gate
• Low ON-resistance: CMOS devices and are pin compatible with the
HEF4052B. They are specified in compliance with JEDEC
– 80 Ω (typical) at VCC − VEE = 4.5 V standard no. 7A.
– 70 Ω (typical) at VCC − VEE = 6.0 V
The 74HC4052/74HCT4052 are dual 4-channel analog
– 60 Ω (typical) at VCC − VEE = 9.0 V multiplexers or demultiplexers with common select logic.
• Logic level translation: to enable 5 V logic to Each multiplexer has four independent inputs/outputs
communicate with ±5 V analog signals (pins nY0 to nY3) and a common input/output (pin nZ). The
• Typical “break before make” built in common channel select logics include two digital select
inputs (pins S0 and S1) and an active LOW enable input
• Complies with JEDEC standard no. 8-1 A (pin E). When pin E = LOW, one of the four switches is
• ESD protection: selected (low-impedance ON-state) with pins S0 and S1.
– HBM EIA/JESD22-A114-A exceeds 2000 V When pin E = HIGH, all switches are in the
high-impedance OFF-state, independent of pins S0 and
– MM EIA/JESD22-A115-A exceeds 200 V.
S1.
• Specified from −40 to +85 °C and −40 to +125 °C.
VCC and GND are the supply voltage pins for the digital
control inputs (pins S0, S1, and E). The VCC to GND
APPLICATIONS ranges are 2.0 to 10.0 V for 74HC4052 and 4.5 to 5.5 V
• Analog multiplexing and demultiplexing for 74HCT4052. The analog inputs/outputs (pins nY0 to
nY3 and nZ) can swing between VCC as a positive limit and
• Digital multiplexing and demultiplexing VEE as a negative limit. VCC − VEE may not exceed 10.0 V.
• Signal gating.
For operation as a digital multiplexer/demultiplexer, VEE is
connected to GND (typically ground).
FUNCTION TABLE
INPUT(1)
CHANNEL BETWEEN
E S1 S0
L L L nY0 and nZ
L L H nY1 and nZ
L H L nY2 and nZ
L H H nY3 and nZ
H X X none
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care.
2003 May 16 2
Philips Semiconductors Product specification
TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
74HC4052 74HCT4052
tPZH/tPZL turn-on time E or Sn to Vos CL = 15 pF; RL = 1 kΩ; 28 18 ns
VCC = 5 V
tPHZ/tPLZ turn-off time E or Sn to Vos CL = 15 pF; RL = 1 kΩ; 21 13 ns
VCC = 5 V
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per switch notes 1 and 2 57 57 pF
CS maximum switch capacitance independent (Y) 5 5 pF
common (Z) 12 12 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ[(CL + CS) × VCC2 × fo] where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CS = maximum switch capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ[(CL + CS) × VCC2 × fo] = sum of the outputs.
2. For 74HC4052 the condition is VI = GND to VCC
For 74HCT4052 the condition is VI = GND to VCC − 1.5 V.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER TEMPERATURE
PINS PACKAGE MATERIAL CODE
RANGE
74HC4052D −40 to +125 °C 16 SO16 plastic SOT109-3
74HCT4052D −40 to +125 °C 16 SO16 plastic SOT109-3
74HC4052DB −40 to +125 °C 16 SSOP16 plastic SOT338-1
74HCT4052DB −40 to +125 °C 16 SSOP16 plastic SOT338-1
74HC4052N −40 to +125 °C 16 DIP16 plastic SOT38-9
74HCT4052N −40 to +125 °C 16 DIP16 plastic SOT38-9
74HC4052PW −40 to +125 °C 16 TSSOP16 plastic SOT403-1
74HC4052BQ −40 to +125 °C 16 DHVQFN16 plastic SOT763-1
74HCT4052BQ −40 to +125 °C 16 DHVQFN16 plastic SOT763-1
2003 May 16 3
Philips Semiconductors Product specification
PINNING
1 16
handbook, halfpage
2Y0 1 16 VCC 2Y2 2 15 1Y2
2Y2 2 15 1Y2
2Z 3 14 1Y1
2Z 3 14 1Y1
2Y3 4 13 1Z
2Y3 4 13 1Z
4052 GND(1)
2Y1 5 12 1Y0 2Y1 5 12 1Y0
E 6 11 1Y3
E 6 11 1Y3
VEE 7 10 S0
VEE 7 10 S0
GND 8 9 S1
8 9
MNB039
GND S1
Top view MNB061
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration DIP16, SO16 and
(T)SSOP16. Fig.2 Pin configuration DHVQFN16.
2003 May 16 4
Philips Semiconductors Product specification
handbook, halfpage 10
13 0 0
handbook, halfpage 4×
9 3
1
1Z
1Y0 6 G4
12
10 S0 1Y1 14
MDX 1
9 S1 1Y2 15 0
5
1Y3 11 1
3
2
2Y0 1 2
2Y1 4
5 3
2Y2 2 12
6 E 2Y3 4 14
13
2Z
15
MNB040
3 11
MNB041
16 13
1Z
12
1Y0
14
1Y1
15
10 1Y2
S0
11
1Y3
LOGIC 1 - OF - 4
LEVEL DECODER
9 CONVERSION 1
S1 2Y0
5
2Y1
6
E 2
2Y2
4
2Y3
3
2Z
8 7
MNB042
GND VEE
2003 May 16 5
Philips Semiconductors Product specification
VCC VEE
VCC VCC
VCC VEE
VEE nZ
from
logic
MNB043
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to VEE = GND
(ground = 0 V); note 1.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +11.0 V
IIK input diode current VI < −0.5 V or VI > VCC + 0.5 V − ±20 mA
ISK switch diode current VS < −0.5 V or VS > VCC + 0.5 V − ±20 mA
IS switch current −0.5 V < VS < VCC + 0.5 V − ±25 mA
IEE VEE current − ±20 mA
ICC; IGND VCC or GND current − ±50 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation Tamb = −40 to +125 °C; note − 500 mW
PS power dissipation per switch − 100 mW
Notes
1. To avoid drawing VCC current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the
bidirectional switch must not exceed 0.4 V. If the switch current flows into pins nZ, no VCC current will flow out of
pins nYn. In this case there is no limit for the voltage drop across the switch, but the voltages at pins nYn and nZ may
not exceed VCC or VEE.
2. For DIP16 packages: above 70 °C derate linearly with 12 mW/K.
For SO16 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C derate linearly with 4.5 mW/K.
2003 May 16 6
Philips Semiconductors Product specification
74HC4052 74HCT4052
SYMBOL PARAMETER CONDITIONS UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
VCC supply voltage see Figs 7 and 8
VCC − GND 2.0 5.0 10.0 4.5 5.0 5.5 V
VCC − VEE 2.0 5.0 10.0 2.0 5.0 10.0 V
VI input voltage GND − VCC GND − VCC V
VS switch voltage VEE − VCC VEE − VCC V
Tamb operating ambient see DC and AC −40 +25 +85 −40 +25 +85 °C
temperature characteristics per −40 − +125 −40 − +125 °C
device
tr, tf input rise and fall times VCC = 2.0 V − 6.0 1000 − 6.0 500 ns
VCC = 4.5 V − 6.0 500 − 6.0 500 ns
VCC = 6.0 V − 6.0 400 − 6.0 500 ns
VCC = 10.0 V − 6.0 250 − 6.0 500 ns
MNB044 MNB045
12 12
handbook, halfpage handbook, halfpage
VCC − GND
VCC − GND (V)
(V) 10
8 8
operating area 6
operating area
4 4
0 0
0 4 8 12 0 4 8 12
VCC − VEE (V) VCC − VEE (V)
Fig.7 Guaranteed operating area as a function of Fig.8 Guaranteed operating area as a function of
the supply voltages for 74HC4052. the supply voltages for 74HCT4052.
2003 May 16 7
Philips Semiconductors Product specification
DC CHARACTERISTICS
Family 74HC4052
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input; Vos is the output voltage at pins nZ or nYn,
whichever is assigned as an output; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
OTHER VCC (V) VEE (V)
Tamb = −40 to +85 °C; note 1
VIH HIGH-level input 2.0 − 1.5 1.2 − V
voltage 4.5 − 3.15 2.4 − V
6.0 − 4.2 3.2 − V
9.0 − 6.3 4.7 − V
VIL LOW-level input 2.0 − − 0.8 0.5 V
voltage 4.5 − − 2.1 1.35 V
6.0 − − 2.8 1.8 V
9.0 − − 4.3 2.7 V
ILI input leakage current VI = VCC or GND 6.0 0 − − ±1.0 µA
10.0 0 − − ±2.0 µA
IS(OFF) analog switch VI = VIH or VIL;
OFF-state current VS = VCC − VEE; see Fig.9
per channel 10.0 0 − − ±1.0 µA
all channels 10.0 0 − − ±2.0 µA
IS(ON) analog switch VI = VIH or VIL; 10.0 0 − − ±2.0 µA
ON-state current VS = VCC − VEE; see Fig.10
ICC quiescent supply VI = VCC or GND; 6.0 0 − − 80.0 µA
current Vis = VEE or VCC; 10.0 0 − − 160.0 µA
Vos = VCC or VEE
2003 May 16 8
Philips Semiconductors Product specification
TEST CONDITIONS
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
OTHER VCC (V) VEE (V)
Tamb = −40 to +125 °C
VIH HIGH-level input 2.0 − 1.5 − − V
voltage 4.5 − 3.15 − − V
6.0 − 4.2 − − V
9.0 − 6.3 − − V
VIL LOW-level input 2.0 − − − 0.5 V
voltage 4.5 − − − 1.35 V
6.0 − − − 1.8 V
9.0 − − − 2.7 V
ILI input leakage current VI = VCC or GND 6.0 0 − − ±1.0 µA
10.0 0 − − ±2.0 µA
IS(OFF) analog switch VI = VIH or VIL;
OFF-state current VS = VCC − VEE; see Fig.9
per channel 10.0 0 − − ±1.0 µA
all channels 10.0 0 − − ±2.0 µA
IS(ON) analog switch VI = VIH or VIL; 10.0 0 − − ±2.0 µA
ON-state current VS = VCC − VEE; see Fig.10
ICC quiescent supply VI = VCC or GND; 6.0 0 − − 160 µA
current Vis = VEE or VCC; 10.0 0 − − 320.0 µA
Vos = VCC or VEE
Note
1. All typical values are measured at Tamb = 25 °C.
2003 May 16 9
Philips Semiconductors Product specification
Family 74HCT4052
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input; Vos is the output voltage at pins nZ or nYn,
whichever is assigned as an output; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
OTHER VCC (V) VEE (V)
Tamb = −40 to +85 °C; note 1
VIH HIGH-level input 4.5 to 5.5 − 2.0 1.6 − V
voltage
VIL LOW-level input 4.5 to 5.5 − − 1.2 0.8 V
voltage
ILI input leakage current VI = VCC or GND 5.5 0 − − ±1.0 µA
IS(OFF) analog switch VI = VIH or VIL;
OFF-state current VS = VCC − VEE; see Fig.9
per channel 10.0 0 − − ±1.0 µA
all channels 10.0 0 − − ±2.0 µA
IS(ON) analog switch VI = VIH or VIL; 10.0 0 − − ±2.0 µA
ON-state current VS = VCC − VEE; see Fig.10
ICC quiescent supply VI = VCC or GND; 5.5 0 − − 80.0 µA
current Vis = VEE or VCC; 5.0 −5.0 − − 160.0 µA
Vos = VCC or VEE
∆ICC additional quiescent VI = VCC − 2.1 V; other inputs 4.5 to 5.5 0 − 45 202.5 µA
supply current per at VCC or GND
input
Tamb = −40 to +125 °C
VIH HIGH-level input 4.5 to 5.5 − 2.0 − − V
voltage
VIL LOW-level input 4.5 to 5.5 − − − 0.8 V
voltage
ILI input leakage current VI = VCC or GND 5.5 0 − − ±1.0 µA
IS(OFF) analog switch VI = VIH or VIL;
OFF-state current VS = VCC − VEE; see Fig.9
per channel 10.0 0 − − ±1.0 µA
all channels 10.0 0 − − ±2.0 µA
IS(ON) analog switch VI = VIH or VIL; 10.0 0 − − ±2.0 µA
ON-state current VS = VCC − VEE; see Fig.10
ICC quiescent supply VI = VCC or GND; 5.5 0 − − 160.0 µA
current Vis = VEE or VCC; 5.0 −5.0 − − 320.0 µA
Vos = VCC or VEE
∆ICC additional quiescent VI = VCC − 2.1 V; other inputs 4.5 to 5.5 0 − − 220.5 µA
supply current per at VCC or GND
input
Note
1. All typical values are measured at Tamb = 25 °C.
2003 May 16 10
Philips Semiconductors Product specification
nYn nZ
A A
VEE
MNB048
nYn nZ
VEE
MNB049
2003 May 16 11
Philips Semiconductors Product specification
TEST CONDITIONS
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
OTHER VCC (V) VEE (V) IS (µA)
Tamb = −40 to +85 °C; note 3
RON(peak) ON-resistance Vis = VCC to VEE; 2.0 0 100 − − − Ω
(peak) VI = VIH or VIL 4.5 0 1000 − 100 225 Ω
6.0 0 1000 − 90 200 Ω
4.5 −4.5 1000 − 70 165 Ω
RON(rail) ON-resistance (rail) Vis = VEE; 2.0 0 100 − 150 − Ω
VI = VIH or VIL 4.5 0 1000 − 80 175 Ω
6.0 0 1000 − 70 150 Ω
4.5 −4.5 1000 − 60 130 Ω
Vis = VCC; 2.0 0 100 − 150 − Ω
VI = VIH or VIL 4.5 0 1000 − 90 200 Ω
6.0 0 1000 − 80 175 Ω
4.5 −4.5 1000 − 65 150 Ω
∆RON maximum Vis = VCC to VEE; 2.0 0 − − − − Ω
ON-resistance VI = VIH or VIL 4.5 0 − − 9 − Ω
difference between
6.0 0 − − 8 − Ω
any two channels
4.5 −4.5 − − 6 − Ω
Tamb = −40 to +125 °C
RON(peak) ON-resistance Vis = VCC to VEE; 2.0 0 100 − − − Ω
(peak) VI = VIH or VIL 4.5 0 1000 − − 270 Ω
6.0 0 1000 − − 240 Ω
4.5 −4.5 1000 − − 195 Ω
RON(rail) ON-resistance (rail) Vis = VEE; 2.0 0 100 − − − Ω
VI = VIH or VIL 4.5 0 1000 − − 210 Ω
6.0 0 1000 − − 180 Ω
4.5 −4.5 1000 − − 160 Ω
Vis = VCC; 2.0 0 100 − − − Ω
VI = VIH or VIL 4.5 0 1000 − − 240 Ω
6.0 0 1000 − − 210 Ω
4.5 −4.5 1000 − − 180 Ω
Notes
1. For 74HC4052: VCC − GND or VCC − VEE = 2.0, 4.5, 6.0 and 9.0 V; for 74HCT4052: VCC − GND = 4.5 and 5.5 V,
VCC − VEE = 2.0, 4.5, 6.0 and 9.0 V.
2. When supply voltages (VCC − VEE) near 2.0 V the analog switch ON-resistance becomes extremely non-linear. When
using a supply of 2 V, it is recommended to use these devices only for transmitting digital signals.
3. All typical values are measured at Tamb = 25 °C.
2003 May 16 12
Philips Semiconductors Product specification
nYn
nZ
VEE
MNB046
MNB047
100
handbook, halfpage
RON (1)
(Ω)
80
(2)
60
(3)
40
20
0
0 1.8 3.6 5.4 7.2 9
Vis (V)
2003 May 16 13
Philips Semiconductors Product specification
AC CHARACTERISTICS
Type 74HC4052
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
TEST CONDITIONS
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
OTHER VCC (V) VEE (V)
Tamb = −40 to +85 °C; note 1
tPHL/tPLH propagation delay Vis to Vos RL = ∞; see Fig.19 2.0 0 − 14 75 ns
4.5 0 − 5 15 ns
6.0 0 − 4 13 ns
4.5 −4.5 − 4 10 ns
tPZH/tPZL turn-on time E, Sn to Vos RL = ∞; see Figs 20, 2.0 0 − 105 405 ns
22 and 21 4.5 0 − 38 81 ns
6.0 0 − 30 69 ns
4.5 −4.5 − 26 58 ns
tPHZ/tPLZ turn-off time E, Sn to Vos RL = 1 kΩ; see Figs 20, 2.0 0 − 74 315 ns
22 and 21 4.5 0 − 27 63 ns
6.0 0 − 22 54 ns
4.5 −4.5 − 22 48 ns
Tamb = −40 to +125 °C
tPHL/tPLH propagation delay Vis to Vos RL = ∞; see Fig.19 2.0 0 − − 90 ns
4.5 0 − − 18 ns
6.0 0 − − 15 ns
4.5 −4.5 − − 12 ns
tPZH/tPZL turn-on time E, Sn to Vos RL = ∞; see Figs 20, 2.0 0 − − 490 ns
22 and 21 4.5 0 − − 98 ns
6.0 0 − − 83 ns
4.5 −4.5 − − 69 ns
tPHZ/tPLZ turn-off time E, Sn to Vos RL = 1 kΩ; see Figs 20, 2.0 0 − − 375 ns
22 and 21 4.5 0 − − 75 ns
6.0 0 − − 64 ns
4.5 −4.5 − − 57 ns
Note
1. All typical values are measured at Tamb = 25 °C.
2003 May 16 14
Philips Semiconductors Product specification
Type 74HCT4052
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
TEST CONDITIONS
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
OTHER VCC (V) VEE (V)
Tamb = −40 to +85 °C; note 1
tPHL/tPLH propagation delay Vis to Vos RL = ∞; see Fig.19 4.5 0 − 5 15 ns
4.5 −4.5 − 4 10 ns
tPZH/tPZL turn-on time E, Sn to Vos RL = 1 kΩ; see Figs 20, 4.5 0 − 41 88 ns
22 and 21 4.5 −4.5 − 28 60 ns
tPHZ tPLZ turn-off time E, Sn to Vos RL = 1 kΩ; see Figs 20, 4.5 0 − 26 63 ns
22 and 21 4.5 −4.5 − 21 48 ns
Tamb = −40 to +125 °C
tPHL/tPLH propagation delay Vis to Vos RL = ∞; see Fig.19 4.5 0 − − 18 ns
4.5 −4.5 − − 12 ns
tPZH/tPZL turn-on time E, Sn to Vos RL = 1 kΩ; see Figs 20, 4.5 0 − − 105 ns
22 and 21 4.5 −4.5 − − 72 ns
tPHZ/tPLZ turn-off time E, Sn to Vos RL = 1 kΩ; see Figs 20, 4.5 0 − − 75 ns
22 and 21 4.5 −4.5 − − 57 ns
Note
1. All typical values are measured at Tamb = 25 °C.
2003 May 16 15
Philips Semiconductors Product specification
Notes
1. Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 Ω).
2. Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 Ω).
RL CL dB
channel
GND
ON
MNB052
Fig.13 Test circuit for measuring sine-wave distortion and minimum frequency response.
2003 May 16 16
Philips Semiconductors Product specification
RL CL dB
channel
GND
OFF
MNB053
0
handbook, full pagewidth
−0
−0
−0
−0
−00
0 0 0 0 0 0
RL CL RL RL CL dB
channel channel
ON OFF
GND GND
MNB054
(a) (b)
Fig.16 Test circuits for measuring crosstalk between any two switches/multiplexers.
2003 May 16 17
Philips Semiconductors Product specification
2RL 2RL
nYn/nZ nZ/nYn
V(p−p) DUT
GND
VEE
MNB055
Fig.17 Test circuit for measuring crosstalk between control and any switch.
5
handbook, full pagewidth
−5
0 0 0 0 0 5 0
2003 May 16 18
Philips Semiconductors Product specification
AC WAVEFORMS
VI
handbook, halfpage
GND
tPLH tPHL
VOH
VOL
MNB056
Fig.19 Waveforms showing the input (Vis) to output (Vos) propagation delays.
90%
E, Sn input VM
10%
tPLZ tPZL
tPHZ tPZH
90%
50%
Vos output
2003 May 16 19
Philips Semiconductors Product specification
tr and tf
FAMILY AMPLITUDE VM
fmax; PULSE WIDTH OTHER
74HC4052 VCC 50% <2 ns 6 ns
74HCT4052 3.0 V 1.3 V <2 ns 6 ns
GND
VEE
MNB058
2003 May 16 20
Philips Semiconductors Product specification
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm; body thickness 1.47 mm SOT109-3
D E A
X
y HE v M A
16 9
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 8 L
e w M detail X
bp
0 2.5 5 mm
scale
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
98-12-23
SOT109-3 MS-012AC
03-02-19
2003 May 16 21
Philips Semiconductors Product specification
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
D E A
X
c
y HE v M A
16 9
Q
A2 A
A1 (A 3)
pin 1 index
θ
Lp
L
1 8 detail X
w M
e bp
0 2.5 5 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
99-12-27
SOT338-1 MO-150
03-02-19
2003 May 16 22
Philips Semiconductors Product specification
D ME
seating plane
A2
A
L A1
c
Z e b1 w M
(e1)
MH
b b2
16 9
pin 1 index
E
1 8
0 5 10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
A A1 A2 Z (1)
UNIT max. b b1 b2 c D (1) E (1) e e1 L ME MH w
min. max. max.
1.65 0.51 1.14 0.36 19.3 6.45 3.81 8.23 9.40
mm 4.32 0.38 3.56 2.54 7.62 0.254 0.76
1.40 0.41 0.76 0.20 18.8 6.24 2.92 7.62 8.38
inches 0.065 0.020 0.045 0.014 0.76 0.254 0.150 0.324 0.37
0.17 0.015 0.14 0.1 0.3 0.01 0.03
0.055 0.016 0.030 0.008 0.74 0.246 0.115 0.300 0.33
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
97-07-24
SOT38-9
03-03-12
2003 May 16 23
Philips Semiconductors Product specification
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
D E A
X
y HE v M A
16 9
Q
A2 (A 3)
A
A1
pin 1 index
θ
Lp
L
1 8
detail X
w M
e bp
0 2.5 5 mm
scale
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
99-12-27
SOT403-1 MO-153
03-02-18
2003 May 16 24
Philips Semiconductors Product specification
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm SOT763-1
D B A
A
A1
E c
terminal 1 detail X
index area
terminal 1 C
e1
index area
e b v M C A B y1 C y
w M C
2 7
1 8
Eh e
16 9
15 10
Dh
X
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
A(1)
UNIT
max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
02-10-17
SOT763-1 --- MO-241 ---
03-01-27
2003 May 16 25
Philips Semiconductors Product specification
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
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Philips Semiconductors Product specification
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, not suitable(3) suitable
HTSSOP, HVQFN, HVSON, SMS
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO, VSSOP not recommended(6) suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Philips Semiconductors Product specification
DEFINITIONS DISCLAIMERS
Short-form specification The data in a short-form Life support applications These products are not
specification is extracted from a full data sheet with the designed for use in life support appliances, devices, or
same type number and title. For detailed information see systems where malfunction of these products can
the relevant data sheet or data handbook. reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
Limiting values definition Limiting values given are in
for use in such applications do so at their own risk and
accordance with the Absolute Maximum Rating System
agree to fully indemnify Philips Semiconductors for any
(IEC 60134). Stress above one or more of the limiting
damages resulting from such application.
values may cause permanent damage to the device.
These are stress ratings only and operation of the device Right to make changes Philips Semiconductors
at these or at any other conditions above those given in the reserves the right to make changes in the products -
Characteristics sections of the specification is not implied. including circuits, standard cells, and/or software -
Exposure to limiting values for extended periods may described or contained herein in order to improve design
affect device reliability. and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information Applications that are
communicated via a Customer Product/Process Change
described herein for any of these products are for
Notification (CPCN). Philips Semiconductors assumes no
illustrative purposes only. Philips Semiconductors make
responsibility or liability for the use of any of these
no representation or warranty that such applications will be
products, conveys no licence or title under any patent,
suitable for the specified use without further testing or
copyright, or mask work right to these products, and
modification.
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
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Philips Semiconductors Product specification
NOTES
2003 May 16 29
Philips Semiconductors Product specification
NOTES
2003 May 16 30
Philips Semiconductors Product specification
NOTES
2003 May 16 31
Philips Semiconductors – a worldwide company
Contact information
Printed in The Netherlands 613508/03/pp32 Date of release: 2003 May 16 Document order number: 9397 750 11266