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NOT GATE-TESTBENCH:

POST-ROUTE-SIMULATION:
NOT GATE:VHDL CODE
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity not_gate is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end not_gate;

architecture Behavioral of not_gate is

begin
b<= not a;
end Behavioral;
//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//

Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Maximum combinational path delay: 8.618ns
Maximum practical path delay:8.6ns
//----------------------------------------------------------------------------------//

Implementation User constrain file using Spartan-3 FPGA kit


//----------------------------------------------------------------------------------//
INPUT = "a" , LOC = "f12" ;
OUTPUT = "b" LOC = "k12" ;
//----------------------------------------------------------------------------------//
Truth table verification:

Truth table of not gate Corresponding I/O mapping to


LOC,FPGA

a b F12 K12
0 1
Off On

1 0 On Off

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “NOT gate”.
AND- GATE-TESTBENCH:

POST-ROUTE-SIMULATION:
AND- GATE-VHDL CODE
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity and_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and_gate;

architecture Behavioral of and_gate is

begin
c<= a and b;

end Behavioral;
//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Maximum combinational path delay: 8.957ns
Maximum practical path delay:8.9ns
//--------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit
//----------------------------------------------------------------------------------//
INPUT= "a" LOC = "F12" ;
INPUT="b" LOC = "G12" ;
OUTPUT="c" LOC = "K12" ;
//----------------------------------------------------------------------------------//
Truth table verification:
Truth table of and gate Corresponding I/O mapping to LOC
a b c F12 G12 K12
0 0 0 Off Off Off
0 1 0 Off On Off
1 0 0 On Off Off
1 1 1 On On On

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “ AND gate”.
OR- GATE-TESTBENCH:

POST-ROUTE-SIMULATION:
OR- GATE-VHDL CODE
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity or_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end or_gate;

architecture Behavioral of or_gate is

begin
c<=a or b;

end Behavioral;
//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Maximum combinational path delay: 8.957ns
Maximum practical path delay:8.9ns
//--------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit
//----------------------------------------------------------------------------------//
INPUT = "a" LOC = "f12" ;
INPUT = "b" LOC = "g12" ;
OUTPUT = "c" LOC = "k12" ;
//----------------------------------------------------------------------------------//
Truth table verification:

Truth table of OR gate Corresponding I/O mapping to LOC


a b c F12 G12 K12
0 0 0 Off Off Off
0 1 1 Off On On
1 0 1 On Off On
1 1 1 On On On

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “OR gate”.
NAND- GATE-TESTBENCH:

POST-ROUTE-SIMULATION:
NAND - GATE-VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity nand_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end nand_gate;

architecture Behavioral of nand_gate is

begin
c<=a nand b;
end Behavioral;
//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Maximum combinational path delay: 8.957ns
Maximum practical path delay:8.9ns
//----------------------------------------------------------------------------------//

Implementation User constrain file using Spartan-3 FPGA kit


//----------------------------------------------------------------------------------//
INPUT = "a" LOC = "f12" ;
INPUT = "b" LOC = "g12" ;
OUTPUT = "c" LOC = "k12" ;
//----------------------------------------------------------------------------------//
Truth table verification:
Truth table of NAND gate Corresponding I/O mapping to LOC
a b c F12 G12 K12
0 0 0 Off Off Off
0 1 1 Off On On
1 0 1 On Off On
1 1 1 On On On

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “ NAND gate”.
NOR- GATE-TESTBENCH:

POST-ROUTE-SIMULATION:
NOR - GATE-VHDL CODE
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity nor_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end nor_gate;

architecture Behavioral of nor_gate is

begin
c<= a nor b;
end Behavioral;

//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Maximum combinational path delay: 8.957ns
Maximum practical path delay: 8.9ns
//--------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit
//----------------------------------------------------------------------------------//
INPUT = "a" LOC = "f12" ;
INPUT = "b" LOC = "g12" ;
OUTPUT = "c" LOC = "k12" ;
//----------------------------------------------------------------------------------//
Truth table verification:
Truth table of NOR gate Corresponding I/O mapping to LOC
a b c F12 G12 K12
0 0 1 Off Off On
0 1 0 Off On Off
1 0 0 On Off Off
1 1 0 On On Off

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “ NOR gate”.
XOR- GATE-TESTBENCH:

POST-ROUTE-SIMULATION:
XOR- GATE-VHDL CODE
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xor_gate;

architecture Behavioral of xor_gate is

begin
c <= a xor b;
end Behavioral;

//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Maximum combinational path delay: 8.957ns
Maximum practical path delay: 8.8ns
//--------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit
//----------------------------------------------------------------------------------//
INPUT = "a" LOC = "f12" ;
INPUT = "b" LOC = "g12" ;
OUTPUT = "c" LOC = "k12" ;
//----------------------------------------------------------------------------------//
Truth table verification:

Truth table of XOR gate Corresponding I/O mapping to LOC


a b c F12 G12 K12
0 0 0 Off Off Off
0 1 1 Off On On
1 0 1 On Off On
1 1 0 On On Off
Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC
Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “ XOR gate”.
XNOR- GATE-TESTBENCH:

POST-ROUTE-SIMULATION:
XNOR- GATE-VHDL CODE
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity xnor_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xnor_gate;

architecture Behavioral of xnor_gate is

begin
c <= a xnor b;
end Behavioral;
//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Maximum combinational path delay: 8.957ns
Maximum practical path delay: 8.8ns
//----------------------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit
//----------------------------------------------------------------------------------//
INPUT = "a" LOC = "f12" ;
INPUT = "b" LOC = "g12" ;
OUTPUT = "c" LOC = "k12" ;
//----------------------------------------------------------------------------------//
Truth table verification:

Truth table of XNOR gate Corresponding I/O mapping to LOC


a B c F12 G12 K12
0 0 1 Off Off On
0 1 0 Off On Off
1 0 0 On Off Off
1 1 1 On On On

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “ XNOR gate”.
HALF-ADDER-TESTBENCH:

POST-ROUTE-SIMULATION:
HALF-ADDRE-VHDL CODE:
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder_1bit is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end adder_1bit;

architecture Behavioral of adder_1bit is

begin
sum <= a xor b;
carry <= a and b;

end Behavioral;
//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Maximum combinational path delay: 9.033ns
Maximum practical path delay: 9.0ns
//---------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit:
INPUT = "a" LOC = "f12" ;
INPUT = "b" LOC = "g12" ;

OUTPUT = "Sum" LOC = "k12";


OUTPUT = "Carry" LOC = " p14" ;

//----------------------------------------------------------------------------------//
Truth table verification:

Truth table of HALF-ADDER Corresponding I/O mapping to


LOC
a b Sum Carry F12 G12 K12 P14
0 0 0 0 Off Off Off Off
0 1 1 0 Off On On Off
1 0 1 0 On Off On Off
1 1 0 1 On On Off On

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC.


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “ HALF-ADDER”.
FULL-ADDER-TESTBENCH:

POST-ROUTE-SIMULATION:
FULL-ADDER-VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_adder is
Port ( a,b,cin : in STD_LOGIC;
Sum,cout : out STD_LOGIC);
end full_adder;

architecture Behavioral of full_adder is

begin

sum <=a xor b xor cin;


cout<=(a and b) or (b and cin) or (cin and a);

end Behavioral;
//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Maximum combinational path delay: 9.033ns
Maximum practical path delay: 9.1ns
//----------------------------------------------------------------------------------//

Implementation User constrain file using Spartan-3 FPGA kit

INPUT = "a" LOC = "f12";


INPUT = "b" LOC = "g12";
INPUT = "cin" LOC = " h12";

OUTPUT = "Sum" LOC = "k12";


OUTPUT = "Cout" LOC = "p12";
//----------------------------------------------------------------------------------//
Truth table verification:

Truth table of FULL-ADDER Corresponding I/O mapping to LOC


a b cin Sum Cout F12 G12 H14 K12 P12
0 0 0 0 0 Off Off Off Off Off
0 1 0 1 0 Off On Off On Off
1 0 0 1 0 On Off Off On Off
1 1 0 0 1 On On Off Off On
0 0 1 1 0 Off Off On On Off
0 1 1 0 0 Off On On Off Off
1 0 1 0 0 On Off On Off Off
1 1 1 1 1 On On On On On

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC.


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “ gate”.
ADDER-3-BIT:

ADDER-3-BIT-TESTBENCH:

POST-ROUTE-SIMULATION:
ADDER-3-BIT-VHDL CODE:
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_adder_3_bit_usin_1_bit is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
b : in STD_LOGIC_VECTOR (2 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (2 downto 0);
cout : out STD_LOGIC);
end full_adder_3_bit_usin_1_bit;

architecture Behavioral of full_adder_3_bit_usin_1_bit is


signal x0,x1:STD_LOGIC;

component full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);

end component;

begin
L1: full_adder port map(a(0),b(0),cin,s(0),x0);
L2: full_adder port map(a(1),b(1),x0,s(1),x1);
L3: full_adder port map(a(2),b(2),x1,s(2),cout);

end Behavioral;

//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
//----------------------------------------------------------------------------------//
Maximum combinational path delay: 12.179ns
Maximum practical path delay: 12.1 ns
//----------------------------------------------------------------------------------//

Implementation User constrain file using Spartan-3 FPGA kit


INPUT = "a(0)" LOC = "f12";
INPUT = "a(1)" LOC = "g12";
INPUT = "a(2)" LOC = "h14";

INPUT = "b(0)" LOC = "h13";


INPUT = "b(1)" LOC = "j14";
INPUT = "b(2)" LOC = "j13";

INPUT = "cin” LOC = " k14";

OUTPUT = "s(0)" LOC = "k12";


OUTPUT = "s(1)" LOC = "p14";
OUTPUT = "s(2)" LOC = "l12";

OUTPUT = "Cout” LOC = "n14";

//----------------------------------------------------------------------------------//
Truth table verification:
Truth table of 3-BIT- FULL-ADDER Corresponding I/O mapping to LOC

0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 0 1 1 1 0
1 1 1 0 0 0 0 1 1 1 0
1 1 1 1 1 1 0 0 1 1 1
0 0 0 0 0 0 1 1 0 0 0
0 0 0 1 1 1 1 0 0 0 1
1 1 1 0 0 0 1 0 0 0 1
1 1 1 1 1 1 1 1 1 1 1

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC.


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “3-BIT- FULL-
ADDER”.
MUX-2-TO-1-TESTBENCH:

POST-ROUTE-SIMULATION:
MUX-2-TO-1- GATE-VHDL CODE
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux_2_1 is
Port ( a,b,s : in STD_LOGIC;
y : out STD_LOGIC);
end mux_2_1;

architecture Behavioral of mux_2_1 is

begin
y<=a when s='0' else b;
end Behavioral;

//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Maximum combinational path delay: 8.957 ns
Maximum practical path delay: 8.9ns
//---------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit

INPUT = "a" LOC = "f12" ;


INPUT = "b" LOC = "g12" ;
INPUT = "s" LOC = " h14" ;
OUTPUT = "y" LOC = "k12" ;

//----------------------------------------------------------------------------------//
Truth table verification:

Truth table of MUX-2-TO-1 Corresponding I/O mapping to LOC


a b s y F12 G12 H14 K12
0 x 0 0 Off Off/on Off Off
1 x 0 1 On Off/on Off On
x 0 1 0 Off/on Off On Off
x 1 1 1 Off/on On On On

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC.


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “MUX-2-TO-1 ”.
MUX-4-TO-1-USING MUX-2-TO-1:

MUX-4-TO-1-TESTBENCH:

POST-ROUTE-SIMULATION:
MUX-4-TO-1-VHDL CODE:
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux_4_1_usin_2_1 is
Port ( d0,d1,d2,d3,s0,s1 : in STD_LOGIC;
y : out STD_LOGIC);
end mux_4_1_usin_2_1;

architecture Behavioral of mux_4_1_usin_2_1 is


signal x0,x1:STD_LOGIC;

component mux_2_1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
y : out STD_LOGIC);
end component;

begin
L1: mux_2_1 port map (d0,d1,s1,x0);
L2: mux_2_1 port map (d2,d3,s1,x1);
L3: mux_2_1 port map (x0,x1,s0, y);

end Behavioral;
//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Maximum combinational path delay: 9.393ns
Maximum practical path delay: 9.4ns
//--------------------------------------------------------------------//
//--------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit

INPUT = "d0" LOC = "f12" ; INPUT = "d1" LOC = "g12" ;


INPUT = "d2" LOC ="h14 "; INPUT = "d2" LOC = "h13 " ;
INPUT = "s0" LOC ="j14 " ; INPUT = "s1" LOC = "j13 " ;
OUTPUT = "y" LOC = "k12";

//----------------------------------------------------------------------------------//
Truth table verification:
Truth table of MUX-4-TO-1 Corresponding I/O mapping to LOC
s0 s1 d0 d1 d2 d3 y J14 J13 F12 G12 H14 H13 K12
0 0 0 x x x 0 Off Off Off Off/On Off/On Off/On Off
0 0 1 x x x 1 Off Off On Off/On Off/On Off/On On
0 1 x 0 x x 0 Off On Off/On Off Off/On Off/On Off
0 1 x 1 x x 1 Off On Off/On On Off/On Off/On On
1 0 x x 0 x 0 On Off Off/On Off/On Off Off/On Off
1 0 x x 1 x 1 On Off Off/On Off/On On Off/On On
1 1 x x x 0 0 On On Off/On Off/On Off/On Off Off
1 1 x x x 1 1 On On Off/On Off/On Off/On On On

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC.


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “MUX-4-TO-1 ”.
DECODER2-TO-4-TESTBENCH:

POST-ROUTE-SIMULATION:
DECODER2-TO-4-VHDL CODE
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder_2_4 is
Port ( e : in STD_LOGIC;
d : in STD_LOGIC_VECTOR(1 DOWNTO 0);
y : out STD_LOGIC_VECTOR(3 DOWNTO 0));
end decoder_2_4;

architecture Behavioral of decoder_2_4 is

begin
process(e,d)
begin
if e='0' then y<=(others =>'0');
else
case d is
when "00" => y<= "0001";
when "01" => y<= "0010";
when "10" => y<= "0100";
when "11" => y<= "1000";
when others => NULL;
end case;
end if;
end process;

end Behavioral;
//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//

Maximum combinational path delay: 9.073ns


Maximum practical path delay: 8.5ns
//----------------------------------------------------------------------------------//
//----------------------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit

INPUT = "e" LOC = "f12" ;


INPUT = "d(0)" LOC = "g12" ;INPUT = "d(1)" LOC = "h14 " ;
OUTPUT = "y(0)" LOC = "k12" ; OUTPUT = "y(1)" LOC = "p14" ;
OUTPUT = "y(2)" LOC = "l12" ; OUTPUT = "y(3)" LOC = "n14" ;

//----------------------------------------------------------------------------------//

Truth table verification:


Truth table of DECODER-2-TO-4 Corresponding I/O mapping to LOC
e d(1) d(0) y(3) y(2) y(1) y(0) F12 G12 H13 K12 P14 L12 N14
0 x x 0 0 0 0 Off Off/on Off/on Off Off Off Off
1 0 0 0 0 0 1 On Off Off Off Off Off On
1 0 1 0 0 1 0 On Off On Off Off On Off
1 1 0 0 1 0 0 On On Off Off On Off Off
1 1 1 1 0 0 0 On On On On Off Off Off

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC.


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “DECODER-2-TO-4 ”.
DECODER-3-TO-8:

DECODER-3-TO-8-TESTBENCH:

POST-ROUTE-SIMULATION:
DECODER-3-TO-8-VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder_3_8_usin_2_4 is
Port ( en : in STD_LOGIC;
i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
y : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end decoder_3_8_usin_2_4;

architecture Behavioral of decoder_3_8_usin_2_4 is

signal x2,en1,en2:STD_LOGIC;

component decoder_2_4 is
Port ( e : in STD_LOGIC;
d : in STD_LOGIC_VECTOR(1 DOWNTO 0);
y : out STD_LOGIC_VECTOR(3 DOWNTO 0));
end component;

component and_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;

component not_gate is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end component;

begin
L1: not_gate port map(i(2),x2);
L2: and_gate port map(x2,en,en1);
L3: and_gate port map(i(2),en,en2);
L4: decoder_2_4 port map(en1,i(1 downto 0),y(3 downto 0));
L5: decoder_2_4 port map(en2,i(1 downto 0),y(7 downto 4));

end Behavioral;

//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
//----------------------------------------------------------------------------------//
Maximum combinational path delay: 9.939ns
Maximum combinational path delay: 10.8ns
//----------------------------------------------------------------------------------//

Implementation User constrain file using Spartan-3 FPGA kit

INPUT = "en" LOC = "f12" ;


INPUT = "i(2)" LOC = "g12" ;
INPUT = "i(1)" LOC = "h14 " ;
INPUT = "i(0)" LOC = "j13 ";

OUTPUT = "y(0)" LOC = "k12" ; OUTPUT = "y(1)" LOC = "p14" ;


OUTPUT = "y(2)" LOC = "l12" ; OUTPUT = "y(3)" LOC = "n14" ;
OUTPUT = "y(4)" LOC = "p13" ; OUTPUT = "y(5)" LOC = "p11" ;
OUTPUT = "y(6)" LOC = " " ; OUTPUT = "y(7)" LOC = " ";
//----------------------------------------------------------------------------------//

Truth table verification:

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC.


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “DECODER-3-TO-8 ”.
ADDER-SUBTRACTOR-DIAGRAM:

ADDER-SUBTRACTOR -TESTBENCH:

POST-ROUTE-SIMULATION:
ADDER-SUBTRACTOR -VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder_subtractor is
Port ( S : in STD_LOGIC;
A,B : in STD_LOGIC_VECTOR (2 downto 0);
F : out STD_LOGIC_VECTOR (2 downto 0);
unsigned_overflow : inout STD_LOGIC;
signed_overflow : out STD_LOGIC);
end adder_subtractor;

architecture Behavioral of adder_subtractor is


signal X0,X1,X2,C1,C2:STD_LOGIC;

component full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end component;

component xor_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;

begin
L1:xor_gate port map(S,B(0),X0);
L2:xor_gate port map(S,B(1),X1);
L3:xor_gate port map(S,B(2),X2);
L4:full_adder port map(A(0),X0,S,F(0),C1);
L5:full_adder port map(A(1),X1,C1,F(1),C2);
L6:full_adder port map(A(2),X2,C2,F(2),unsigned_overflow);
L7:xor_gate port map(unsigned_overflow,C2,signed_overflow);

end Behavioral;
//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
//----------------------------------------------------------------------------------//
Maximum combinational path delay: 8.618ns
//----------------------------------------------------------------------------------//

Implementation User constrain file using Spartan-3 FPGA kit


INPUT = "S" LOC = "f12" ;
INPUT = "A(0)" LOC = "g12" ;
INPUT = "A(1)" LOC = "h14";
INPUT = "A(2)" LOC = "h13";
INPUT = "B(0)" LOC = "j14" ;
INPUT = "B(1)" LOC = "j13";
INPUT = "B(2)" LOC = "k14";

OUTPUT = "F(0)" LOC = "k12" ;


OUTPUT = "F(1)" LOC = "p14" ;
OUTPUT = "F(2)" LOC = "l12" ;
OUTPUT = " unsigned_overflow " LOC = "n14" ;
OUTPUT = " signed_overflow " LOC = "p13" ;
//----------------------------------------------------------------------------------//

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC.


Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “ADDER-SUBTRACTOR”.