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Introduction to VLSI Design

CMOS VLSI Design 2
CMOS VLSI Design 2
CMOS VLSI Design 2

CMOS VLSI Design

2

Introduction

Introduction Why is designing digital ICs different today than it was before? Will it change in

Why is designing digital ICs different today than it was before? Will it change in future?

Why is designing digital ICs different today than it was before? Will it change in future?
Why is designing digital ICs different today than it was before? Will it change in future?

CMOS VLSI Design

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The First Computer

The First Computer The Babbage Difference Engine (1832) 25,000 parts c o s t : £17,470
The First Computer The Babbage Difference Engine (1832) 25,000 parts c o s t : £17,470

The Babbage Difference Engine

(1832)

25,000 parts cost: £17,470

The First Computer The Babbage Difference Engine (1832) 25,000 parts c o s t : £17,470

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CMOS VLSI Design

ENIAC - The first electronic computer (1946)

5 CMOS VLSI Design
5 CMOS VLSI Design
5 CMOS VLSI Design

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CMOS VLSI Design

The First Integrated Circuits

Bipolar logic 1960’s ECL 3-input Gate Motorola 1966 6 CMOS VLSI Design
Bipolar logic 1960’s ECL 3-input Gate Motorola 1966 6 CMOS VLSI Design

Bipolar logic

1960’s

ECL 3-input Gate Motorola 1966

Bipolar logic 1960’s ECL 3-input Gate Motorola 1966 6 CMOS VLSI Design

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CMOS VLSI Design

Intel 4004 Micro-Processor

Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation 7 CMOS VLSI Design
Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation 7 CMOS VLSI Design

1971

1000 transistors 1 MHz operation

Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation 7 CMOS VLSI Design

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CMOS VLSI Design

Intel Pentium (IV) microprocessor

8 CMOS VLSI Design
8 CMOS VLSI Design
8 CMOS VLSI Design

8

CMOS VLSI Design

Transistor Counts K 11 BillionBillion TransistorsTransistors 1,000,000 100,000 10,000 1,000 Pentium ® III
Transistor Counts
K
11 BillionBillion
TransistorsTransistors
1,000,000
100,000
10,000
1,000
Pentium ® III
Pentium ® II
Pentium ® Pro
i486 Pentium ®
i386
100
80286
10
8086
Source:Source: IntelIntel
1
1975
1980
1985
1990
1995
2000
2005
2010
ProjectedProjected
9
CMOS VLSI Design
Courtesy, Intel

Moore’s Law

Moore’s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months

He made a prediction that semiconductor technology will double its effectiveness every 18 months 10 CMOS

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CMOS VLSI Design

Moore’s Law 16 15 14 13 12 11 10 9 8 7 6 5 4
Moore’s Law
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Electronics, April 19, 1965.
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CMOS VLSI Design
LOG 2 OF THE N UMBER OF
COMPONENTS PER INT EGRATED FUNCTION
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975

Design Abstraction Levels

SYSTEM MODULE + GATE CIRCUIT DEVICE G D S n+ n+
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
D
S
n+
n+
Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT DEVICE G D S n+ n+ 12 CMOS

12

CMOS VLSI Design

Fabrication and Layout CMOS VLSI Design Slide 13
Fabrication and Layout CMOS VLSI Design Slide 13

Fabrication and Layout

CMOS VLSI Design

Slide 13

Die Cost

Die Cost Single die Wafer 14 From http://www.amd.com CMOS VLSI Design
Die Cost Single die Wafer 14 From http://www.amd.com CMOS VLSI Design

Single die

Die Cost Single die Wafer 14 From http://www.amd.com CMOS VLSI Design
Die Cost Single die Wafer 14 From http://www.amd.com CMOS VLSI Design

Wafer

Die Cost Single die Wafer 14 From http://www.amd.com CMOS VLSI Design

14 From http://www.amd.com

CMOS VLSI Design

Going up to 12” (30cm)

Yield

No. of good chips per wafer

Y

× 100%

=

Total number of chips per wafer

Die cost =

Wafer cost

Dies per wafer

× Die yield

Dies per wafer =

π×

(

wafer diameter/2 2

)

di e area

π× wafer diameter

yield Dies per wafer = π× ( wafer diameter/2 2 ) di e area π× wafer

2× die area

yield Dies per wafer = π× ( wafer diameter/2 2 ) di e area π× wafer
yield Dies per wafer = π× ( wafer diameter/2 2 ) di e area π× wafer
yield Dies per wafer = π× ( wafer diameter/2 2 ) di e area π× wafer

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CMOS VLSI Design

Silicon Lattice

Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms

Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors

Forms crystal lattice with bonds to four neighbors Si Si Si Si Si Si Si Si

SiSi Si Si Si

SiSi Si Si Si

SiSi Si Si Si

Si Si Si
Si Si Si
lattice with bonds to four neighbors Si Si Si Si Si Si Si Si Si Fabrication
Si Si Si Si Si Si
Si
Si
Si
Si
Si
Si
bonds to four neighbors Si Si Si Si Si Si Si Si Si Fabrication and Layout
bonds to four neighbors Si Si Si Si Si Si Si Si Si Fabrication and Layout

Fabrication and Layout

CMOS VLSI Design

Slide 16

Dopants

Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants

Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)

Si Si Si - + Si As Si Si Si Si
Si
Si
Si
-
+
Si
As
Si
Si
Si
Si
Si Si Si + - Si B Si Si Si Si
Si
Si
Si
+
-
Si
B
Si
Si
Si
Si
Si - + Si As Si Si Si Si Si Si Si + - Si B

Fabrication and Layout

CMOS VLSI Design

Slide 17

p-n Junctions

p-n Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in

A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction

p-type n-type

p-type

p-type
p-type

n-type

anode

cathode

Current flows only in one direction p-type n-type anode cathode Fabrication and Layout CMOS VLSI Design
Current flows only in one direction p-type n-type anode cathode Fabrication and Layout CMOS VLSI Design

Fabrication and Layout

CMOS VLSI Design

Slide 18

nMOS Transistor

nMOS Transistor Fabrication and Layout CMOS VLSI Design Slide 19
nMOS Transistor Fabrication and Layout CMOS VLSI Design Slide 19
nMOS Transistor Fabrication and Layout CMOS VLSI Design Slide 19

Fabrication and Layout

CMOS VLSI Design

Slide 19

MOS Structure

MOS Structure Fabrication and Layout CMOS VLSI Design Slide 20
MOS Structure Fabrication and Layout CMOS VLSI Design Slide 20
MOS Structure Fabrication and Layout CMOS VLSI Design Slide 20

Fabrication and Layout

CMOS VLSI Design

Slide 20

MOS Structure

MOS Structure Fabrication and Layout CMOS VLSI Design Slide 21
MOS Structure Fabrication and Layout CMOS VLSI Design Slide 21
MOS Structure Fabrication and Layout CMOS VLSI Design Slide 21

Fabrication and Layout

CMOS VLSI Design

Slide 21

nMOS Operation

Step 1: Apply Gate Voltage

nMOS Operation Step 1: Apply Gate Voltage SiO 2 Insulator (Glass) Gate 5 volts N N

SiO 2 Insulator (Glass)

Gate 5 volts N N P
Gate
5 volts
N
N
P

Step 2: Excess electrons surface in channel, holes are repelled.

Source

Drain

surface in channel, holes are repelled. Source Drain holes electrons electrons to be transmitted Step 3:

holessurface in channel, holes are repelled. Source Drain electrons electrons to be transmitted Step 3: Channel

electronssurface in channel, holes are repelled. Source Drain holes electrons to be transmitted Step 3: Channel

electrons to be transmittedin channel, holes are repelled. Source Drain holes electrons Step 3: Channel becomes saturated with electrons.

Step 3: Channel becomes saturated with electrons. Electrons in source are able to flow across channel to Drain.

Figure 2

Electrons in source are able to flow across channel to Drain. Figure 2 CMOS VLSI Design

CMOS VLSI Design

Image courtesy of me. =o)

nMOS Operation

nMOS Operation Body is commonly tied to ground (0 V) When the gate is at a

Body is commonly tied to ground (0 V) When the gate is at a low voltage:

– P-type body is at low voltage

– Source-body and drain-body diodes are OFF

– No current flows, transistor is OFF

Source Gate Drain Polysilicon SiO 2 0 n+ n+ S D p bulk Si
Source
Gate
Drain
Polysilicon
SiO 2
0
n+
n+
S
D
p
bulk Si
OFF Source Gate Drain Polysilicon SiO 2 0 n+ n+ S D p bulk Si Fabrication

Fabrication and Layout

CMOS VLSI Design

Slide 23

nMOS Operation

nMOS Operation When the gate is at a high voltage: – Positive charge on gate of

When the gate is at a high voltage:

– Positive charge on gate of MOS capacitor

– Negative charge attracted to body

– Inverts a channel under gate to n-type

– Now current can flow through n-type silicon from source through channel to drain, transistor is ON

Source Gate Drain Polysilicon SiO 2 1 n+ n+ S D p bulk Si
Source
Gate
Drain
Polysilicon
SiO 2
1
n+
n+
S
D
p
bulk Si
ON Source Gate Drain Polysilicon SiO 2 1 n+ n+ S D p bulk Si Fabrication

Fabrication and Layout

CMOS VLSI Design

Slide 24

Operation

Operation Fabrication and Layout CMOS VLSI Design Slide 25
Operation Fabrication and Layout CMOS VLSI Design Slide 25
Operation Fabrication and Layout CMOS VLSI Design Slide 25

Fabrication and Layout

CMOS VLSI Design

Slide 25

Band Diagram

Band Diagram Fabrication and Layout CMOS VLSI Design Slide 26
Band Diagram Fabrication and Layout CMOS VLSI Design Slide 26
Band Diagram Fabrication and Layout CMOS VLSI Design Slide 26

Fabrication and Layout

CMOS VLSI Design

Slide 26

Fabrication and Layout CMOS VLSI Design Slide 27
Fabrication and Layout CMOS VLSI Design Slide 27
Fabrication and Layout CMOS VLSI Design Slide 27

Fabrication and Layout

CMOS VLSI Design

Slide 27

Some Definitions

Some Definitions Fabrication and Layout CMOS VLSI Design Slide 28
Some Definitions Fabrication and Layout CMOS VLSI Design Slide 28
Some Definitions Fabrication and Layout CMOS VLSI Design Slide 28

Fabrication and Layout

CMOS VLSI Design

Slide 28

Fabrication and Layout CMOS VLSI Design Slide 29
Fabrication and Layout CMOS VLSI Design Slide 29
Fabrication and Layout CMOS VLSI Design Slide 29

Fabrication and Layout

CMOS VLSI Design

Slide 29

Fabrication and Layout CMOS VLSI Design Slide 30
Fabrication and Layout CMOS VLSI Design Slide 30
Fabrication and Layout CMOS VLSI Design Slide 30

Fabrication and Layout

CMOS VLSI Design

Slide 30

Basic Equations

Basic Equations Fabrication and Layout CMOS VLSI Design Slide 31
Basic Equations Fabrication and Layout CMOS VLSI Design Slide 31
Basic Equations Fabrication and Layout CMOS VLSI Design Slide 31

Fabrication and Layout

CMOS VLSI Design

Slide 31

Fabrication and Layout CMOS VLSI Design Slide 32
Fabrication and Layout CMOS VLSI Design Slide 32
Fabrication and Layout CMOS VLSI Design Slide 32

Fabrication and Layout

CMOS VLSI Design

Slide 32

Current Equation

Current Equation Fabrication and Layout CMOS VLSI Design Slide 33
Current Equation Fabrication and Layout CMOS VLSI Design Slide 33
Current Equation Fabrication and Layout CMOS VLSI Design Slide 33

Fabrication and Layout

CMOS VLSI Design

Slide 33

Current Equation

Current Equation Fabrication and Layout CMOS VLSI Design Slide 34
Current Equation Fabrication and Layout CMOS VLSI Design Slide 34
Current Equation Fabrication and Layout CMOS VLSI Design Slide 34

Fabrication and Layout

CMOS VLSI Design

Slide 34

Fabrication and Layout CMOS VLSI Design Slide 35
Fabrication and Layout CMOS VLSI Design Slide 35
Fabrication and Layout CMOS VLSI Design Slide 35

Fabrication and Layout

CMOS VLSI Design

Slide 35

Fabrication and Layout CMOS VLSI Design Slide 36
Fabrication and Layout CMOS VLSI Design Slide 36
Fabrication and Layout CMOS VLSI Design Slide 36

Fabrication and Layout

CMOS VLSI Design

Slide 36

Fabrication and Layout CMOS VLSI Design Slide 37
Fabrication and Layout CMOS VLSI Design Slide 37
Fabrication and Layout CMOS VLSI Design Slide 37

Fabrication and Layout

CMOS VLSI Design

Slide 37

Fabrication and Layout CMOS VLSI Design Slide 38
Fabrication and Layout CMOS VLSI Design Slide 38
Fabrication and Layout CMOS VLSI Design Slide 38

Fabrication and Layout

CMOS VLSI Design

Slide 38

Fabrication and Layout CMOS VLSI Design Slide 39
Fabrication and Layout CMOS VLSI Design Slide 39
Fabrication and Layout CMOS VLSI Design Slide 39

Fabrication and Layout

CMOS VLSI Design

Slide 39

Linear Region

Linear Region Fabrication and Layout CMOS VLSI Design Slide 40
Linear Region Fabrication and Layout CMOS VLSI Design Slide 40
Linear Region Fabrication and Layout CMOS VLSI Design Slide 40

Fabrication and Layout

CMOS VLSI Design

Slide 40