Freesclae Motor Control

June, 2010
Getting Started with Digital Signal Controllers (DSCs) for Motor Control and Energy Conversion
FTF-IND-F0580 Pavel Grasblum, Ph.D.
Application Engineer
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 2010 Freescale Semiconductor, Inc.
Agenda
DSC

Introduction
Roadmap Update DSCs Overview
DSC

Core Introduction Key peripherals for Motor Control and Energy Conversion Applications
Detail Description Differences among DSC Families
Peripherals

Utilization Guidelines
ADC to PWM Synchronization Low Cost Current Measurement BLDC Motor Commutation
MC
and SMPS Demos presented at FTF in Orlando
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What is a Digital Signal Controller?
Designed for controller code Compact code size Easy to program Inefficient signal processing
Designed for DSP processing Designed for matrix operations Complex programming Less suitable for control
Instructions optimized for controller code, DSP, matrix operations
Compact assembly and C compiled code size Easy to program Additional MIPS headroom and extended addressing space
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When is a Digital Signal Controller a Good Fit?

When
the application is dominated by high-speed capture and analysis of analog input and feedback (e.g. PWM adjustment) to a closed loop system
DSC is similar to an MCU but with the performance to run complex algorithms for more responsive control and often, system cost reduction DSC provides flexibility to be used in multiple systems or to adapt within a system to environmental changes (compared to fixed analog-based control)
Key

features
Sufficient MIPs (32-60 MIPS) MCU/DSP performance for advanced algorithms High speed/performance 600ns/12 bit ADC for fast dynamic response High speed sophisticated (60 MHz- 96 Mhz) PWMs and timer modules to effectively increase PWM resolution Quadrature decoders for direct interface to Hall effect sensors or optical encoders Safety features (fault inputs, loss of clock) to prevent catastrophic failures
Key
applications
Motor control Digital power conversion Advanced lighting control
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Flash Size
DSC Roadmap
Low Power Low Cost Large Capacity Mid Range High Performance
<280kB <560kB
MC56F816x MC56F816x 40MHz 40MHz
MC56F836x MC56F836x 60MHz 60MHz 32-bit Core, 32-bit Core, 100MHz, DMA, 100MHz, DMA, FAST ADC & FAST ADC & PWM PWM MC56F834x MC56F834x 60MHz 60MHz 32-bit Core, 32-bit Core, 100MHz, DMA, 100MHz, DMA, FAST ADC & FAST ADC & PWM PWM
Pin Compatible
<144kB
MC56F803x MC56F803x 32MHz, HR PWM, 32MHz, HR PWM, CAN, ADC, DAC CAN, ADC, DAC
MC56F824x/5x MC56F824x/5x 60MHz, 60MHz, Accurate PWM Accurate PWM FAST ADC 2010 FAST ADC 60MHz, 60MHz, Accurate PWM Accurate PWM FAST ADC FAST ADC
32-bit Core, 32-bit Core, 100MHz, DMA, 100MHz, DMA, FAST ADC & FAST ADC & PWM PWM 32-bit Core 32-bit Core 100 MHz, DMA 100 MHz, DMA FAST ADC & FAST ADC & PWM PWM
Production - Available NOW
<64kB
<32kB
Pin Compatible
MC56F802x MC56F802x 32MHz, HR PWM, 32MHz, HR PWM, ADC, DAC ADC, DAC MC56F801x MC56F801x 32MHz, 32MHz, HR PWM, HR PWM, ADC ADC 56F800x 56F800x V. Low Cost, V. Low Cost, HR PWM HR PWM
40MHz 40MHz Ultra Low Cost Ultra Low Cost
<16kB
Execution - Specification Frozen, in design Proposal - Specification Subject to Change
2009
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Cost-Effective 56F8000 Solutions (56F801x)

32 MIPS performance 12K -16 K Bytes program FLASH 4 K Bytes program/data RAM Tunable internal relaxation oscillator Software programmable phase locked loop Up to 96 MHz peripherals timers and PWMs Up to 6-output PWM module with up to 4
56F8011/56F8013/56F8014
12K - 16KB Program Flash 4kB Program/ Data RAM System Integration Module (SIM) Interrupt Controller PLL Relaxation OSC Voltage Regulator COP Power-On-Reset JTAG/EOnCE Power Supervisor 6-ch PWM Output Up to 26 GPIOs 1 x SCI 1 x SPI 1x IIC 3-4ch 12bit ADC 3-4ch 12bit ADC
programmable fault inputs Two 12-bit ADCs with up to 8 inputs, 1.125us conversion rate Synchronization between PWM and ADC Four 16-bit general purpose programmable timers Computer operating properly timer Serial ports: SCI, SPI, I2C Up to 26 GPIOs Versatile pin usage Low power consumption 59 mA max. and .026 mA min. JTAG/EOnCE debug port Industrial and automotive temperature range Cost effective
56800E Core 32MHz
Synch
4Ch 16bit Timer
Package: 32LQFP In Production
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56F8000 Family Expansion (56F802x/56F803x)

32 MHz/32 MIPS 56800E core 3.0-3.6V operation 32K-64 K Bytes program FLASH 4K-8 K Bytes program/data RAM Flash security Tunable internal relaxation oscillator Software programmable phase locked loop Up to 96 MHz peripherals timers and PWMs 6 output PWM module with 4 programmable fault inputs with selectable PWM frequency for each PWM signal complementary pair Two 12-bit ADCs with up to 16 inputs , 1.125us conversion rate Up to two 12-bit digital to analog converters Two analog comparators Synchronization between PWM and ADC 4 or 8 16-bit general purpose programmable timers 1 or 3 programmable interval timers (PIT) Computer operating properly timer 2-queued serial communications interface 2-queued serial peripheral interface Optional MSCAN I2C communications interface Up to 53 GPIOs Versatile pin usage JTAG/EOnCE debug port Industrial and automotive temperature range
56F8023/56F8025/56F8036/56F8037
32KB - 64KB Program Flash 4kB-8KB Program/ Data RAM System Integration Module (SIM) Interrupt Controller PLL Relaxation OSC Crystal OSC Up to 53 GPIOs 2 x QSCI 2 x QSPI 1xIIC 1x MSCAN 3xPIT 8ch 12bit ADC 8ch 12bit ADC
56800E Core 32MHz
Voltage Regulator COP Power-On-Reset
Synch
8Ch 16bit Timer 6-ch PWM Output
JTAG/EOnCE
Power Supervisor
2 x 12 bit DAC
2 x Comparators
Package 32 LQFP, 44LQFP, 48LQFP, 64LQFP In Production
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Ultra Low Cost: 56F800x

32 MHz/32 MIPS 56800E core 1.8-3.6V operation 12K - 16K Bytes program FLASH with Flash security 2K Bytes program/data RAM Tunable internal relaxation oscillator and 32 KHz clock Phase locked loop (PLL) Up to 96 MHz peripherals timers, PWM & Hi-SCI 6 output PWM module with 4 programmable fault inputs with selectable PWM frequency for each PWM signal complementary pair Two programmable gain amplifiers with x2, x4, x8, x16 gains (clocked in order to cancel input offset) Two 12-bit ADCs with up to 24 inputs , 2.5us per conversion Programmable delay block provides precise control of ADC/PGA sample times relative to PWM reload cycles Three high speed analog comparators 2 multiple function programmable timers Computer operating properly timer One periodic interval timer (PIT) 1 high speed serial communication interface (Hi-SCI) 1 serial peripheral interface (SPI) I2C communications interface Up to 40 GPIOs versatile pin usage JTAG/EOnCE debug port Industrial temperature range: -40C 105C
56F8002, 56F8006
12-16KB Program Flash 2KB Program/ Data RAM System Integration Module (SIM) Interrupt Controller PLL Relaxation OSC Crystal OSC 1 Period Int Timer Up to 40 GPIOs 1 SCI 1 SPI 1 IIC 2 x 16bit Timers 3 x Analog Comparators 2 x Programmable Gain Amplifiers 12ch 12bit ADC 12ch 12bit ADC
56800E Core 32MHz

JTAG/EOnCE
Voltage Regulator COP Power-On-Reset Power Supervisor
Synch
Programmable Delay Block 6-ch PWM Output
Package: 28SOIC, 32SDIP , 32LQFP, 48 LQFP In Production
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56F8000 Series Feature Summary

56F8002 Performance Temperature Range (V) Voltage Range Voltage Regulator Program/Data Flash Program/Data RAM Program Security PLL COP (Watchdog) PWM (96 Mhz Clock) PWM Fault Inputs 12-bit ADCs 12-bit DACs Analog Comparator Prog Gain Amp 16-bit Timers Prog. Interval Timers GPIO (max) (+/-8mA) IIC SCI (UART) / LIN Slave SPI (Synchronous) CAN JTAG/EOnCE Power Consumption Package 32MHz/MIPs -40C~105C 1.8V - 3.6V On-Chip 12KB 2KB Yes Yes Yes 1 x 6ch 4 2 x 8ch 0 3 2 3 1 (RTC) 23 1 1 - SCI 1 - SPI No Yes 32LQFP (.8p) 56F8006 -40C~105C 1.8V - 3.6V On-Chip 16KB 2KB Yes Yes Yes Yes 1 x 6ch 4 2 x 12ch 0 3 2 3 1 (RTC) 40 1 1 - SCI 1 - SPI No Yes
28SOIC 32LQFP 32SDIP 48LQFP
56F8011 -40C~125C 3.0V - 3.6V On-Chip 12KB 2KB Yes Yes Yes Yes 1 x 6ch 4 2 x 3ch No No No 4 No 26* 1 1 - SCI 1 - SPI No Yes 32LQFP
56F8013 32MHz/MIPs -40C~125C 3.0V - 3.6V On-Chip 16KB 4KB Yes Yes Yes Yes 1 x 6ch 4 2 x 3ch No No No 4 No 26* 1 1 - SCI 1 - SPI No Yes 32LQFP
56F8014 -40C~125C 3.0V - 3.6V On-Chip 16KB 4KB Yes Yes Yes Yes 1 x 5ch 3 2 x 4ch No No No 4 No 26* 1 1 - SCI 1 - SPI No Yes 32LQFP
56F8023 -40C~105C 3.0V - 3.6V On-Chip 32KB 4KB Yes Yes Yes Yes 1 x 6ch 4 2 x 3ch 2 2 No 4 1 26* 1 - QIIC 1 - QSCI 1 - QSPI No Yes 32LQFP
56F8025 32MHz/MIPs -40C~105C 3.0V - 3.6V On-Chip 32KB 4KB Yes Yes Yes Yes 1 x 6ch 4 2 x 4ch 2 2 No 4 3 35* 1 - QIIC 1 - QSCI 1 - QSPI No Yes 44LQFP
56F8036 32MHz/MIPs -40C~105C 3.0V - 3.6V On-Chip 64KB 8KB Yes Yes Yes Yes 1 x 6ch 4 2 x 5ch 2 2 No 4 3 39* 1 - QIIC 1 - QSCI 1 - QSPI MSCAN Yes 48LQFP
56F8027/37 32MHz/MIPs -40C~105C 3.0V - 3.6V On-Chip 32KB / 64KB 4KB /8KB Yes Yes Yes Yes 1 x 6ch 4 2 x 8ch 2 (Pinned out) 2 No 8 3 53* 1 - QIIC 1 - QSCI 1 - QSPI MSCAN Yes 64LQFP
32MHz/MIPs 32MHz/MIPs
32MHz/MIPs 32MHz/MIPs
On Chip Relaxation Osc. Yes
IDD = 45.6mA;IDDA = 4.5mA
IDD = 42mA; IDDA = 13.5mA
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Flash Size
DSC Roadmap
Low Power Low Cost Large Capacity Mid Range High Performance
<280kB <560kB
MC56F836x MC56F836x 60MHz 60MHz 32-bit Core, 32-bit Core, 100MHz, DMA, 100MHz, DMA, FAST ADC & FAST ADC & PWM PWM MC56F834x MC56F834x 60MHz 60MHz 32-bit Core, 32-bit Core, 100MHz, DMA, 100MHz, DMA, FAST ADC & FAST ADC & PWM PWM
Pin Compatible
<144kB
MC56F803x MC56F803x 32MHz, HR PWM, 32MHz, HR PWM, CAN, ADC, DAC CAN, ADC, DAC
MC56F824x/5x MC56F824x/5x 60MHz, 60MHz, Accurate PWM Accurate PWM FAST ADC 2010 FAST ADC 60MHz, 60MHz, Accurate PWM Accurate PWM FAST ADC FAST ADC
32-bit Core, 32-bit Core, 100MHz, DMA, 100MHz, DMA, FAST ADC & FAST ADC & PWM PWM 32-bit Core 32-bit Core 100 MHz, DMA 100 MHz, DMA FAST ADC & FAST ADC & PWM PWM
Production - Available NOW
<64kB
<32kB
Pin Compatible
MC56F802x MC56F802x 32MHz, HR PWM, 32MHz, HR PWM, ADC, DAC ADC, DAC MC56F801x MC56F801x 32MHz, 32MHz, HR PWM, HR PWM, ADC ADC 56F800x 56F800x V. Low Cost, V. Low Cost, HR PWM HR PWM
<16kB
Execution - Specification Frozen, in design Proposal - Specification Subject to Change
2009
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MC56F824x/MC56F825x Features

60 MHz/60 MIPS from 56800E core 2.7-3.6V operation 64K Bytes program FLASH 8K Bytes program/data RAM Flash security 8Mhz/100Khz tunable internal relaxation oscillator Software programmable phase locked loop Up to 60 MHz peripherals timers and PWMs

64KB Program Flash 8kB Data RAM
8ch 12-bit ADCA 8ch 12-bit ADCB CRC Crystal Oscillator
Prog Gain Amp Ax1,2,4 Prog Gain Amp Bx1,2,4 8-ch High Res PWM 1ch 12-bit DAC 3 5-bit DAC 3 Analog Comparators
56800E Core 60 Mhz

JTAG/EOnCE
PLL Relaxation OSC 2 x High Speed QSCIs 1 x QSPI 2x IIC/SMbus 1 x MSCAN 8Ch 16-bit Timer Inter-module Cross Bar
8 output PWM module 520ps PWM and PFM resolution
2-12-bit ADCs with total 16 inputs 600ns conversion rate built-in PGA with 1x, 2x, 4x, gains 1 12-bit digital to analog converter 3 5-bit digital to analog converters 3 analog comparators 8 16-bit enhanced GP multifunction
Voltage Regulator System Integration Module (SIM) Interrupt Controller COP POR LVI
programmable timers Cyclic redundancy check generator (CRC) Computer operating properly timer 2 high speed serial communications interface (SCI) 1 queued serial peripheral interface (QSPI) 1 MS-CAN bus 2 I2C/SMbus communications interface Up to 54 GPIOs Inter module cross-bar JTAG/EOnCE debug port Industrial temperature range: -40C to 105C with 60 Mhz
44LQFP, 48LQFP 64 LQFP, Samples Available
Breakthrough Features: New generation high speed PWM module

520 ps duty cycle and frequency resolution Flexible edge placement
High speed ADC with programmable gain amplifiers

600ns conversion rate Supports multi trigger source in one ADC scan
Inter-module cross bar Programmable inter module connection
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DSP56800E Core Architecture
Instruction Fetch: PAB - 21 bits PDB - 16 bits 1st Data Access: XAB1 - 24 bits CDBR - 32 bits CDBW - 32 bits 2nd Data Access: XAB2 - 24 bits XDB2 - 16 bits Operations Performed: 1st - PAB / PDB 2nd - XAB1 / DBRCDBW 3rd - XAB2 / XDB2
PC LA LA2 HWS FIRA FISR SR OMR LC LC2
PROGRAM CONTROLLER
INSTRUCTION DECODER INTERRUPT UNIT LOOPING UNIT
AGU
ALU1 ALU1
ALU2 ALU2
M 01 N3
R0 R0 R1 R1 R2 R2 R3 R3 R4 R4 R5 R5 N N SP SP
Program Memory
XAB1 XAB2 PAB PDB CDBW CDBR XDB2
Data Memory
IP-Bus Interface
BIT MANIPULATION UNIT EOnCE/JTAG TAP
A2 B2 C2 D2
A1 B1 C1 D1 Y0 Y1 X0
A0 B0 C0 D0
DATA ALU
External Bus Interface Multi-bit Shifter
MAC and ALU
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Mapping the Architecture to DSP Algorithms

y( n) = c(i )x( n i )
i=0 N 1
; Typical Digital Filter Formula
Parallel Move
Source 1 MACR X0,Y0,A OPCODE AND OPERANDS
Destination 1
Source 2
Destination 2
X:(R0)+N,Y0
X:(R3)-,X0
PRIMARY READ SECONDARY READ (Uses XAB1 and CGDB) (Uses XAB2 and XDB2)
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Mapping the Architecture to DSP Algorithms

PROGRAM CONTROLLER
PC LA LA2 HWS FIRA FISR SR OMR LC LC2 INSTRUCTION DECODER INTERRUPT UNIT LOOPING UNIT
AGU
ALU1 ALU1
ALU2 ALU2
M 01 N3
R0 R0 R1 R1 R2 R2 R3 R3 R4 R4 R5 R5 N N SP SP
Program Memory
XAB1 XAB2 PAB PDB CDBW CDBR XDB2
Operations Performed: Multiply-Accumulate 3 Memory Accesses 2 Address Additions Instruction Fetch:

PAB PDB - 21 bits - 16 bits
Data Memory
BIT MANIPULATION UNIT EOnCE / JTAG TAP
A2 B2 C2 D2
A1 B1 C1 D1 Y0 Y1 X0
A0 B0 C0 D0
DATA ALU
IP-Bus Interface
1st Data Access:

XAB1 - 24 bits CDBR - 32 bits
MAC and ALU
Multi-bit Shifter
External Bus Interface
2nd Data Access:

XAB2 - 24 bits XDB2 - 16 bits
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Pulse Width Modulation Modules
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Pulse Width Modulator (PWM) MC56F800x, MC56F80xx

Clock PWM up to 96Mhz Three complementary signal pairs or six independent
signals or combinations
Complementary channel operation Separate deadtime insertions for rising and falling edge Separate top and bottom polarity control Edge-aligned or center-aligned signals 15-bits of resolution Half-cycle reload capability Asymmetric mode of operation (for phase shifting) Programmable integral reload rates (half to 16) Individually software-controlled PWM outputs ADC synchronization Up to 4 programmable fault inputs PWM compare output polarity control 8 or 4 mA current source/sink Output polarity control Write protected registers Double-buffered PWM registers Wait/debug mode operation Selectable PWM supply source for each
complementary PWM signal pair (F8000 family only)

PWM generator External GPIO Internal timer channel ADC conversion result, taking into account values setting ADC high and low limit register
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Enhanced Flex Pulse Width Modulator (eFlexPWM) 56F824x/5x

Four independent sub-modules with own time base, two PWM
outputs + 1 auxiliary PWM input/output 16 bits resolution for center, edge aligned, and asymmetrical PWMs Fractional delay for enhanced resolution of the PWM period and edge placement Complementary pairs or independent operation Independent control of both edges for each PWM output Synchronization to external hardware or other PWM submodules Double buffered PWM registers Integral reload rates from 1 to 16 include half cycle reload Half cycle reload capability Multiple output trigger events per PWM cycle Support for double switching PWM outputs Fault inputs can be assigned to control multiple PWM outputs Programmable lters for fault inputs Independently programmable PWM output polarity Independent top and bottom deadtime insertion Individual software control for each PWM output Software control, and swap features via FORCE_OUT event Compare/capture functions for unused PWM channels Enhanced dual edge capture functionality
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eFlexPWM - Sub-Module Detail
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eFlexPWM PWM Generation
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eFlexPWM Edge Aligned PWM Generation

VAL1 ($0100) VAL5 ($0000) VAL3 INIT ($FF00) VAL2, VAL4 = $FF00
CH0b
CH0a
All PWM-on values are set to the init value, and never changed again. Positive PWM-off values generate pulse widths above 50% duty cycle . Negative PWM-off values generate pulse widths below 50% duty cycle . This works well for bipolar waveform generation.
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eFlexPWM Center Aligned PWM Generation

VAL1 ($0100) VAL3 VAL5 ($0000) VAL4 VAL2 INIT ($FF00)
Ch0a
Ch0b
When the Init value is the signed negative of the Modulus value, the PWM module works in signed mode. Center-aligned operation is achieved when the turn-on and turn-off values are the same number, but just different signs.
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eFlexPWM Shifted PWM Generation

VAL1 ($0100) VAL5 VAL3 ($0000) VAL4 VAL2 INIT ($FF00)
CH0a
CH0b
In this example, both PWMs have the same duty-cycle. However, the edges are shifted relative to each other by simply biasing the compare values of one waveform relative to the other.
Alternatively, if the waveforms are generated by different sub-modules, the waveforms can be shifted by simply changing the Init value of one sub-module relative to the other.
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eFlexPWM Force Output Logic
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eFlexPWM Complementary and Deadtime Logic
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eFlexPWM Fractional Delay and Output Logic
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eFlexPWM High Resolution Duty Cycle Generation

PWM
resolution is given by input clock of PWM module Example:

Lets generate PWM signal with MODULO=4, DUTY_CYCLE=2 (50 %)
0011
0000 tclk
tPWM
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PWM The
resolution is given by input clock of PWM module
PWM resolution can be enhanced by analog delay circuit, which can place edge between two edges, derived from input clock

Example:
Consider 2-bit analog delay block Lets generate PWM signal with MODULO=4:0, DUTY_CYCLE=2:3 (68.75 %)
0011:00
0000:00 tclk
tPWM
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At

high resolution duty cycle generation

The leading edge is usually aligned with digital clock The falling edge is generated by delay block The analog delay is constant every PWM period
0010:11 0000:00 0000:00
0010:11 0000:00
0010:11
0011:00 0010:11
0000:00 tclk ttimer tPWM PWM output using delay block DUTY_CYCLE = 0010:11 PWM output w/t delay block DUTY_CYCLE = 0010 Timer clock
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eFlexPWM High Resolution Frequency Generation

Example:

Consider 2-bit analog delay block Lets generate PWM signal with MODULO=4:2, DUTY_CYCLE=2:1 (50 %)
0011
0000 tclk
tPWM
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Example:

Consider 2-bit analog delay block Lets generate PWM signal with MODULO=4:2, DUTY_CYCLE=2:1 (50 %)
0011:00
0000:00 tclk
tPWM
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At

high resolution frequency generation

Both edges are generated by delay block The analog delay is changing edge by edge every PWM period The analog delay must be calculated every edge or requires some hardware support
0000:00
0011:00 0010:01 0010:00 0001:00 0000:10 0000:00 tclk ttimer tPWM
0010:01
0000:10
0010:11
0000:00 + 1clk
0010:01
PWM output using delay block period = 0100:10
PWM output w/t delay block period = 0100
Timer clock
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eFlexPWM HR Frequency Generation HW Support

Need
to calculate the next edge position for rising and falling edges within very short period not fast enough, so need hardware adder shows 21 bit adder to control both edges automatically setting new comparator values after each edge has been triggered
Ideal timing 16 bits at IP Bus timing resolution 5 bits NanoEdge timing resolution
Actual timing 16 bits at IP Bus timing resolution 5 bits NanoEdge timing resolution
Timer 16 bits at IP Bus timing resolution 5 bits NanoEdge timing resolution
Software
16 bit + 5 bit adder
Diagram
PWM Period N
PWM Period N-1

5 bits from previous NEP calculation
PWM Period N
PWM reload times are restricted to 16-bit IP bus timing (truncation of 21 bit value). Any residual left over from PWM period N-1 needs to be added back to period N.
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eFlexPWM HR Frequency Generation from User Perspective

The The
new edge calculation is seem less from user perspective
user sets required 21-bit (16+5 bit) values into corresponding value registers only 5-bit delay block corresponds to 1.92 GHz input clock (for 60MHz PWM module input clock)
16-bit digital value
PWM Value Register NanoEdgeTM placement not used. 16-bit value only.
The

PWM Value Register
5-bit nanoedge value PWM Fractional Value Register
NanoEdgeTM placement enabled. 21-bit (32-bit) value.
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eFlexPWM HR Frequency Generation from User Perspective

Example

of high resolution calculation
For high frequency the digital value is usually less than 11 bits. For example, 200 kHz edge-aligned PWM has resolution less than 9 bits Therefore we can keep calculation in 16 bits Result of calculation is moved right by 5 bits and written into 32-bit register
5-bit nanoedge value
Internal User Representation

PWM Value Register
5-bit nanoedge value PWM Fractional Value Register
NanoEdgeTM placement enabled. 21-bit (32-bit) value.
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Analog to Digital Converters
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A/D Converter MC56F800x

Two ADC modules allowing parallel conversion Input voltage range from VSSA to VDDA Up to 28 analog inputs Output in 12-, 10- or 8-bit right-justified format Single or continuous conversion (automatic return to idle after single conversion) 2.5 s conversion time Configurable sample time and conversion speed/power Conversion complete flag and interrupt Input clock selectable from up to four sources Operation in wait or stop modes for lower noise operation Asynchronous clock source for lower noise operation Hardware and software triggering Temperature sensors that are routed to ANA26 and ANB26 Support up to four samples per conversion
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Programmable Gain Amplifier (PGA) MC56F800x

Sampled PGA architecture Common mode noise and offset cancelation Synchronized with PWM operation 0.14 MSPS maximum Sampling time can be precisely controlled (to less than 0.1 s) Programmable gains (1, 2, 4, 8, 16, and 32) Selectable tradeoff for slower/low power versus faster/more power Rail-to-rail input voltage range Single-ended output routed directly to on-chip ADCs ANA15 and ANB15 Software and hardware triggers are available Includes additional calibration features: Offset calibration eliminates any errors in the internal reference used to generate the VDDA/2 output center point Gain calibration can be used to verify the gain of the overall datapath Both features require software correction of the ADC result
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12-bit resolution Maximum ADC clock frequency is 5.33 MHz Sampling rate up to 1.6 million samples per second Sequential: First 1.6s subsequent 1.125s Simultaneous: 8 conversions in 4.97s Internal or external Vref ADC can be synchronized to a PWM via the SYNC signal High and low limits can control PWM outputs Simultaneous or sequential sampling Internal multiplexer to select two of eight inputs Ability to sequentially scan and store up to eight measurements Ability to simultaneously sample and hold two inputs Optional interrupts at the end of a scan, if an out-of-range limit is exceeded, (high or low) or at zero crossing Optional sample correction by subtracting a pre-programmed offset value Signed or unsigned result Single-ended or differential inputs for all input pins with support for an arbitrary mix of input types Auto-standby mode to reduce power consumption Power savings modes allow automatic shutdown/startup of all or part of ADC
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A/D Converter MC56F802x/3x

Differences

from 56F801x devices:
16 sample and result registers First 8 samples support high/low limits, zero-crossing and offset features only
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A/D Converter MC56F824x/5x

Differences
from 56F802x/3x devices:

8x HIGH LIMIT
8x Gain Setting X1, x2, x4 AN0 AN1

MUX
LOW LIMIT
IRQ Logic
ADC input clock 10 MHz (conversion time 850/600 ns) Integrated PGA with gain 1x, 2x, 4x Support multi-trigger operation
> <
Above IRQ
Below
Zero Crossing Logic

V+
PGA
V-
12Bit ADC
RESULT MUX
ANx Vrefl
ADC RESULT
16x
Channel Select Single Ended or Differential
ADC OFFSET
8x
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Analog Comparators
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Analog Comparator MC56F802x/3x
PSEL [0,2] CIN_A0 CIN_A1 CIN_A2 DAC_A
M U X
Power Down PDN INV
Falling Edge Interrupt Request Rising Edge Interrupt Request Programmable Glitch Filter COUT To Timer A1 To PWM To GPIO
Export Source Select ESEL [0,1] Export to CMP_B
Negative input Source Select NSEL [0,2]
CMP_A
0 1
M U X
Import From CMP_B
M U X
To PWM Fault 1
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Analog Comparator MC56F802x/3x

Up
to two continuous-time differential-input analog comparator modules Internal switching matrix supports the independent connection of the analog inputs to the positive or negative input of the analog comparator and to the comparators export output for another comparator module. 5 selectable input sources:

Three GPIO pins One DAC output One import input from another comparator module
Programmable
comparator output polarity Comparator output edge indicator Interrupt can be generated by comparator output rising edge, or falling edge, or both edges Comparator output can be fed to timer input, PWM faults input, PWM source, external pin output Software controlled power down mode
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Analog Comparator MC56F800x, MC56F824x/5x

Operates over the entire supply range Less than 40 mV of input offset Less than 15 mV of hysteresis Inputs may range from rail to rail Selectable interrupt on rising edge, falling edge, or both edges of comparator output Selectable inversion on comparator output
Two software selectable performance levels:

Shorter propagation delay at the expense of higher power Low power, with longer propagation delay Sampled Windowed (ideal for certain PWM zero-crossing-detection applications) Digitally filtered Filter can be bypassed
Comparator output may be:

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Timers
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Quad Timer All DSCs

Quad-Timer Channel
MUX MUX COUNTER COMPARATOR COMPARATOR
PRESCALER
OUTPUT
OFLAG
Primary Input
INPUTS OTHER INPUTS
Output
Secondary Input
CONTROL STATUS & CONTROL
TMRLOAD
TMRHOLD
CAPTURE
TMRCMP1
TMRCMP2
CMPLD1
CMPLD2
DATA BUS
4x
Unique architecture with 2x Inputs (primary + secondary) and 1x output Powerful MUX - primary input, secondary input and output can be connected to external pins Individual channel capability - input capture trigger, output compare, clock source, prescaler Counters are pre-loadable, count once or repeatedly Master operation - any channel can be a master that broadcasts its compare signal to the other channels. This way
they can be configured to reinitialize their counters and/or force their OFLAG output signals to predetermined values. Compare - The TMRCMP1/2 registers provide the compare values (up/down) for the counter. If a match occurs, the OFLAG signal can be set, cleared, or toggled (polarity is selectable). If enabled, an interrupt is generated, and the new compare value is loaded into TMRCMP1 or 2 registers from TMRCMPLD1 and 2 (as enabled). Capture register stores a copy of the counters value when an input edge (positive, negative, or both) is detected. Once a capture event occurs, no further updating of the capture register will occur until the input edge flag is cleared.
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Quad Timer Operating Modes

Stop Mode: Counter is inert. No counting will occur Count Mode: Counts rising or falling edges
(generating periodic interrupts, timing purposes)
Edge Count Mode: Counts rising and falling edges
Gated Count Mode: Counts primary input if secondary
(counting of simple encoder wheel)
input is high (signal width measurement)
Signed Count Mode: Counts primary input up or down
Cascaded Count Mode: Input is connected to the
based on polarity of secondary input
output of another (great for large counts up to 264)
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Triggered Count Mode: Start/Stop count of primary input on rising edge of secondary input.
One-Shot Mode: Provides timing delays
(ADC acquisition of new samples until a specified period of time has passed since the PWM sync signal occurred)
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Fixed Frequency PWM: Fixed frequency, variable Variable Frequency PWM: Variable frequency
duty cycle (driving PWM amplifiers)
and duty cycle (driving PWM amplifiers)
Pulse Output Mode: Supports stepper motor
Quadrature Count Mode
systems and provides change of signal frequency and number of pulses

Count Mode Primary Count Output
Timer Stopped due to Compare (COMP1 = 4)
Counter will decode the primary and secondary external inputs as quadrature encoded signals Compare interrupts will signal commutation
Timer is Off
Timer is in Count Mode
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Others
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Crossbar Switch - MC56F824x/5x

Flexible
signal interconnection among peripherals Connects any of 22 signals on left side to the output on right side (multiplexer) Total 30 multiplexers All multiplexers share the same set of 22 signals Increase flexibility of peripheral configuration according to user needs
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Crossbar Inter-module Connection - MC56F824x/5x

5-bit VREF
12-bit DAC output
Trigger[1:0] 0 1 2 3
HSCMP
Pin
3
Dual 12bit ADC

DAC input for test only
Pin ADC_In
12-bit DAC output
3 0 2 1
Crossbar Fabric
To comparators
12-bit DAC Output
Pin
SYNC_IN
3 Window / Sample[2:0]
X3 Quad Timer B
TB[3:0]
4 4
12-Bit DAC
Pin
X4
OUT_TRIG0[2,0] OUT_TRIG1[2,0]
X6
4
OR Functions
I/O Module
I/O Muxing
X9
PWMA[3:0] PWMB[3:0] PWMX[3]
8-ch GHzPWM
2 OUT_TRIG0[3] OUT_TRIG1[3] EXTA[3:0] 14 EXT_SYNC[3:0] EXT_FORCE EXT_CLK FAULT[3:0]
Pin I/O Module

peripheral functions
X6
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ADC to PWM Synchronization
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Why Is ADC to PWM Synchronization Needed?

ADC
sampling helps to filter the measured current - antialiasing

PWM Period
Asynchronous Sampling
Average Current
Inductor Current
Sampled Current
Synchronized Sampling PWM 0
ADC trigger Signal

A/D calc. Data Processing and New PWM Parameters Calculation
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Why Is ADC to PWM Synchronization Needed?

Phase
+U/2
PWM At PWM Bt Phase A PWM Ab PWM Bb PWM Ct Phase B PWM Cb Phase C
PWM2 Q AB
current can be sensed for certain time only

DC Bus
PWM1 Q AT
Shunt resistor
Shunt resistor Ground
Dead Time
- U/2
I sense_A
time to sensing stabilized current sampling window
3-ph AC Induction Motor 3-ph PM Synchronous Motor
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ADC to PWM Synchronization: MC56F80xx

Smart
combination of the PWM + QTimer + ADC allows precise control of the sample event The PWM synch output is connected to secondary input of QTimer - Ch3 The QTimer Ch3 output is connected to ADC SYNC0 The QTimer Ch2 output is connected to ADC SYNC1 The ADC sample can be easily synchronized with PWM with no software overhead (constant delay). Note the delay also can be applied to the external trigger signal Cycle-by-cycle control of the QTimer addresses advanced ADC trigger delay control
PWM
IP BusCLK PWM Sync
MUX
ADC SYNC1
ADCB ADCA
ADC SYNC0 * can be used to mimic ADC SYNC pulse during debugging
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ADC to PWM Synchronization Details: MC56F80xx
QTimer Ch3 settings:

Primary input: System clock Secondary Input: 3-th input (PWM synch) Operation mode: Triggered mode Count length: Count until compare and reinitialize Output mode: Clear on secondary, set on compare
PWM COUNTER
PWM SYNC
PWM
GENERATOR OUTPUTS 0, 1
dead-time/2 dead-time/2
PWM
PINS 0, 1
POWER
t1 - time between PWM SYNC signal and TMR3 output. TMR3 output starts ADC conversion immediately. t2 ADC conversion time
STAGE VOLTAGE
dead-time
dead-time
TMR3
COUNTER
TMR3
t1 t2
OUTPUT
ADC CONVERSION
ADC
ISR
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ADC to PWM Synchronization: MC56F800x
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Programmable Delay Block Operation Modes MC56F800x
Individual Operation
Each ADC is controlled individually
ORed Operation
Both ADC converters operate in ping pong mode. Up to four samples can be taken per conversion sequence
Pulsed (PWM) Operation

This mode can be used for window operation of high speed comparator The output can be connected to pin and generated PWM signal
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ADC to PWM Synchronization: MC56F800x (Individual mode)
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ADC to PWM Synchronization: MC56F800x (ORed Mode)
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ADC to PWM Synchronization: MC56F800x (ORed Mode)
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ADC to PWM Synchronization: MC56F824x/5x

5-bit VREF
12-bit DAC output
Trigger[1:0] 0 1 2 3
HSCMP
Pin
3
Dual 12-bit ADC

DAC input for test only
Pin ADC_In
12-bit DAC output
3 0 2 1
Crossbar Fabric
To comparators
12-bit DAC Output
Pin
SYNC_IN
3 Window / Sample[2:0]
X3 Quad Timer B
TB[3:0]
4 4
12-Bit DAC
Pin
X4
OUT_TRIG0[2,0] OUT_TRIG1[2,0]
X6
4
OR Functions
I/O Module
I/O Muxing
X9
PWMA[3:0] PWMB[3:0] PWMX[3]
8-ch GHzPWM
2 OUT_TRIG0[3] OUT_TRIG1[3] EXTA[3:0] 14 EXT_SYNC[3:0] EXT_FORCE EXT_CLK FAULT[3:0]
Pin I/O Module

peripheral functions
X6
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eFlexPWM PWM Generation
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ADC to PWM Synchronization Details: MC56F824x/5x
8-ch eFlexPWM
OUT_TRIG0[0]
submodule 0
OUT_TRIG1[0]
OR
crossbar input[16] crossbar input[17]
Crossbar Fabric
OUT_TRIG0[1]
submodule 1
OUT_TRIG1[1]
OR
OR
crossbar input[19]
OUT_TRIG0[2]
submodule 2
OUT_TRIG1[2]
OR
crossbar input[18]
OUT_TRIG0[3]
crossbar input[20] crossbar input[21]
submodule 3
OUT_TRIG1[3]
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Low Cost Current Measurement Single Shunt Current Reconstruction
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Single Shunt Current Reconstruction
+U/2
PWM At PWM Bt Phase A PWM Ab PWM Bb PWM Ct Phase B PWM Cb
DC Bus
Phase C
Shunt resistor
- U/2
3-ph AC Induction Motor 3-ph PM Synchronous Motor
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Single Shunt Current Reconstruction - Analysis
(000)(100) (110) (111) (110) (100)
Measurement Table
DC-Link current idc +ia -ic +ib -ia +ic -ib 0 0
V1(100) V2(110) V3(010) V4(011) V5(001) V6(101)
Voltage Vector
A B C
iDC=-ic iDC=+ia iDC=0 iDC=0
iDC=-ic iDC=+ia
V7(111)
t delay = t deadtime + t progdelay
V0(000)
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Single Shunt Current Reconstruction - Issues

Two
current samples cannot be taken:
1. Voltage vector is crossing a sector border

Only one sample can be taken Sampling intervals too short None of current samples can be taken
2. Low modulation indexes

Passing Active Vector
Low Modulation Index
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Single Shunt Current Reconstruction - Solution

Asymmetrical
PWMs
Case 1 Passing active vector:

Freeze center edge Move one critical edge Goes for higher modulation indexes
Critical edge
Move critical edge
Case 2 Low modulation indexes:

Freeze center edge Move both side edges in opposite direction Goes for low modulation indexes
Critical edges
Move critical edges
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Single Shunt Current Reconstruction MC56F8013 Implementation
PWM Modulo Counter
Compare level sample #2 Compare level sample #1 Compare level sample #0
Timer ch. 3 Counter
ADC Conversion
Conversion time each 2.48us ISR duration each 0.92us
ADC End-of-Scan ISR
PWM Reload ISR
ISR duration cca. 13.8us
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BLDC Motor Commutation
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Six
Step BLDC Motor Control
Voltage applied on two phases only

+U/2
PWM At PWM Bt Phase A PWM Ab PWM Bb PWM Ct Phase B PWM Cb Phase C DC Bus
Shunt resistor
- U/2
3-ph Brushless DC Motor
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Six

Step BLDC Motor Control
Voltage applied on two phases only It creates 6 flux vectors Phases are powered based on rotor position The process is called commutation
Phase voltages
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Complementary
bipolar PWM switching
Q1=Q4=PWM; Q2=Q3=Q1
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BLDC Motor Commutation MC56F800x, MC56F80xx

PWM Channel Control Register SWAP MASK
A
70% 70%
B
70%
0 0 0 0 0 0
0 0 0
1.
30%
3.
30%
5.
30%
One shot write to all six One shot write to all six PWM channels! PWM channels! Value written to this register Value written to this register defines just the speed of defines just the speed of motor rotation and motor rotation and
2.
4.
6.
PWM Value Register 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1
5999h 70% of max. value of Duty Cycle when 7FFFh is the max. value
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PWM Channel Control Register SWAP MASK
A
70% 0%
B
70%
0 0 0 0 1 1 6. 5. 4. 3. 2. 1. transistors
0 0 0
1.
0%
3.
30%
5.
30%
Mask will disable Mask will disable the complementary the complementary transistor pair transistor pair
2.
MASK
4.
6.
PWM Value Register 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1
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Mask and Swap are set simultaneously! Mask and Swap are set simultaneously! Value written to this register defines the Value written to this register defines the exact commutation stage. exact commutation stage.
PWM Channel Control Register SWAP MASK 0 0 0 0 1 1 6. 5. 4. 3. 2. 1. transistors 0 0 1 CBA phases
A
0% 70%
B
30%
1.
0%
3.
30%
5.
70%
Swap reroutes the top Swap reroutes the top and bottom control and bottom control signals of complementary signals of complementary pair pair
2.
4.
6.
PWM Value Register SWAP 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1
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Advantage:

The MASK and SWAP feature is asynchronous to PWM generation Speed control and commutation control are fully independent
The The
same approach can be used on 56F82xx using FORCE_OUT logic
56F82xx allows preloading of new state and time for next commutation. The commutation is performed based on timer event
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Motor Control and Energy Conversion Demos
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Sensorless BLDC Motor Control Using MC9S08MP16

Six
step commutation Sensorless back-EMF zero crossing detection technique Back-EMF zero crossing detection using internal comparators Running on MC9S08MP16 Both directions of rotation Speed closed loop control Torque closed loop control Target applications:
Fans Compressors Pumps Appliances
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Sensorless PMSM Motor Control Using MC56F80xx

MC56F80xx digital signal controller 3-phase AC/BLDC high voltage power stage board 1-phase line input 110/230VAC @ 50/60Hz Appliance PM motor Initial rotor position detection Full torque at motor start-up Field weakening Application based on C-callable library functions (GFLIB, GDFLIB, MCLIB, ACLIB) Current control loop execution time: 55us Speed control loop with field weakening execution time : 17us Flash: ~ 6KB, RAM ~ 1.5KB Reference design manual
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AC/DC Switch Mode Power Supply

500W digitally controlled LLC resonant converter Input voltage
85-265Vac @ 45-65Hz 12V/41 Amps (max.) 5V/25 Amps (max.) 500W shared by both voltage outputs. The power limit can be set individually by SW for each voltage output. PM bus communication (HW ready) CAN communication (HW ready) Communication with PC using USB Over-voltage, over-current, overtemperature on both primary and secondary side. Active controlled cooling
Output voltage

Output power
Communication

Full fault protection
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Solar Inverter using MC56F8023

400
VA digitally controlled solar inverter One or two 200Wp solar panels On grid/off grid operation
Single
phase output 230V/50Hz or 115V/60Hz Optional battery charger MPPT algorithm implemented Over-current, short circuit, input under-voltage protection
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TM

Freesclae Motor Control

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June, 2010

Roadmap Update DSCs Overview

and SMPS Demos presented at FTF in Orlando

What is a Digital Signal Controller?

Instructions optimized for controller code, DSP, matrix operations

When is a Digital Signal Controller a Good Fit?

Motor control Digital power conversion Advanced lighting control

MC56F816x MC56F816x 40MHz 40MHz

MC56F815x MC56F815x 40MHz 40MHz

MC56F835x MC56F835x 60MHz 60MHz

MC56F814x MC56F814x 40MHz 40MHz

MC56F833x MC56F833x 60MHz 60MHz

MC56F832x MC56F832x 60MHz 60MHz

40MHz 40MHz Ultra Low Cost Ultra Low Cost

MC56F812x MC56F812x 40MHz 40MHz

40MHz 40MHz Ultra Low Cost Ultra Low Cost

Execution - Specification Frozen, in design Proposal - Specification Subject to Change

Cost-Effective 56F8000 Solutions (56F801x)

56800E Core 32MHz

Package: 32LQFP In Production

56F8000 Family Expansion (56F802x/56F803x)

56800E Core 32MHz

Voltage Regulator COP Power-On-Reset

Package 32 LQFP, 44LQFP, 48LQFP, 64LQFP In Production

Ultra Low Cost: 56F800x

56800E Core 32MHz

Voltage Regulator COP Power-On-Reset Power Supervisor

Package: 28SOIC, 32SDIP , 32LQFP, 48 LQFP In Production

56F8000 Series Feature Summary

On Chip Relaxation Osc. Yes

IDD = 45.6mA;IDDA = 4.5mA

IDD = 42mA; IDDA = 13.5mA

IDD = 48mA; IDDA = 18.8mA

IDD = 48mA; IDDA = 18.8mA

MC56F816x MC56F816x 40MHz 40MHz

MC56F815x MC56F815x 40MHz 40MHz

MC56F835x MC56F835x 60MHz 60MHz

MC56F814x MC56F814x 40MHz 40MHz

MC56F833x MC56F833x 60MHz 60MHz

MC56F832x MC56F832x 60MHz 60MHz

40MHz 40MHz Ultra Low Cost Ultra Low Cost

MC56F812x MC56F812x 40MHz 40MHz

40MHz 40MHz Ultra Low Cost Ultra Low Cost

Execution - Specification Frozen, in design Proposal - Specification Subject to Change

64KB Program Flash 8kB Data RAM

8ch 12-bit ADCA 8ch 12-bit ADCB CRC Crystal Oscillator

56800E Core 60 Mhz

8 output PWM module 520ps PWM and PFM resolution

44LQFP, 48LQFP 64 LQFP, Samples Available

Breakthrough Features: New generation high speed PWM module

High speed ADC with programmable gain amplifiers

Inter-module cross bar Programmable inter module connection

DSP56800E Core Architecture

XAB1 XAB2 PAB PDB CDBW CDBR XDB2

BIT MANIPULATION UNIT EOnCE/JTAG TAP

External Bus Interface Multi-bit Shifter

MAC and ALU

Mapping the Architecture to DSP Algorithms

; Typical Digital Filter Formula

Source 1 MACR X0,Y0,A OPCODE AND OPERANDS

Mapping the Architecture to DSP Algorithms

Operations Performed: Multiply-Accumulate 3 Memory Accesses 2 Address Additions Instruction Fetch: