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System
Mukesh Maheshwari
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2
VHDL
INTRODUCTION
ELEMENTS OF VHDL
2
3
Introduction
WHAT IS VHDL ?
FEATURES OF VHDL
HISTORY OF VHDL
LEVELS OF ABSTRACTION 3
4
What is VHDL?
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7
Sequential Language
7
Timing Specification 8
Example:
process
begin
clk <= ‘0’;
wait for 20ns;
clk <= ‘1’;
wait for 12ns;
end process;
8
Test Language 9
Test bench
Is part of a VHDL model that generates a set of test
vectors and sends them to the Module being tested.
Collects the responses made by the Module Under Test
and compares them against a specification of correct
results.
Need
To ensure that design is correct.
Model is operating as required.
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10
Design Hierarchy
10
Design libraries 11
Design Unit
Is any block of VHDL code or collection of VHDL
codes that may be independently analysed and
inserted into a design library.
Design Library:
Is a storage facility in which analysed VHDL
descriptions are stored.
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12
History of VHDL
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Logic Systems 14
Multivalued logic
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17
Basic Building Blocks
Entity
A design’s interface to the external circuitry.
Architecture
Describes a design’s behavior and functionality.
Configuration
Binds an entity to an architecture when there are multiple
architectures for a single entity.
Package
Contains frequently used declarations, constants,
functions, procedures, user data types and components.
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18
Basic Building Blocks
Library
Is a collection of compiled VHDL units
Promotes sharing of compiled designs and hides the
source code from the users
Commonly used functions, procedure and user data types
can be compiled into a user-defined library for use in all
designs
Library should be declared before EACH entity declaration
even if it is in the same VHDL file.
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Entity
Example :
entity and_gate is
port ( 1A, 2A, 3A, 4A : in std_logic;
1B, 2B, 3B, 4B : in std_logic;
1Y, 2Y, 3Y, 4Y : out std_logic
);
end and_gate ;
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Entity 20
Entity Declaration
Defines the input and output ports of the design.
Each port in the port list must be given,
• a name
• data flow direction
• a type.
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Entity 21
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22
Modes
entity driver is
port ( A : in std_logic;
B : out std_logic;
Data : inout std_logic;
Count : buffer std_logic Drivers reside
); outside the entity
end driver ;
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Mode OUT
entity driver is
port ( A : in std_logic;
B : out std_logic;
Data : inout std_logic;
Count : buffer std_logic )
; Drivers reside
inside the entity
end driver ;
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Mode INOUT
Bi-directional
Entit
Value can be read and assigned
y
Port
Example: signal
entity driver is
port ( A : in std_logic;
Data
B : out std_logic;
Data : inout std_logic;
Count : buffer std_logic )
; Signal can
end driver ; be read
inside the
Drivers may reside both entity
inside and outside the entity
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Mode BUFFER
Entity
Output port with Internal read
capability
Example:
Count
Driver reside
entity driver is Inside the entity
port ( A : in std_logic;
B : out std_logic;
Data : inout std_logic;
Count : buffer std_logic ) Signal inside can be
; read inside the entity
end driver ;
26
Architecture 27
Specifies,
Behavior
Function
Relationship between inputs and outputs of an
entity.
Syntax:
architecture architecture_name of entity_name is
declarations
begin
concurrent_statements
end [ architecture_name ];
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Architecture 28
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Architecture
29
VHDL Design Styles or Hardware Design
Modeling
VHDL Design
Styles
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31
Architecture Bodies
Behavioral
Consists of a set of
assignment statements to
represent behavior.
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32
Architecture Bodies
Dataflow
Use concurrent
signal
assignment
statements.
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33
Architecture Bodies
Structural
Components from
libraries are connected
together.
Consists of VHDL
netlists.
It is possible to mix the three Modeling styles in a single
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architecture body.
34
Comparing Architectural Bodies
34
35
Language Elements
OBJECTS
OPERATORS
AGGREGATES
35
OBJECTS 36
Objects are used to represent & store the data in the system
being described in VHDL.
Object contains a value of a specific type. For ex:
object
results in an object
SIGNAL COUNT : INTEGER called count which holds
integer value
class Data type
CONSTANTS :These
: are identifiers with fixed value.
Example:
constant Bus_Width : Integer := 16;
constant CLK_Period : Time := 15 ns;
process ( a )
Note : a_int contains the total
variable a_int : integer := number of events that occurred
1;
on signal a
begin
a_int := a_int + 1;
end process;
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Scalar Data Types
ENUMERATION TYPES :
This declaration defines a set of user-defined values
consisting of identifiers & character literals.
41
Scalar data types 42
44
Data Operators 45
Relational Operators
Shift Operators
Adding Operators
Multiplying Operators
45
46
Logical Operators
Incorrect Examples:
port ( a, b : bit_vector (3 downto 0);
e : bit_vector (1 downto 0);
h, i, j, k : bit;
l, m, n : boolean );
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49
Shift Operators – VHDL 93
Each operator
Takes an array of BIT or BOOLEAN as the left operand
Integer value as the right operand
+ - &
Addition subtraction
concatenation
Concatenation Operator (&)
Operands can be one-dimensional array type or element
type
“&” Operator works on vectors only.
Example:
signal a: std_logic_vector ( 5 downto 0 );
signal b,c,d: std_logic_vector ( 2 downto 0 );
begin
b <= ‘0’ & c(1) & d(2);
a <= c & d;
end; 51
52
Adding Operators
architecture bad of ex is
signal a : std_logic_vector ( 2 downto 0 );
signal b : std_logic_vector ( 3 downto 0 );
begin
‘0’ & a <= b; -- Error!
end bad;
52
Multiplying Operators 53
* / mod rem
Abs **
The abs operator has only one operand. It allows defining the
operand’s absolute value. The result is of the same type as
the operand.
Aggregates:
Assigns values to the elements of an array.
Example :
a <= ( others => ‘0’; ) identical to a <= “00000”
Example:
55
Aggregates 56
Concurrent Statements
Consider
X = X+Y;
In software:
X and Y are register
locations
The contents of X
and Y are added and
the result is stored
in X.
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Concurrent Statements
In concurrent
statements, there
are no implied
registers.
Feedback is
described around
Combinational
logic.
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Drivers
60
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Drivers
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Selected Signal Assignment – ‘when’ statement
Z <= A when
ASSIGN_A = '1'
else
B when
ASSIGN_B = '1'
else
C; 62
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Selected Signal Assignment – ‘when’ statement
63
64
Selected Signal Assignment – ‘with’ statement
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Selected Signal Assignment – ‘with’ statement
signal A, B, C, D, Z: std_logic;
signal CONTROL: std_logic_vector
(1 downto 0);
with CONTROL select
Z <= A when "00",
B when "01",
C when "10",
D when "11";
‘0’ when others;Why
“
when others” clause?
process (sel, a, b, c, d)
begin
If sel(2) = ‘1’ then
y <= a;
elsif sel(1) = ‘1’ then
y <= b;
elsif sel(0) = ‘1’ then
y <= c;
else
y <= d; • Generates a priority structure.
end if;
• Corresponds to “when-else”
end process;
command in the concurrent part.
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Case Statement
statements.
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Case statement
process (sel,a,b,c,d)
begin
case sel is
when 0=> y <=a;
when 1=> y <=b;
when 2=> y <=c;
when others =>
y<=d;
end case;
end process;
70
Case statement 71
end case;
Process Statement – characteristics
Are executed one after another, in the order in which they are
written.
Can appear only in a Process or Subprogram.
Only sequential statements can use Variables.
“Process” is the primary concurrent VHDL statement used to
describe sequential behavior.
Statements in a process, are executed sequentially in zero
time.
Process Statement
Process places
only one driver on
a signal.
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Sensitivity List
76
Process statement
Combinatorial Process
Generates combinational logic
All inputs must be present in the sensitivity
list.
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Process Statement
Clocked Process:
Generates synchronous logic.
process (clk)
begin
if (clk’ event and clk =‘1’ )
then
Q < = D;
end if;
end process;
78
Process Statement 79
80
Loop statements 81
process ( Input )
Has a Boolean Iteration variable i : POSITIVE := 1;
Scheme. begin
Condition is evaluated L1: while i <= 8 loop
before execution. Output (i) <= Input (i+8)
;
i := i + 1;
end loop L1;
81
end process;
82
Loop Statements - For LOOP
Example : factorial := 1;
for number in 2 to N loop
factorial := factorial * number;
end loop;
82
Loop Statements – For LOOP 83
Syntax:
next;
next loop_label when condition;
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85
Loop statements – Next Statement
Example:
for J in 10 downto 5 loop
if sum < total_sum then
sum := sum + 2;
elsif sum = total_sum then
next;
else
null;
end if;
k : k+1;
end loop;
85
Loop statements – exit Statement 86
Exit Statement
Syntax:
exit;
exit loop_label when condition;
86
87
Loop statements – exit Statement
Example:
sum := 1; j := 0;
L3 : loop
J := J + 21;
sum := sum * 10;
if sum > 100 then
exit L3;
end if;
end loop L3;
Note:
Exit : Causes the specified loop to be terminated.
Next :Causes the current loop iteration of the specified
loop to be prematurely terminated; execution resumes with
the next iteration.
87
Component Instantiation
Syntax:
instance_name : component_name
port map (
[ port_name => ] expression
[port_name => ] expression);
88
Component Instantiation 89
entity ND4 IS
port ( IN1,IN2,IN3,IN4 : in BIT;
Z : out BIT);
end ND4;
architecture gate_arch of ND4 is
component ND2
port ( A, B: in BIT;
C : out BIT);
end component;
signal TEMP_1,TEMP_2 : BIT;
begin
U1: ND2 port map ( A =>IN1, B =>IN2, C=>TEMP_1 );
U2: ND2 port map ( A =>IN3, B =>IN4, C=>TEMP_2 );
U3: ND2 port map ( A =>TEMP_1, B =>TEMP_2, C=>Z );
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Component Instantiation 90
90
Generate Statement 91
91
Generate Statement 92
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Generate Statement 93
Example:
93
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Generate Statement
Example:
94
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Generate Statement
Example:
Example:
95
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Generate Statement
Example:
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GENERIC
It provides a powerful mechanism in VHDL to model
parameterized designs.
Syntex:-
entity entity_name is
generic (
const. name: const. type;
………..
………….;
port (
signal_name : mode signal_type;
……………………
……………………);
End entity_name;
97
EXAMPLE OF GENERIC STATEMENT WITH GENERATE
STATEMENT
Library ieee;
Use ieee.std-logic_1164;
Entity inv1 is
Generic ( two : positive := 5 );
port ( I :in bit_vector (two downto 0);
o :out vector (two downto 0));
end inv1;
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99
Wait Statement
Wait statement
Suspends the execution of a process or
procedure until some conditions are
met.
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Wait Statement
Example:
100
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Wait Statement
Illegal coding
Processes with a “wait” Statement
and “Sensitivity list” are illegal.
Example:
process ( clk )
begin
wait until clk = ‘1’;
q <= d;
end process;
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102
Hardware Modeling Examples
process (clk)
begin
if (clk'event and clk = '1')
then
out1 <= a and b;
end if;
end process;
104
Hardware modeling Examples-
Examples- Latch 105
105
Hardware modeling Examples – Latch 106
Completely specified
Conditional expression.
incompletely specified
process (en,a)
Conditional expression. begin
if en='1‘ then
process (en,a) out1 <= a;
begin else
if en='1' then out1 <='1';
out1<= a; end if;
end if; end process;
end process;
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Configuration 107
Need:
107
Configuration 108
Syntax:
108
PACKAGE
A file containing definations of objects.
Objects can be used in other programs.
All objects are global.
Syntex :-
:-
package package_name is
type declarations
signal/constant declarations
function/procedure declaration
end package_name;
use work.package_name.all
all;
110
Subprograms
Include :
functions and procedures
Commonly used pieces of code
Can be placed in a library, and then reused and
shared among various projects
Abstract operations that are repeatedly performed
Type conversions
Use only sequential statements, the same as
processes
111
Typical Locations of Subprograms
PACKAGE LIBRARY
PACKAGE BODY
global
FUNCTION / ENTITY
PROCEDURE local for all architectures
of a given entity
ARCHITECTURE
Declarative part
local for a given architecture
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Functions
113
Functions – basic features
Functions
Always return a single value as a result
FUNCTION
It always return a value.
It is used to generalised a perticular program for the use of other
program.
Syntax:-
function function_name (
signal names :signal tupe;
………………..
)return
return return_type is
type declarations
const. / variable declarations
…………………
…………………….
begin
sequential statements
115
end function_name;
Type conversion function (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------------
---------------------------------------
------------------
PACKAGE my_package IS
FUNCTION conv_integer (SIGNAL vector:
STD_LOGIC_VECTOR)
RETURN INTEGER;
END my_package;
----------------------------------------
---------------------------------------
116
------------------
Type conversion function (2)
PACKAGE BODY my_package IS
FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR)
RETURN INTEGER;
VARIABLE result: INTEGER RANGE 0 TO 2**vector’LENGTH -
1;
VARIABLE carry: STD_LOGIC;
BEGIN
IF(vector(vector’HIGH)=‘1’ THEN result:=1;
ELSE result := 0;
FOR i IN (vector’HIGH-1) DOWNTO (vector’LOW) LOOP
result := result*2;
IF (vector(i) = ‘1’ THEN result := result+1;
END IF;
RETURN result;
END conv_integer;
END my_package;
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Type conversion function (3)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_package.all;
------------------------------------------------
----------------------------------------------
---
ENTITY conv_int2 IS
PORT ( a: IN STD_LOGIC_VECTOR (0 TO 3);
y: OUT INTEGER RANGE 0 TO 15);
END conv_int2;
------------------------------------------------
----------------------------------------------
---
ARCHITECTURE my_arch OF conv_int2 IS
BEGIN 118
y <= conv_integer(a);
END my_arch;
Procedures
119
Procedures – basic features
Procedures
do not return a value
are called using formal and actual parameters the same way as
components
may modify parameters passed to them
each parameter must have a mode: IN, OUT, INOUT
parameters can be constants (including generics), signals
(including ports), and variables;
the default for inputs (mode in) is a constant, the default for
outputs (modes out and inout) is a variable
when passing parameters, range specification should be included
(for example RANGE for INTEGERS, and TO/DOWNTO for
STD_LOGIC_VECTOR)
120
PROCEDURE :-
It is alternate to function .
it doesnot return any value.
Syntex is also same as with function except return type;
121
EXAMAPLE OF FUNCTION
Use library ieee;
use ieee.std_logic_1164.all;
use ieee.std-logic_unsigned.all;
package fun is
function sum1 ( x,y :in std-lofic_vector (1 downto 0))
return std_logic_vector;
end fun;
package body fun is
function sum1 ( x,y :in std-lofic_vector (1 downto 0))
return std_logic_vector is
122
Use library ieee;
use ieee.std_logic_1164.all;
use ieee.std-logic_unsigned.all;
Use work.fun.all;
Entity fun2 is
port (a,b :in std_logic_vector(1 downto 0);
sum : out std_logic_vector(2 downto 0))
End fun2;
123
EXAMAPLE OF PROCEDURE
Use library ieee;
use ieee.std_logic_1164.all;
use ieee.std-logic_unsigned.all;
package pro is
procedure sum2 ( x,y :in std-lofic_vector (1 downto 0);
signal z :out std_logic_vector(2 downto0))
end pro;
Entity pro2 is
port (a,b :in std_logic_vector(1 downto 0);
sum : out std_logic_vector(2 downto 0))
End profun2;
125
Examples
126
And Gate
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity and1 is
Port(a:in std_logic;
b:in std_logic;
c1:out std_logic;
End and1;
Architechture behaviuoral of and1 is
Begin
Process(a,b)
Begin
If(a=‘1’and b=‘1’)then
C<=‘1’
Else c<=‘0’;
End if;
End process;
End behavioural;
Nand Gate
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity nand1 is
Port(a:in std_logic;
b:in std_logic;
c1:out std_logic;
End nand1;
Architechture dataflow of nand1 is
Begin
C<=a nand b;
End dataflow;
Xor Gate
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity xor2 is
Port(p:in std_logic;
q:in std_logic;
r:out std_logic);
End adder;
Architechture behavioural of xor2 is
Begin
r<=p xor q;
End behavioural;
Adder
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity adder is
Port(a:in std_logic_vector(3 downto 0);
b:in std_logic_vector(3 downto 0);
c1:in std_logic;
S:out std_logic_vector(3 downto 0);
C0:out std_logic;
End adder;
Architechture behavioural of adder is
Component fa is
Port(a:in std_logic;
b:in std_logic;
c1: in std_logic;
a : out std_logic;
c :out std_logic);
End component;
Signal ca :std_logic_vector(4 downto);
Begin
Ca(0)<=ci;
Ioop1:for i in 0 to 3 generate
F:fa port map
(a)(i),b(i),ca(i),a(i),ca(i+1);
End generate loop1;
Co<=ca(4);
end behavioural;
Half Adder
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity xor1 is
Port(p:in std_logic;
q:in std_logic;
r:out std_logic);
End xor1;
Architechture behavioural of xor1 is
Component and1 is
Port(a,b:in std_logic;c:out std_logic);
End component;
Component halfadder is
Port (a,b:in std_logic;
s,c:out std_logic);
End component;
Begin
U1:and1 port map(a,b,carry);
U2:xor1 portmap(a,b,sum);
End behaviural;
Full Adder
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity fa is
Port(a:in std_logic;
b:in std_logic;
c1:in std_logic;
S:out std_logic;
C:out std_logic);
End fa;
Architechture behavioural of fa is
Signals1,s2,s3:std_logic;
Component ha is
Port(a,b:in std_logic;
s,c:out std_logic) ;
End component;
Begin
X:ha port map(a,b,s1,s2);
y:ha port map(s1,c1,s,s3);
C<=s2 or s3;
End behavioural;
Mux
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity mux is
Port(a:in std_logic_vector(15 downto 0);
sel:in std_logic_vector(3 downto 0);
Op:out std_logic;
End mux;
Architechture behavioural of mux is
Begin
Process(a,sel)
Begin
Case(sel)is
When”0000”=>
op<=a(0);
When”0001”=>
op<=a(1);
When”0010”=>
op<=a(2);
When”0011”=>
op<=a(3);
When”0100”=>
op<=a(4);
When”0101”=>
op<=a(5);
When”1000”=>
op<=a(6);
143
When”0111”=>
op<=a(7);
When”1000”=>
op<=a(8);
When”1001”=>
op<=a(9);
When”1010”=>
op<=a(10);
When”1011”=>
op<=a(11);
When”1100”=>
op<=a(12);
When”1101”=>
op<=a(13);
When”1110”=>
op<=a(14);
When”1111”=>
op<=a(15);
when others=>
op<=‘Z’;
End case;
End process;
145
end behavioural;
JK Flipflop
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity jkff is
Port(j:in std_logic;
k:in std_logic;
clk:in std_logic;
q:out std_logic;
q1:out std_logic);
End jkff;
Architechture behavioural of jkff is
Begin
Prcess(j,k,clk)
Variable var:std_logic;
Begin
If(clk’event and clk=‘1’)then
If (j=‘0’ and k=‘1’)then
var:=‘0’;
elsIf (j=‘1’ and k=‘0’)then
Var:=‘1’;
elsIf (j=‘1’ and k=‘1’)then
Var:=not(var);
elsIf (j=‘0’ and k=‘0’)then
Var:=var;
Else null;
End if;
End if;
Q<=var;
Q1<=not (var);
End process;
End behavioural;
T Flip Flop
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity tff is
Port(t:in std_logic;
clk:in std_logic;
q:out std_logic;
q1:out std_logic);
End tff;
Architechture behavioural of tff is
Begin
Process(t,clk)
Variable a,b:std_logic;
Begin
If(clk’event and clk=‘1’)then
If(t=‘1’)then
Q<=t;
D flipflop
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity dff is
Port(d:in std_logic;
clk:in std_logic;
q:out std_logic);
End dff;
151
Architechture behavioural of dff is
Begin
Process(d,clk)
Variable var:std_logic;
Begin
If(clk’event and clk=‘1’)then
If(d=‘0’)then
var:=‘1’;
else
null;
end if;
end if;
Q<= var;
end process;
End behavioral;
152
Mod c
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity modc is
Port(r:in std_logic;
clk:in std_logic;
count:out std_logic_vector(2 downto 0);
End modc;
Architechture behavioural of modc is
Begin
Prcess(r,clk)
Variable var:std_logic_vector(2 down to 0);
Begin
If (clk’evbent and clk=‘1’)then
If (r=‘1’)then
Var:=“000”;
Else
Var:=var+1;
End if;
If(var:=“111”)then
Var:=“000”;
End if;
End if;
Count<=var;
End process;
End behavioural;
Rom
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity rom is
Generic(words:integer:=8;
Bits:integer:=8);
Port(adder:in integer range0 to(words-1)
data:out std_logic_vector((bits-1)
downto 0);
End rom;
Architechture behavioural of rom is
Type array1 is array(0 to (words-1))of
std_logic_vector((bite-1)down to 0);
Constant memory:array1:=(“00000001”;)
“00000011”;
“00000111;
“00001111”;
“00011111”;
“00111111”;
”01111111”;
“11111111”);
Begin
Process(addr)
Begin
Data<=memory(addr);
End process;
End behavioural;
Up Down counter
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity udcounter is
Port(r:in std_logic;
clk:in std_logic;
updown:in std_logic;
count:out std_logic_vector(3 downto 0);
End udcounter;
Architechture behavioural of udcounter is
Begin
Process(r,updown,clk)
Variable var:std_logic_vector(3 downto 0);
Begin
If(clk’event and clk=‘1’)then
If (r=‘1’)then
var:=“0000”;
elsIf (updown=‘1’)then
Var:=var+1;
Elsif(updown=‘0’)then
Var:=var-1;
Else
Null;
End if;
If(var=“1010”or var=“1111”)then
Var:=“0000”;
End if;
End if;
Count<=var;
End process;
End behavioural;
Twisted
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity twisted is
Port(r:in std_logic;
clk:in std_logic;
count:out std_logic_vector(3 downto
0));
End twisted;
Architechture behavioural of twisted is
Signal s:std_logic_vector(2 downto 0);
Begin
Process(clk)
Begin
If(clk’event and clk=‘1’)
If(r=‘1’)then
S<=“111”;
Else
S<=s+1;
End if;
End if;
Case s is
When”000”=>;count<=“0001”;
When”001”=>;count<=“0011”;
When”010”=>;count<=“0111”;
When”011”=>;count<=“1111”;
When”100”=>count<=“1110”;
When”101”=>;count<=“1100”;
When”110”=>;count<=“1000”;
When”111”=>;count<=“0000”;
When others=>null;
End case ;
End process;
End behavioural;
Ram
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity ram is
Generic(words:integer:16;
Bits:integer:=4);
Port(clk:in std_logic;
Wr_en:in std_logic;
detain:in std_logic_vector(bits-1) downto 0);
Addr:in integer range 0 to (words-1);
Dataout:out std_logic_vector(bits-1)downto 0));
End ram;
Architechture behavioural of ram is
Type array1 is array(0 to (words-1)of
Std_logic_vector(bits-1)downto 0);
Signal memory:array1;
Begin
Process(clk,wr_en,datain,addr)
Begin
If(clk’event and clk=‘1’)then
If(wr_en=‘1’)then
Memory(addr<=datain);
Else
Dataout<=memory(addr);
End if;
Else
Null;
End if;
End process;
End behavioural;
Srla
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity srla is
Port(s:in std_logic;
r:in std_logic;
clk:in std_logic;
q:out std_logic;
q1:out std_logic);
End srla;
Architechture behavioural of srla is
Signal var:std_logic:
Begin
If(clk’event and clk=‘1’)then
If(s=‘0’ and r=‘1’)then
Var<=‘0’;
Elsif(s=‘1’ and r=‘0’)then
Var<=‘1’;
Elsif(s=‘1’ and r=‘1’)then
Var<=‘Z’;
Elsif(s=‘0’ and r=‘0’)then
Var<=var;
End if;
End if;
Q<=var;
Q1<=not var;
End process;
End behavioral;
Srla nand
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity srla_nandgate is
Port(s:in std_logic;
r:in std_logic;
clk:in std_logic;
q:out std_logic;
q1:out std_logic);
End srla_nandgate;
Architechture behavioural of
srla_nandgate is
Signal a,b,c,d:std_logic;
Component nand1 is
port(a,b:in std_logic;
C:out std_logic);
End component;
Begin
E;nand1 port map(s,clk,a);
F:nand1 port map(r,clk,c);
G:nand1 port map(a,d,b);
H:nand1 pot map(c,b,d);
Q<=b;
Q1<=d;
End behavioural;
SiSo
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity siso is
Port(a:in std_logic;
clk:in std_logic;
b:out std_logic);
End siso;
Architechture behavioural of siso is
Signal s:std_logic_vector(3 downto 0):
Begin
Process(a,clk)
begin
If(clk’event and clk=‘1’)then
S(3)<=s(2);
S(2)<=s(1);
S(1)<=s(0);
S(0)<=a;
Else
null;
End if;
B<=s(3);
End process;
End behavioral;
parity
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity parity is
Port(a:in std_logic_vector(2 downto 0);
pg:out std_logic;
pc:out std_logic);
End parity;
Architechture behavioural of parity is
Signal s1:std_logic_vector;
Begin
With a select
S1<=‘1’when “000”;
‘0’when “001”;
‘0’when “010”;
‘1’when “011”;
‘0’when “100”;
‘1’when “101”;
‘1’when “110”;
‘0’when “111”;
‘0’when others;
Pc<=(not s1);
Pg<=s1;
Queue
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity queue is
numeric(bits: integer:=4;
words:integer:=8);
Port(clk:in std_logic;
r_w: in std_logic;
datain: in std_logic_vector(bits-1) downto 0);
dataout: out std_logic_vector(bits-1)downto 0);
pc:out std_logic);
Empty : out std_logic;
Full: out std_logic);
End queue;
Architectural behavioral of queue is
Type stack1 is array(0 to (words)) of
Std_logic_vector((bits-1)downto 0);
Signal s1,s2: integer range 0 to (words);
Signal memory: stack1;
Begin
Process(clk,r_w:datain)
Begin
If(clk’event and clk =‘1’)then
If(r_w=‘0’)then
If(s1=8)then
Full<=‘1’;
Else
S1<=s1+1;
Memory(s1)<=datain;
Empty<=‘0’;
Full<=‘0’;
End if;
Else
If(s1=0 or s2 =8) then
Empty<=‘1’;
Else
Empty<=‘0’;
S2<=s2+1;
Dataout<=memory(s2);
End if;
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End if;
Else
Null;
End if;
End process;
End behavioral;
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Q1<=not(t);
Else null;
End if;
End if;
End process;
End behavioural;
Stack
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_airth.all;
Use ieee.std_logic_unsigned.all;
entity stack is
numeric(bits: integer:=4;
words:integer:=8);
Port(clk:in std_logic;
r_w: in std_logic;
datain: in std_logic_vector(bits-1) downto 0);
dataout: out std_logic_vector(bits-1)downto 0);
pc:out std_logic);
Empty : out std_logic;
Full: out std_logic);
End stack; 184
Architectural behavioral of queue is
Type stack1 is array(0 to (words)) of
Std_logic_vector((bits-1)downto 0);
Signal s: integer range 0 to (words);
Signal memory: stack1;
Begin
Process(clk,r_w:datain)
Begin
If(clk’event and clk =‘1’)then
If(r_w=‘0’)then
If(s1=8)then
Full<=‘1’;
Else
S<=s+1;
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Memory(s)<=datain;
Empty<=‘0’;
Full<=‘0’;
End if;
Else
If(s=0) then
Empty<=‘1’;
Else
full<=‘0’;
Empty<=‘0’;
Dataout<=memory(s);
S<=s-1;
End if;
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End if;
Else
Null;
End if;
End process;
End behavioral;
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