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HDL For Embedded

System

Mukesh Maheshwari
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VHDL

INTRODUCTION

ELEMENTS OF VHDL

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Introduction

WHAT IS VHDL ?

FEATURES OF VHDL

HISTORY OF VHDL

LEVELS OF ABSTRACTION 3
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What is VHDL?

DIGITAL SYSTEM DESIGN USING


HDL’S IS AN ESTABLISHED
METHODOLOGY IN EDA.

VHDL stands for


Very High Speed Integrated Circuits
Hardware Description Language.
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Features of VHDL
VHDL is the amalgamation of following languages:
 Concurrent Language
 Sequential Language
 Timing Specification
 Simulation Language
 Test Language
Powerful Language Constructs
 Ex: if---else, with---select, etc.
Design Hierarchies to create Modular designs
Supports Design Libraries
Facilitates device independent design and
Portability
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Concurrent Language

Concurrent Statements execute at


the same time in parallel,
parallel as in
Hardware.

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Sequential Language

Sequential Statements execute one at


a time in sequence.
As the case with any conventional
language
Sequence of statements is important.

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Timing Specification 8

Example:
process
begin
clk <= ‘0’;
wait for 20ns;
clk <= ‘1’;
wait for 12ns;
end process;

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Test Language 9

Test bench
 Is part of a VHDL model that generates a set of test
vectors and sends them to the Module being tested.
 Collects the responses made by the Module Under Test
and compares them against a specification of correct
results.

Need
 To ensure that design is correct.
 Model is operating as required.

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Design Hierarchy

Hierarchy can be represented using VHDL.


Consider example of a Full-adder which is the top-
level module, being composed of three lower level
modules I.e. Half-Adder and OR gate.

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Design libraries 11

Design Unit
 Is any block of VHDL code or collection of VHDL
codes that may be independently analysed and
inserted into a design library.
Design Library:
 Is a storage facility in which analysed VHDL
descriptions are stored.

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History of VHDL

In 1981 the Institute for Defense Analysis (IDA) had arranged


a workshop to study
 Various Hardware Description methods
 Need for a standard language
 Features required by such a standard.

A team of three companies, IBM, Texas Instruments, and


Intermetrics were awarded contract by DoD to develop a
language.

Version 7.2 of VHDL was released along with Language


Reference Manual (LRM) in 1985.

Standardized by IEEE in 1987 known as the IEEE Std 1076-


1987. 12
Logic Systems 13

Need for a multi-valued Logic System


 Conventional Logic systems had only three values
I.e. ‘0’ , ‘1’ and ‘Z’
 Consider truth table for AND gate
 A B Y
 0 0 0
 0 1 0
 1 0 0
 1 1 1
For
 0 Z ???
A 9-value package STD_LOGIC_1164 was developed
and accepted as IEEE Std 1164-1993.

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Logic Systems 14

Need for a standard Logic System

Different vendors used different logic systems.

 Sharing of codes developed on different toolsets was


difficult.

Multivalued logic

 Unknown : Value was known, but is not any


more.
 Un-initialized : Value was never known in the first
place !
 High impedance : Net has no driver.
 Drive strengths : Handle different output drivers.
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 Don’t care : Optimizes synthesis implementation.
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Multi-
Multi-Valued Logic

A 9-value package STD_LOGIC_1164


was developed and accepted as IEEE
Std 1164-1993.
‘U’ : Uninitialized
‘X’ : Unknown
‘0’ : Logic 0
‘1’ : Logic 1
‘Z’ : High impedance
‘W’ : weak unknown
‘L’ : weak logic 0
‘H’ : weak logic 1
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‘-’ : Don’t care
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ELEMENTS OF VHDL – Agenda

BASIC BUILDING BLOCKS


ENTITY
ARCHITECTURE
LANGUAGE ELEMENTS
CONCURRENT STATEMENTS
SEQUENTIAL STATEMENTS
SIGNALS & VARIABLES
CONFIGURATION
PACKAGE

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Basic Building Blocks

Entity
 A design’s interface to the external circuitry.

Architecture
 Describes a design’s behavior and functionality.

Configuration
 Binds an entity to an architecture when there are multiple
architectures for a single entity.
Package
 Contains frequently used declarations, constants,
functions, procedures, user data types and components.

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Basic Building Blocks

Library
 Is a collection of compiled VHDL units
 Promotes sharing of compiled designs and hides the
source code from the users
 Commonly used functions, procedure and user data types
can be compiled into a user-defined library for use in all
designs
 Library should be declared before EACH entity declaration
even if it is in the same VHDL file.

Syntax library IEEE;


use IEEE.std_logic_1164.all
use IEEE.std_logic_unsigned.all

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Entity

Equivalent to pin configuration of an IC.


Syntax:
 entity entity_name is
port (port_list) ;
end entity_name;

Example :
entity and_gate is
port ( 1A, 2A, 3A, 4A : in std_logic;
1B, 2B, 3B, 4B : in std_logic;
1Y, 2Y, 3Y, 4Y : out std_logic
);
end and_gate ;

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Entity 20

VHDL design description must include,


 ONLY ONE ENTITY

Entity Declaration
 Defines the input and output ports of the design.
 Each port in the port list must be given,
• a name
• data flow direction
• a type.

Can be used as a component in other entities after being


compiled into a library.

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Entity 21

Proper documentation of the ports in an entity


is very important.
A specified port should have a self explanatory
name that provides information about its
function.
Ports should be well documented with
comments at the end of the line providing
additional information about the signal.
Consider example of an ALU.

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Modes

Signal in the port has a Mode which


indicates the driver direction.
Mode also indicates whether or not the
port can be read from within the
entity.
Four types of Modes are used in
VHDL.
 Mode IN
 Mode OUT
 Mode INOUT
 Mode BUFFER 22
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Mode IN

Value can be read but not


assigned.
Entity
Port Signal
Example:

entity driver is
port ( A : in std_logic;
B : out std_logic;
Data : inout std_logic;
Count : buffer std_logic Drivers reside
); outside the entity
end driver ;

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Mode OUT

Value can be assigned but not


read. Entit Port Signal
y
Example:

entity driver is
port ( A : in std_logic;
B : out std_logic;
Data : inout std_logic;
Count : buffer std_logic )
; Drivers reside
inside the entity
end driver ;

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Mode INOUT

Bi-directional
Entit
Value can be read and assigned
y
Port
Example: signal
entity driver is
port ( A : in std_logic;
Data
B : out std_logic;
Data : inout std_logic;
Count : buffer std_logic )
; Signal can
end driver ; be read
inside the
Drivers may reside both entity
inside and outside the entity
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Mode BUFFER

Entity
Output port with Internal read
capability

Example:
Count
Driver reside
entity driver is Inside the entity
port ( A : in std_logic;
B : out std_logic;
Data : inout std_logic;
Count : buffer std_logic ) Signal inside can be
; read inside the entity
end driver ;

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Architecture 27

Specifies,
 Behavior
 Function
 Relationship between inputs and outputs of an
entity.

 Syntax:
architecture architecture_name of entity_name is
declarations
begin
concurrent_statements
end [ architecture_name ];
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Architecture 28

Equivalent to truth table.


Example:
A B C
L L L
L H L
H L L
H H H

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Architecture

Can contain only Concurrent Statements.

A design can be described in an Architecture using


various Levels of Abstraction.
 To facilitate faster design
 Better understanding
 Lesser complexity.

There can be no architecture without an Entity.

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VHDL Design Styles or Hardware Design
Modeling
VHDL Design
Styles

dataflow structural behavioral

Concurrent Components and Sequential statements


statements interconnects
• Registers & counters

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Architecture Bodies

Behavioral

 Also known as High-level


Descriptions.

 Consists of a set of
assignment statements to
represent behavior.

 No need to focus on the


gate-level implementation
of a design.

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Architecture Bodies

Dataflow

Use concurrent
signal
assignment
statements.

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Architecture Bodies

Structural

 Components from
libraries are connected
together.

 Designs are hierarchical.

 Each component can be


individually simulated.

 Consists of VHDL
netlists.
It is possible to mix the three Modeling styles in a single
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architecture body.
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Comparing Architectural Bodies

A structural design methodology is used to

 Split a design into manageable units.

 Silicon vendors provide libraries which can be used to


instantiate components that represent device-specific
resources and optimized structures.
 eg. LogiBLOX in Xilinx Tool.

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Language Elements

VHDL is a strongly TYPED Language.

VHDL is not case sensitive.


sensitive

VHDL supports a variety of data types and operators.

 OBJECTS

 OPERATORS

 AGGREGATES

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OBJECTS 36

Objects are used to represent & store the data in the system
being described in VHDL.
Object contains a value of a specific type. For ex:
object
results in an object
SIGNAL COUNT : INTEGER called count which holds
integer value
class Data type

The name given to object (also port ) is called as identifier.


 RESERVED WORDS cannot be used as identifies
Each object has a type & class.
 Class indicates how the object is used in the model & what
can be done with the object.
 Type indicates what type of data the object contains.
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OBJECTS

Each object belong to one of the following


CLASS
CONSTANT SIGNAL
VARIABLE

The set of values that each object can hold is


specified by DATA TYPES
SCALAR ACCESS FILE
COMPOSITE
Integer Array
Real
Enumerated
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Physical
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Data Objects

CONSTANTS :These
: are identifiers with fixed value.

The value is assigned only once, when declared.

Value cannot be changed during simulation.

Example:
constant Bus_Width : Integer := 16;
constant CLK_Period : Time := 15 ns;

Constants makes the design description more


readable.
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Design changes at later time becomes easy.


SIGNALS 39

Represents wires within a circuit.


architecture and_gt of anding is
signal temp : std_logic;
begin
U1 : AND2 portmap
(a,b,temp);
U2 : AND2 portmap
(temp,a,b;
end and_gt;
Thus Signals can used
>
 To connect design entities together & communicate changes
in values within a design.
 Instead of inout signals.
Each signal has a history of values i.e holds a list of values
which include current value of signal & set of possible future
values that are to appear on the signal.
Computed value is assigned to signal after specified delay called
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‘ delta delay ‘.
VARIABLES 40

These are objects with single current value.


Are used to store the intermediate values between the
sequential VHDL statements.
Variable assignment occurs immediately.
Variable can be declared & used inside the process
statement only. But retain their value throughout the entire
simulation.

process ( a )
Note : a_int contains the total
variable a_int : integer := number of events that occurred
1;
on signal a
begin
a_int := a_int + 1;
end process;
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Scalar Data Types

ENUMERATION TYPES :
This declaration defines a set of user-defined values
consisting of identifiers & character literals.

Ex : type micro_op is ( load, store, add, sub, mul, div )

 As shown micro_op is enumerated types & supports the


values load, store, add & sub.

 Values of enumeration type has position number


associated with them. Compiler encodes these
enumeration literals in ascending order.

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Scalar data types 42

PREDEFINED ENUMERATION TYPES

Bit – Supports the values ‘0’ & ‘1’.


Boolean – Supports literals FALSE & TRUE is defined as
Ex : variable error_flag : boolean := true.
Std_logic_type – Data type defined in the std_logic_1164 package of
IEEE library. It is defined as
type std_logic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’);
‘U’ : Uninitialized
‘X’ : Unknown U, X W, - represent behavior of
‘0’ : Logic 0 model itself rather than the
‘1’ : Logic 1 behavior of hardware being
‘Z’ : High impedance synthesized.
‘W’ : Unknown
‘L’ : Low logic 0
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‘H’ : Low logic 1 ‘-’ : Don’t care
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SCALAR DATA TYPES

Data type Meaning Example

Integer Has set of values type index is range 0 to 15


that follow within signal count : integer range o
specific range to 8
Real Has a set of values type real_data is range 0.0 to
in given range of 35.5
real numbers.
Physical Used to represent Constant set_up : time := 2 ns.
physical quantities
such as current,
time distance

OBJECTS OF PHYSICAL TYPE ARE NOT


SYNTHESISABLE ?? 43
COMPOSITE DATA TYPES 44

Represents collection of values.


Ex ARRAY: - Consists of the elements that have same type.
 Vector ( special case of single dimensional array )
Ex signal A : std_logic_vector (7 downto 0);
 Two dimensional array (typical application is a memory device)

Ex : type memory 1K4 is array ( 0 to 1023 ) of std_logic_vector ( 3


downto 0);
signal memory : memory 1K4

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Data Operators 45

Logical Operators Lowest priority (except “not”)


??

Relational Operators

Shift Operators

Adding Operators

Multiplying Operators

Miscellaneous Operators Highest priority

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Logical Operators

AND OR NAND NOR XOR XNOR NOT


Are defined for
 Types BIT and BOOLEAN.
 One dimensional arrays of BIT and BOOLEAN.

Incorrect Examples:
port ( a, b : bit_vector (3 downto 0);
e : bit_vector (1 downto 0);
h, i, j, k : bit;
l, m, n : boolean );

h <= i and j or k; -- parenthesis required;


a <= b nand e; -- operands must be of the same
size;
h <= i or l; -- operands must be of the same 46
type;
Relational ( Conditional ) Operators 47

 Are used to check conditions.


= /= < > <= >=

“<“, “<=“, “>”, and “>=“ are


predefined for
 For integer types
 Enumerated types
 One-dimensional arrays of enumeration
and integer types. 47
Relational Operators 48

No numerical meaning is associated with a BIT


vector
Elements of a vector are just a collection of objects
of the same type.

For array types operands are aligned to the left and


compared to the right.

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Shift Operators – VHDL 93

sll srl sla sra ror rol

 sll Shift left logical


 srl Shift right logical
 sla Shift left arithmetic
 sra Shift right arithmetic
 rol Rotate left logical
 ror Rotate right logical
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Shift Operators 50

Each operator
 Takes an array of BIT or BOOLEAN as the left operand
 Integer value as the right operand

Ex: ‘A’ is a bit_vector equal to “10010101”


A sll 2 is “01010100” (shift left logical, filled with ‘0’)
A srl 3 is “00010010” (shift right logical, filled with ‘0’)
A sla 3 is “10101111” (shift left arithmetic, filled with right
bit )
A sra 2 is “11100101” (shift right arithmetic, filled with
left
bit )
A rol 3 is “10101100” (rotate left)
A ror 2 is “01100101” (rotate right)
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Adding Operators

+ - &
Addition subtraction
concatenation
 Concatenation Operator (&)
 Operands can be one-dimensional array type or element
type
 “&” Operator works on vectors only.

Example:
signal a: std_logic_vector ( 5 downto 0 );
signal b,c,d: std_logic_vector ( 2 downto 0 );
begin
b <= ‘0’ & c(1) & d(2);
a <= c & d;
end; 51
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Adding Operators

Do not use Concatenation operator on


the left of the assignment symbol.

architecture bad of ex is
signal a : std_logic_vector ( 2 downto 0 );
signal b : std_logic_vector ( 3 downto 0 );
begin
‘0’ & a <= b; -- Error!
end bad;
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Multiplying Operators 53

* / mod rem

( * ) and ( / ) are predefined for: Integers Floating point


numbers

mod ( modulus ) and rem ( remainder ) are predefined for


Integers
Example:only.
variable A,B : Integer;
Variable C : Real;
C <= 12.34 * ( 234.4 / 43.89
);
A <= B mod 2;
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Miscellaneous Operators

Abs **

The abs operator has only one operand. It allows defining the
operand’s absolute value. The result is of the same type as
the operand.

** ( Exponential Operator ) is defined for any integer or


floating point number
Examples :
2 ** 8 = 256
3.8 ** 3 =
54.872
abs (-1) = 1 54
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Aggregates

Aggregates:
 Assigns values to the elements of an array.
 Example :
a <= ( others => ‘0’; ) identical to a <= “00000”

 We can assign values to some bits in a vector and use


“others” clause to assign the remaining bits.

Example:

a <= ( 1=>’1’, 3=>’1’, others =>’0’ );


signal data_bus : std_logic_vector ( 15 downto 0 );
data_bus <= ( 14 downto 8 => '0', others => '1‘ );

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Aggregates 56

Elements in a vector can also be assigned values of other


signals.
Example : “a” has a length of 5 bits.

a <= (1=> c(2), 3=> c(1), others => d(0);


identical to
a <= c(2) & d(0) & c(1) & d(0) & d(0) ; ------(
Disadvantage ? )

“others” choice can be only the last choice in an aggregate.

Each element of the value defined by an aggregate must be


represented ONCE AND ONLY ONCE in the aggregate.
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Concurrent Statements

MEANING IN HARDWARE TERMS


CONCURRENT CONSTRUCTS
WHEN_ELSE STATEMENT
WITH_SELECT STATEMENT
SEQUIENTIAL CONSTRUCTS
- if - else STATEMENT
- case STATEMENT
COMPONENT INSTANTIATION
USE OF GENERATE STATEMENT
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Concurrent Statements

Consider
X = X+Y;

In software:
 X and Y are register
locations
 The contents of X
and Y are added and
the result is stored
in X.

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Concurrent Statements

In concurrent
statements, there
are no implied
registers.

Feedback is
described around
Combinational
logic.
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Drivers

Are created by signal assignment statements

Concurrent signal assignment produces one driver


for each signal assignment

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Drivers

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Selected Signal Assignment – ‘when’ statement

Z <= A when
ASSIGN_A = '1'
else
B when
ASSIGN_B = '1'
else
C; 62
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Selected Signal Assignment – ‘when’ statement

 Modeling Tri-state buffer


architecture tri_ex_a of tri_ex is
begin
out1 <= in1 when control =
'1' else
'Z';
end tri_ex_a;

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Selected Signal Assignment – ‘with’ statement

Syntax with choice_expression select


target <= expression 1 when choice 1
expression 2 when choice 2
expression N when choice N ;

‘with...select’ statement evaluates


choice_expression and compares that value to each
choice value.
In ‘when’ statement the matching choice value has
its expression assigned to target.
Each value in the range of the choice_expression
type must be covered by one choice.

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Selected Signal Assignment – ‘with’ statement

signal A, B, C, D, Z: std_logic;
signal CONTROL: std_logic_vector
(1 downto 0);
with CONTROL select
Z <= A when "00",
B when "01",
C when "10",
D when "11";
‘0’ when others;Why

when others” clause?

No two choices can overlap.


All possible choices must be enumerated.
Each choice can be either a static expression (such as 3) or a
static range (such as 1 to 3).
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If Statement

Syntax: if condition1 then


{ sequential_statement }
elsif condition2 then
{ sequential_statement }
else
{ sequential_statement }
end if;

“If “ Statement evaluates each


condition in order.
Statements can be nested.
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if Statement

Avoid using more than three levels Of If…else statements .

When defining the condition, use parentheses to differentiate


levels of operations on the condition.
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If statement

process (sel, a, b, c, d)
begin
If sel(2) = ‘1’ then
y <= a;
elsif sel(1) = ‘1’ then
y <= b;
elsif sel(0) = ‘1’ then
y <= c;
else
y <= d; • Generates a priority structure.
end if;
• Corresponds to “when-else”
end process;
command in the concurrent part.
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Case Statement

Syntax: case expression is


when choice1 =>{ statements }
when choice2 =>{ statements }
when others=>{ statements }
end case;

“Case “ Statement isIs a series of


parallel checks to check a
condition.
It selects, for execution one of a
number of alternative sequences of 69

statements.
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Case statement

process (sel,a,b,c,d)
begin
case sel is
when 0=> y <=a;
when 1=> y <=b;
when 2=> y <=c;
when others =>

y<=d;
end case;
end process;

Does not result in prioritized logic structure unlike the if


statement.
Corresponds to “with….select” in concurrent statements.

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Case statement 71

Every possible value of the case expression must be covered in


one and only one when clause.
Each choice can be either a static expression ( such as 3 ) or a
static range ( such as 1 to 3 ). we cannot have a “when”
condition 71
that changes when it is being evaluated.
Null Statement 72

Does not perform any action


Can be used to indicate that when
some conditions are met no action is
to be performed
Example:
case a is
when “00” => q1 <= ‘1’;
when “01” => q2 <= ‘1’;
when “10” => q3 <= ‘1’;
when others <= null; ----------------------
Why? 72

end case;
Process Statement – characteristics

Are executed one after another, in the order in which they are
written.
 Can appear only in a Process or Subprogram.
 Only sequential statements can use Variables.
 “Process” is the primary concurrent VHDL statement used to
describe sequential behavior.
Statements in a process, are executed sequentially in zero
time.

All processes in an architecture behave concurrently.

NOTE : SEQUENTIAL STATEMENTS DO NOT GENERATE


SEQUENTIAL HARDWARE
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Process Statement

Process places
only one driver on
a signal.

Value that the


signal is updated
with is the last
value assigned to
it within the
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process
execution.
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Rules About Process

A process with a sensitivity clause must not contain an


explicit wait statement.

Only static signal names for which reading is permitted may


appear in the sensitivity list of a process statement.

The execution of a process statement consists of the


repetitive execution of its sequence of statements.

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Sensitivity List

Simulator runs a process


when any one of the signals
in the sensitivity list
changes.

Process should either have a


“sensitivity list” or a “wait”
statement at the end.

Only static signal names are


allowed in the sensitivity list.

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Process statement

Two types of processes:


Combinatorial
Clocked

Combinatorial Process
Generates combinational logic
All inputs must be present in the sensitivity
list.
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Process Statement

Clocked Process:
 Generates synchronous logic.
process (clk)
begin
if (clk’ event and clk =‘1’ )
then
Q < = D;
end if;
end process;

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Process Statement 79

Clocked processes having an “else”


clause will generate wrong
hardware.
process(clk)
begin
if (clk'event and clk = '1')
then
out1 <= a and b;
else
out1 <= c;
end if;
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end process;
Loop statements

Loop statements are used to iterate through a set of sequential


statements.
While loop

Syntax: loop_label: while condition loop


sequence_of_statements
end loop loop_label

Has a Boolean Iteration Scheme.


Condition is evaluated before execution.

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Loop statements 81

Loop statements are used to iterate through a set of


sequential statements.

While loop Syntax: loop_label: while condition loop


sequence_of_statements
end loop loop_label

process ( Input )
Has a Boolean Iteration variable i : POSITIVE := 1;
Scheme. begin
Condition is evaluated L1: while i <= 8 loop
before execution. Output (i) <= Input (i+8)
;
i := i + 1;
end loop L1;
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end process;
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Loop Statements - For LOOP

Syntax: loop_label: for loop_parameter in range loop


Sequence_of_statements
end loop loop_label;

Has an Integer Iteration Scheme. Number of repetitions is


determined by an Integer range
The loop is executed once for each value in the range
The loop parameter’s range is tested at the beginning of the loop, not
at the end.

Example : factorial := 1;
for number in 2 to N loop
factorial := factorial * number;
end loop;
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Loop Statements – For LOOP 83

“For loop rules”


 Loop parameter is implicitly defined.
 Inside the loop, the loop parameter is a
constant. Thus, it may be used but not
altered.
 Discrete range of the loop is evaluated
before the loop is first executed.
 Loop counter only exists within the loop.
 Labels in loop parameters enable better
loop control with the “next” and “exit”
statements. 83

 Labels also enhance readability and


Loop statements – Next Statement 84

Syntax:
next;
next loop_label when condition;

Skips the remaining statements in the current iteration of the


specified loop.

Execution resumes with the first statement in the next


iteration of the loop.

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Loop statements – Next Statement

Example:
 for J in 10 downto 5 loop
if sum < total_sum then
sum := sum + 2;
elsif sum = total_sum then
next;
else
null;
end if;
k : k+1;
end loop;

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Loop statements – exit Statement 86

Exit Statement
Syntax:

exit;
exit loop_label when condition;

Entirely terminates the execution of the loop in which it is located.

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Loop statements – exit Statement

Example:
sum := 1; j := 0;
L3 : loop
J := J + 21;
sum := sum * 10;
if sum > 100 then
exit L3;
end if;
end loop L3;
Note:
 Exit : Causes the specified loop to be terminated.
 Next :Causes the current loop iteration of the specified
loop to be prematurely terminated; execution resumes with
the next iteration.

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Component Instantiation

Syntax:

instance_name : component_name
port map (
[ port_name => ] expression
[port_name => ] expression);

instance_name names this instance of the component type


component_name - WHY?
port map connects each port of this instance of
component_name to a signal-valued expression in the current
entity.

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Component Instantiation 89

entity ND4 IS
port ( IN1,IN2,IN3,IN4 : in BIT;
Z : out BIT);
end ND4;
architecture gate_arch of ND4 is
component ND2
port ( A, B: in BIT;
C : out BIT);
end component;
signal TEMP_1,TEMP_2 : BIT;
begin
U1: ND2 port map ( A =>IN1, B =>IN2, C=>TEMP_1 );
U2: ND2 port map ( A =>IN3, B =>IN4, C=>TEMP_2 );
U3: ND2 port map ( A =>TEMP_1, B =>TEMP_2, C=>Z );

89
Component Instantiation 90

Ports can be mapped to signals by ‘Positional’ or ‘mixed’


notation.

U1: ND2 port map ( IN1,IN2, TEMP_1 ); --


positional
U1: ND2 port map (IN1,IN2, C => TEMP1); --
Mixed

Named association is preferred because it makes the code


more readable and pins can be specified in any order.

All positional connections should be placed before any named


connections.

90
Generate Statement 91

Concurrent statements can be conditionally selected or


replicated using “generate” statement.

Used to create multiple copies of components, processes, or


blocks.
For ex: Provides a compact description of regular
structures such as memories, registers, and counters.

No simulation semantics are associated.

91
Generate Statement 92

Two forms of “generate” statement


 for…generate
 Number of copies is determined by a discrete range
 if…generate
 Zero or one copy is made, conditionally

Note: Range must be a computable integer, in either of these


forms:
 integer_expression to integer_expression
 integer_expression downto integer_expression
 Each integer_expression evaluates to an integer.

92
Generate Statement 93

Example:

93
94
Generate Statement

Example:

94
95
Generate Statement

Example:
Example:

95
96
Generate Statement

Example:

96
GENERIC
 It provides a powerful mechanism in VHDL to model
parameterized designs.

 Syntex:-
entity entity_name is
generic (
const. name: const. type;
………..
………….;
port (
signal_name : mode signal_type;
……………………
……………………);
End entity_name;

97
EXAMPLE OF GENERIC STATEMENT WITH GENERATE
STATEMENT
Library ieee;
Use ieee.std-logic_1164;

Entity inv1 is
Generic ( two : positive := 5 );
port ( I :in bit_vector (two downto 0);
o :out vector (two downto 0));
end inv1;

Architecture bus_inv1 of inv1 is


component inv is
port b ( I : in bit;
o :out bit);
End component;
begin
x : for I in 0 to two generate
u : inv port map (I (i),o(i));
End generate;
End bus_inv1;

98
99
Wait Statement

Wait statement
 Suspends the execution of a process or
procedure until some conditions are
met.

Three basic forms:


 wait on sensitivity clause
 wait until condition clause
 wait for timeout clause

99
100
Wait Statement

“Wait” statement at the end of the process is equivalent to the


“sensitivity list” at the beginning of the process. -----Why?

Example:

process -- No Sensitivity list


begin
if ( clk'event and clk = '1')
then
q <= d;
end if;
wait on clk; -- Replaces the Sensitivity list
end process;

100
101
Wait Statement

Illegal coding
 Processes with a “wait” Statement
and “Sensitivity list” are illegal.
Example:
process ( clk )
begin
wait until clk = ‘1’;
q <= d;
end process;

101
102
Hardware Modeling Examples

Synchronous Reset : Flip-flops are reset on the


active edge of the clock when reset is held active.
process (CLK)
begin
if ( CLK’ event and CLK =
‘1’) then
if ( RST = ‘1’ ) then
Q <= ‘0’;
else
Q <= D;
end if;
end if;
end process; 102
103
Hardware Modeling Examples

Asynchronous Reset : Flip-flops are cleared as


soon as reset is asserted.

process (CLK, RST)


begin
if ( RST = ‘1’ ) then
Q <= ‘0’;
elsif ( CLK’event and CLK =
‘1’)
then
Q <= D;
end if;
end process;
103
Hardware Modeling Examples 104

Any assignment within clock statement will


– generate a Flip-flop and
– all other combinational circuitry will be created at the ‘D’
input of the Flip-flop.

process (clk)
begin
if (clk'event and clk = '1')
then
out1 <= a and b;
end if;
end process;
104
Hardware modeling Examples-
Examples- Latch 105

Incompletely specified Conditional expression


infers a latch.
Latch is a combinational circuit which necessarily
has feedback to hold the output to previous value
for the unspecified states/conditions.
Avoid the inference of latches in synchronous
designs. As latches infer feedback and they cause
difficulties in timing analysis and test insertion
applications. Most synthesizers provide warnings
when latches are inferred.

105
Hardware modeling Examples – Latch 106

Completely specified
Conditional expression.
incompletely specified
process (en,a)
Conditional expression. begin
if en='1‘ then
process (en,a) out1 <= a;
begin else
if en='1' then out1 <='1';
out1<= a; end if;
end if; end process;
end process;

106
Configuration 107

Need:

107
Configuration 108

Configuration declaration is used to select one of the many


architectures that an entity may have.

Syntax:

configuration configuration_name of entity_name is


for architecture_name
for instantiation:component_name
use library_name.entity_name(architecture_name);
end for;
end for;
end configuration_name;

108
PACKAGE
 A file containing definations of objects.
 Objects can be used in other programs.
 All objects are global.

 Syntex :-
:-
package package_name is
type declarations
signal/constant declarations
function/procedure declaration
end package_name;

package body package_name is


type declarations
signal/constant declarations
function/procedure definations
end package_name;
109
Use of package :-

use work.package_name.all
all;

110
Subprograms

 Include :
functions and procedures
 Commonly used pieces of code
 Can be placed in a library, and then reused and
shared among various projects
 Abstract operations that are repeatedly performed
 Type conversions
 Use only sequential statements, the same as
processes

111
Typical Locations of Subprograms

PACKAGE LIBRARY
PACKAGE BODY
global

FUNCTION / ENTITY
PROCEDURE local for all architectures
of a given entity

ARCHITECTURE
Declarative part
local for a given architecture
112
Functions

113
Functions – basic features
Functions
Always return a single value as a result

Are called using formal and actual parameters the


same way as components
Never modify parameters passed to them
Parameters can only be constants (including
generics) and signals (including ports);
variables are not allowed; the default is a
CONSTANT
when passing parameters, no range specification
should be included (for example no RANGE for
INTEGERS, or TO/DOWNTO for
STD_LOGIC_VECTOR)

are always used in some expression, and not called114


on their own
FUNCTION/PROCEDURE

 FUNCTION
 It always return a value.
 It is used to generalised a perticular program for the use of other
program.
 Syntax:-

function function_name (
signal names :signal tupe;
………………..
)return
return return_type is

type declarations
const. / variable declarations
…………………
…………………….
begin
sequential statements
115
end function_name;
Type conversion function (1)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------------
---------------------------------------
------------------
PACKAGE my_package IS
FUNCTION conv_integer (SIGNAL vector:
STD_LOGIC_VECTOR)
RETURN INTEGER;
END my_package;
----------------------------------------
---------------------------------------
116
------------------
Type conversion function (2)
PACKAGE BODY my_package IS
FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR)
RETURN INTEGER;
VARIABLE result: INTEGER RANGE 0 TO 2**vector’LENGTH -
1;
VARIABLE carry: STD_LOGIC;
BEGIN
IF(vector(vector’HIGH)=‘1’ THEN result:=1;
ELSE result := 0;
FOR i IN (vector’HIGH-1) DOWNTO (vector’LOW) LOOP
result := result*2;
IF (vector(i) = ‘1’ THEN result := result+1;
END IF;
RETURN result;
END conv_integer;
END my_package;
117
Type conversion function (3)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_package.all;
------------------------------------------------
----------------------------------------------
---
ENTITY conv_int2 IS
PORT ( a: IN STD_LOGIC_VECTOR (0 TO 3);
y: OUT INTEGER RANGE 0 TO 15);
END conv_int2;
------------------------------------------------
----------------------------------------------
---
ARCHITECTURE my_arch OF conv_int2 IS
BEGIN 118
y <= conv_integer(a);
END my_arch;
Procedures

119
Procedures – basic features
Procedures
 do not return a value

 are called using formal and actual parameters the same way as
components
 may modify parameters passed to them
 each parameter must have a mode: IN, OUT, INOUT
 parameters can be constants (including generics), signals
(including ports), and variables;
the default for inputs (mode in) is a constant, the default for
outputs (modes out and inout) is a variable
 when passing parameters, range specification should be included
(for example RANGE for INTEGERS, and TO/DOWNTO for
STD_LOGIC_VECTOR)

 Procedure calls are statements on their own

120
PROCEDURE :-

It is alternate to function .
it doesnot return any value.
Syntex is also same as with function except return type;

121
EXAMAPLE OF FUNCTION
Use library ieee;
use ieee.std_logic_1164.all;
use ieee.std-logic_unsigned.all;
package fun is
function sum1 ( x,y :in std-lofic_vector (1 downto 0))
return std_logic_vector;
end fun;
package body fun is
function sum1 ( x,y :in std-lofic_vector (1 downto 0))
return std_logic_vector is

variable temp : std_logic_vector(2 downto 0);


variable x1,y1 : std_logic_vector(2 downto 0);
begin
x1 := 0 & x;
y1 := 0 & y;
temp := x1 +y1;
return (temp);
end fun;

122
Use library ieee;
use ieee.std_logic_1164.all;
use ieee.std-logic_unsigned.all;
Use work.fun.all;

Entity fun2 is
port (a,b :in std_logic_vector(1 downto 0);
sum : out std_logic_vector(2 downto 0))
End fun2;

Architecture fun2_beh of fun2 is


begin
sum <= sum1(a,b);
End fun2_beh;

123
EXAMAPLE OF PROCEDURE
Use library ieee;
use ieee.std_logic_1164.all;
use ieee.std-logic_unsigned.all;

package pro is
procedure sum2 ( x,y :in std-lofic_vector (1 downto 0);
signal z :out std_logic_vector(2 downto0))
end pro;

package body pro is


procedure sum2 ( x,y :in std-lofic_vector (1 downto 0);
signal z :out std_logic_vector(2 downto0))
is
variable x1,y1 : std_logic_vector(2 downto 0);
begin
x1 := 0 & x;
y1 := 0 & y;
z1<:= x1 +y1;
end pro;
124
Use library ieee;
use ieee.std_logic_1164.all;
use ieee.std-logic_unsigned.all;
Use work.pro.all;

Entity pro2 is
port (a,b :in std_logic_vector(1 downto 0);
sum : out std_logic_vector(2 downto 0))
End profun2;

Architecture pro2_beh of fun2 is


begin
sum2 (a,b,sum) ;
End pro2_beh;

125
Examples

126
And Gate
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity and1 is
 Port(a:in std_logic;
b:in std_logic;
c1:out std_logic;
End and1;
 Architechture behaviuoral of and1 is
 Begin
 Process(a,b)
 Begin
 If(a=‘1’and b=‘1’)then
 C<=‘1’
 Else c<=‘0’;
 End if;
 End process;
 End behavioural;
Nand Gate
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity nand1 is
 Port(a:in std_logic;
b:in std_logic;
c1:out std_logic;
End nand1;
Architechture dataflow of nand1 is
Begin
C<=a nand b;
End dataflow;
Xor Gate
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity xor2 is
 Port(p:in std_logic;
q:in std_logic;
r:out std_logic);
End adder;
Architechture behavioural of xor2 is
Begin
r<=p xor q;
End behavioural;
Adder
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity adder is
 Port(a:in std_logic_vector(3 downto 0);
b:in std_logic_vector(3 downto 0);
c1:in std_logic;
S:out std_logic_vector(3 downto 0);
C0:out std_logic;
End adder;
Architechture behavioural of adder is
Component fa is
Port(a:in std_logic;
b:in std_logic;
c1: in std_logic;
a : out std_logic;
c :out std_logic);
End component;
Signal ca :std_logic_vector(4 downto);
Begin
Ca(0)<=ci;
Ioop1:for i in 0 to 3 generate
F:fa port map
(a)(i),b(i),ca(i),a(i),ca(i+1);
End generate loop1;
Co<=ca(4);
end behavioural;
Half Adder
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity xor1 is
 Port(p:in std_logic;
q:in std_logic;
r:out std_logic);
End xor1;
Architechture behavioural of xor1 is
Component and1 is
Port(a,b:in std_logic;c:out std_logic);
End component;
Component halfadder is
Port (a,b:in std_logic;
s,c:out std_logic);
End component;
Begin
U1:and1 port map(a,b,carry);
U2:xor1 portmap(a,b,sum);
End behaviural;
Full Adder
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity fa is
 Port(a:in std_logic;
b:in std_logic;
c1:in std_logic;
S:out std_logic;
C:out std_logic);
End fa;
 Architechture behavioural of fa is
 Signals1,s2,s3:std_logic;
 Component ha is
 Port(a,b:in std_logic;
 s,c:out std_logic) ;
 End component;
 Begin
 X:ha port map(a,b,s1,s2);
 y:ha port map(s1,c1,s,s3);
 C<=s2 or s3;
 End behavioural;
Mux
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity mux is
 Port(a:in std_logic_vector(15 downto 0);
sel:in std_logic_vector(3 downto 0);
Op:out std_logic;
End mux;
 Architechture behavioural of mux is
 Begin
 Process(a,sel)
 Begin
 Case(sel)is
 When”0000”=>
 op<=a(0);
 When”0001”=>
 op<=a(1);
 When”0010”=>
 op<=a(2);
 When”0011”=>
 op<=a(3);
 When”0100”=>
 op<=a(4);
 When”0101”=>
 op<=a(5);
 When”1000”=>
 op<=a(6);
143
 When”0111”=>
 op<=a(7);
 When”1000”=>
 op<=a(8);
 When”1001”=>
 op<=a(9);
 When”1010”=>
 op<=a(10);
 When”1011”=>
 op<=a(11);
 When”1100”=>
 op<=a(12);
 When”1101”=>
 op<=a(13);
 When”1110”=>
 op<=a(14);
 When”1111”=>
 op<=a(15);
 when others=>
 op<=‘Z’;
 End case;
 End process;
145
 end behavioural;
JK Flipflop
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity jkff is
 Port(j:in std_logic;
k:in std_logic;
clk:in std_logic;
q:out std_logic;
q1:out std_logic);
End jkff;
 Architechture behavioural of jkff is
 Begin
 Prcess(j,k,clk)
 Variable var:std_logic;
 Begin
 If(clk’event and clk=‘1’)then
 If (j=‘0’ and k=‘1’)then
 var:=‘0’;
 elsIf (j=‘1’ and k=‘0’)then
 Var:=‘1’;
 elsIf (j=‘1’ and k=‘1’)then
 Var:=not(var);
 elsIf (j=‘0’ and k=‘0’)then
 Var:=var;
 Else null;
 End if;
 End if;
 Q<=var;
 Q1<=not (var);
 End process;
 End behavioural;
T Flip Flop
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity tff is
 Port(t:in std_logic;
clk:in std_logic;
q:out std_logic;
q1:out std_logic);
End tff;
Architechture behavioural of tff is
Begin
Process(t,clk)
Variable a,b:std_logic;
Begin
If(clk’event and clk=‘1’)then
If(t=‘1’)then
Q<=t;
D flipflop
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity dff is
 Port(d:in std_logic;
clk:in std_logic;
q:out std_logic);
End dff;
151
 Architechture behavioural of dff is
 Begin
 Process(d,clk)
 Variable var:std_logic;
 Begin
 If(clk’event and clk=‘1’)then
 If(d=‘0’)then
 var:=‘1’;
 else
 null;
 end if;
 end if;
 Q<= var;
 end process;
 End behavioral;
152
Mod c
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity modc is
 Port(r:in std_logic;
clk:in std_logic;
count:out std_logic_vector(2 downto 0);

End modc;
 Architechture behavioural of modc is
 Begin
 Prcess(r,clk)
 Variable var:std_logic_vector(2 down to 0);
 Begin
 If (clk’evbent and clk=‘1’)then
 If (r=‘1’)then
 Var:=“000”;
 Else
 Var:=var+1;
 End if;
If(var:=“111”)then
Var:=“000”;
End if;
End if;
Count<=var;
End process;
End behavioural;
Rom
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity rom is
 Generic(words:integer:=8;
 Bits:integer:=8);
 Port(adder:in integer range0 to(words-1)
data:out std_logic_vector((bits-1)
downto 0);
 End rom;
 Architechture behavioural of rom is
 Type array1 is array(0 to (words-1))of
std_logic_vector((bite-1)down to 0);
 Constant memory:array1:=(“00000001”;)
 “00000011”;
 “00000111;
 “00001111”;
 “00011111”;
 “00111111”;
 ”01111111”;
 “11111111”);
 Begin
Process(addr)
Begin
Data<=memory(addr);
End process;
End behavioural;
Up Down counter
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity udcounter is
 Port(r:in std_logic;
clk:in std_logic;
updown:in std_logic;
count:out std_logic_vector(3 downto 0);
End udcounter;
 Architechture behavioural of udcounter is
 Begin
 Process(r,updown,clk)
 Variable var:std_logic_vector(3 downto 0);
 Begin
 If(clk’event and clk=‘1’)then
 If (r=‘1’)then
 var:=“0000”;
 elsIf (updown=‘1’)then
 Var:=var+1;
 Elsif(updown=‘0’)then
 Var:=var-1;
 Else
 Null;
 End if;
 If(var=“1010”or var=“1111”)then
 Var:=“0000”;
 End if;
 End if;
 Count<=var;
 End process;
 End behavioural;
Twisted
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity twisted is
 Port(r:in std_logic;
clk:in std_logic;
count:out std_logic_vector(3 downto
0));
End twisted;
Architechture behavioural of twisted is
Signal s:std_logic_vector(2 downto 0);
Begin
Process(clk)
Begin
If(clk’event and clk=‘1’)
If(r=‘1’)then
S<=“111”;
 Else
 S<=s+1;
 End if;
 End if;
 Case s is
 When”000”=>;count<=“0001”;
When”001”=>;count<=“0011”;
When”010”=>;count<=“0111”;
When”011”=>;count<=“1111”;
When”100”=>count<=“1110”;
When”101”=>;count<=“1100”;
When”110”=>;count<=“1000”;
When”111”=>;count<=“0000”;
When others=>null;
End case ;
End process;
End behavioural;
Ram
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity ram is
 Generic(words:integer:16;
 Bits:integer:=4);
 Port(clk:in std_logic;
Wr_en:in std_logic;
detain:in std_logic_vector(bits-1) downto 0);
Addr:in integer range 0 to (words-1);
Dataout:out std_logic_vector(bits-1)downto 0));
End ram;
Architechture behavioural of ram is
Type array1 is array(0 to (words-1)of
Std_logic_vector(bits-1)downto 0);
Signal memory:array1;
Begin
Process(clk,wr_en,datain,addr)
Begin
If(clk’event and clk=‘1’)then
 If(wr_en=‘1’)then
 Memory(addr<=datain);
 Else
 Dataout<=memory(addr);
 End if;
 Else
 Null;
 End if;
 End process;
 End behavioural;
Srla
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity srla is
 Port(s:in std_logic;
r:in std_logic;
clk:in std_logic;
q:out std_logic;
q1:out std_logic);
End srla;
 Architechture behavioural of srla is
 Signal var:std_logic:
 Begin
 If(clk’event and clk=‘1’)then
 If(s=‘0’ and r=‘1’)then
 Var<=‘0’;
 Elsif(s=‘1’ and r=‘0’)then
 Var<=‘1’;
 Elsif(s=‘1’ and r=‘1’)then
 Var<=‘Z’;
 Elsif(s=‘0’ and r=‘0’)then
 Var<=var;
 End if;
 End if;
 Q<=var;
 Q1<=not var;
 End process;
 End behavioral;
Srla nand
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity srla_nandgate is
 Port(s:in std_logic;
r:in std_logic;
clk:in std_logic;
q:out std_logic;
q1:out std_logic);
End srla_nandgate;
 Architechture behavioural of
srla_nandgate is
 Signal a,b,c,d:std_logic;
 Component nand1 is
 port(a,b:in std_logic;
 C:out std_logic);
 End component;
 Begin
 E;nand1 port map(s,clk,a);
F:nand1 port map(r,clk,c);
G:nand1 port map(a,d,b);
H:nand1 pot map(c,b,d);
Q<=b;
Q1<=d;
End behavioural;
SiSo
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity siso is
 Port(a:in std_logic;
clk:in std_logic;
b:out std_logic);
End siso;
 Architechture behavioural of siso is
 Signal s:std_logic_vector(3 downto 0):
 Begin
 Process(a,clk)
 begin
 If(clk’event and clk=‘1’)then
 S(3)<=s(2);
 S(2)<=s(1);
 S(1)<=s(0);
 S(0)<=a;
 Else
 null;
 End if;
 B<=s(3);
 End process;
 End behavioral;
parity
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity parity is
 Port(a:in std_logic_vector(2 downto 0);
pg:out std_logic;
pc:out std_logic);
End parity;
 Architechture behavioural of parity is
 Signal s1:std_logic_vector;
 Begin
 With a select
 S1<=‘1’when “000”;
 ‘0’when “001”;
 ‘0’when “010”;
 ‘1’when “011”;
 ‘0’when “100”;
 ‘1’when “101”;
 ‘1’when “110”;
 ‘0’when “111”;
 ‘0’when others;
 Pc<=(not s1);
 Pg<=s1;
Queue
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity queue is
 numeric(bits: integer:=4;
 words:integer:=8);
 Port(clk:in std_logic;
r_w: in std_logic;
datain: in std_logic_vector(bits-1) downto 0);
dataout: out std_logic_vector(bits-1)downto 0);
pc:out std_logic);
Empty : out std_logic;
Full: out std_logic);
End queue;
 Architectural behavioral of queue is
 Type stack1 is array(0 to (words)) of
 Std_logic_vector((bits-1)downto 0);
 Signal s1,s2: integer range 0 to (words);
 Signal memory: stack1;
 Begin
 Process(clk,r_w:datain)
 Begin
 If(clk’event and clk =‘1’)then
 If(r_w=‘0’)then
 If(s1=8)then
 Full<=‘1’;
 Else
 S1<=s1+1;
 Memory(s1)<=datain;
 Empty<=‘0’;
 Full<=‘0’;
 End if;
 Else
 If(s1=0 or s2 =8) then
 Empty<=‘1’;
 Else
 Empty<=‘0’;
 S2<=s2+1;
 Dataout<=memory(s2);
 End if;
181
End if;
Else
Null;
End if;
End process;
End behavioral;

182
Q1<=not(t);
Else null;
End if;
End if;
End process;
End behavioural;
Stack
 Library ieee;
 Use ieee.std_logic_1164.all;
 Use ieee.std_logic_airth.all;
 Use ieee.std_logic_unsigned.all;
 entity stack is
 numeric(bits: integer:=4;
 words:integer:=8);
 Port(clk:in std_logic;
r_w: in std_logic;
datain: in std_logic_vector(bits-1) downto 0);
dataout: out std_logic_vector(bits-1)downto 0);
pc:out std_logic);
Empty : out std_logic;
Full: out std_logic);
End stack; 184
 Architectural behavioral of queue is
 Type stack1 is array(0 to (words)) of
 Std_logic_vector((bits-1)downto 0);
 Signal s: integer range 0 to (words);
 Signal memory: stack1;
 Begin
 Process(clk,r_w:datain)
 Begin
 If(clk’event and clk =‘1’)then
 If(r_w=‘0’)then
 If(s1=8)then
 Full<=‘1’;
 Else
 S<=s+1;

185
 Memory(s)<=datain;
 Empty<=‘0’;
 Full<=‘0’;
 End if;
 Else
 If(s=0) then
 Empty<=‘1’;
 Else
 full<=‘0’;
 Empty<=‘0’;
 Dataout<=memory(s);
 S<=s-1;
 End if;

186
End if;
Else
Null;
End if;
End process;
End behavioral;

187

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