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Introduction PERIOD Constraints OFFSET Constraints FROM:TO Constraints Modular Design Constraints

6.xi Timing and Constraints 2

NGC/EDIF netlist

UCF User Constraints File

NGDBUILD
Flatten Hierarchical Design .NGD

MAP
Logical to Physical translation Group LUTs and FFs into CLBs

Design Flow
Optional: Reports block delays

.NCD

.PCF

TRCE
Static Timing Estimates

PAR
Layout of Physical Design Routes Physical Design

BITGEN
Generates configuration file

.NCD .BIT
6.xi Timing and Constraints 3

Internal clock speed for one or more clocks I/O speed Logic using multi-cycle clocks Pad to Pad timing Pad Locations & Logic Locations Clk & CE Speed
I/O Speed I/O Speed
X CLK Y Z<0:9>
D Q D Q

Logic Locations

1 Level of Logic 2 Levels of Logic

OUT1

Pin Locations

OUT2

Pin Locations

Pin 2 Pin Speed


6.xi Timing and Constraints 4

Timing Constraints Specify delay along logic paths Allows both high level and highly detailed timing control C C AB AB M= Location Constraints N M= K KN BL BL AP 1 Specify location of components on FPGA M OP C _F FL AB MY T ST M= S IN Specify mapping constraints KN IN BL
IN ST FL OP 2

6.xi Timing and Constraints 5

What is the motive behind timing analysis


Meet the desired frequency by:
Coverage (100% is ideal case) Slack (Timing budget must account for jitter, noise, etc) Special Case analysis (Multi-Cycle, False path)

How is this accomplished?


Constraints!
Timing Placement
6.xi Timing and Constraints 6

They can be input in a separate file called a .UCF (User Constraints File) They can be added to HDL source code if your compiler supports them Timing constraints may be applied to a Schematic using the TIMESPEC symbol (FROM:TO s)

TIMESPEC

Note: This is the order of priority between these files.

6.xi Timing and Constraints 7

LOGICAL DOMAIN
NGC/EDIF netlist UCF User Constraints File

User netlist and logical constraints

NGDBUILD DESIGN TRANSLATION MAP Mapped design and physical constraints DRC

PHYSICAL DOMAIN

.NCD

.PCF

PAR

TRCE

FPGA Editor NGDANNO

6.xi Timing and Constraints 8

Where do you find syntax?


Constraints Guide (SW Manuals)
http://www.xilinx.com/support/sw_manuals/xilinx6/index.htm

Constraints Editor
This is a great tool to write out constraints for you with the correct syntax

Online Timing presentation


Tech tips -> Timing and Constraint -> Related Features
6.xi Timing and Constraints 9

What constraints are important to be familiar with?


PERIOD OFFSET Creating Groups (TNM, TNM_NET, TIMEGRP) FROM:TO TIMESPEC

6.xi Timing and Constraints 10

Using PERIOD and OFFSET constraints

Setup Calculation
An internal setup violation occurs when the data changes at the destination FF after the clock arrives.

Hold Calcuation
An internal hold violation occurs when the data changes at the destination FF before the clock arrives The data delay is less than the positive clock skew
6.xi Timing and Constraints 12

2ns

PERIOD is the duration of the clock and can be configured to have different duty cycles Derived clocks can be defined as a function of another clock (*,/) and will have cross clock domain analysis done. PERIOD is preferred over FROM:TO constraints; The tools will have a faster runtime. PERIOD should cover most of design. PERIOD only covers from Sync. Elements to Sync. Elements, like Flip flops to flip-flops
6.xi Timing and Constraints 13

The PERIOD constraint covers paths between synchronous elements clocked by the reference net The PERIOD constraint does NOT analyze delay paths:
From input pads to output pads (purely combinatorial) From input pads to synchronous elements From synchronous elements to output pads Between unrelated clocks
ADATA CLKA
FLOP1 D Q FLOP2 D Q FLOP3 D Q

OUT1

BUS [7..0]
CLKB CDATA

BUFG

FLOP4 D Q

FLOP5 D Q

OUT2

= Unconstrained Data Path


BUFG

= Constrained Data Path

6.xi Timing and Constraints 14

The PERIOD constraint takes the following into account:


Data path delay Clock skew on global and local clocks Clock phase including DCM phase and negative edge clocking Clock duty cycles

HOLD violation check is done for all paths


FF1 FF2

CLK BUFG

6.xi Timing and Constraints 15

Clock skew = destination clock path delay - source clock path delay Positive clock skew is truncated to 0 in the timing report for setup paths
Positive clock skew is used in hold time calculations

6.xi Timing and Constraints 16

clk20

Tiopi = 0.825 net = 0.798

DCM CLKIN CLK0

CLK90

net = 0.852 net = 0.860

net = 0.639 clk20g

ff_0f D Q

ff_90 D Q

clk20_90g Tgi0o = 0.860

net = 0.639

Tdcmino = -4.197

Destination Clock Delay - Source Clock Delay


(0.825 + 0.798 + -4.197 + 0.860 + 0.860 + 0.639) (0.825 + 0.798 + -4.197 + 0.852 + 0.860 + 0.639) = 0.008 ns

6.xi Timing and Constraints 17

PERIOD analyzes the following: Synchronous element to synchronous element data path calculations Automatically deals with inverted clock pins Deals with non 50% duty cycles clocks If the Source Clock Timing Constraint is related to the Destination Clock Timing Constraint, the Destination Clock Timing Constraint will cover cross clock domain analysis.

Period#2 will control this path, if derived. (TS_Period#1 * 2)


Period#1 Period#2

6.xi Timing and Constraints 18

PERIOD will trace THROUGH the Address pins of all RAM, and TO the D/WE pins of Sync RAM (THROUGH WE of Async RAM)
Sync RAM WE D WCLK ADDRESS ASync RAM WE

ADDRESS

6.xi Timing and Constraints 19

DCM

clk20

CLKIN CLK0

clk20_0 clk20_90

CLK90

User entered constraint on DCM clock input


NET "clk20" TNM_NET = "clk20"; TIMESPEC "TS_clk20" = PERIOD "clk20" 20 ns HIGH 50 %;

Translate step generates DCM clock constraints


CLK0: TS_clk20_0=PERIOD clk20_0 TS_clk20*1.000000 HIGH 50.000000% CLK90: TS_clk20_90=PERIOD clk20_90 TS_clk20*1.000000 PHASE + 5.000000 nS HIGH 50.000000%

6.xi Timing and Constraints 20

TIMESPEC TSidentifier =PERIOD TNM_reference period {HIGH | LOW} [high_or_low_time] Covers all synchronous to synchronous paths with the same reference net example
net clk TNM = clk_in ; TIMESPEC TS_clk_in = PERIOD clk_in 10 ns HIGH 50%;

6.xi Timing and Constraints 21

By net NET CLK300 PERIOD = 3.334 ns ; NET CLK200 PERIOD = 5 HIGH 20 ; By group: (The Recommended Way) NET CLK50 TNM_NET = CLK50_GRP ; #OR NET CLK50_I TNM = CLK50_GRP; NET CLK25 TNM = CLK25_GRP ; TIMESPEC TS_CLK_FULL = PERIOD CLK50_GRP 20; TIMESPEC TS_CLK_HALF = PERIOD CLK25_GRP TS_CLK_FULL * 2 ; (Note: Must use signal after global buffer for TNM groups. See TNM/TIMEGRP Section for details)
TNM_NET=CLK50_GRP
BUFG
6.xi Timing and Constraints 22

TNM=CLK50_GRP

Recommended way Allows PERIOD to be passed through DCM by NGDBuild Allows constraints to be related using the TIMESPEC name

6.xi Timing and Constraints 23

Clocks are related by using the period constraint


Clocks are not related based upon the design Translate process creates period constraints on the output DCM clocks relative to the user defined period constraint on the DCM input clock Related
TIMESPEC "TS_clk20" = PERIOD "clk20_grp" 20 ns; TS_clk20_0=PERIOD clk20_0_grp TS_clk20*1.0; TS_clk20_90=PERIOD clk20_90_grp TS_clk20*1.0 PHASE + 5.0;

Unrelated
TS_clk20_0=PERIOD clk20_0_grp 20 ns; TS_clk20_90=PERIOD clk20_90_grp 20 ns PHASE + 5.0;

6.xi Timing and Constraints 24

Slack equation Basic element type is listed Updated Logic Levels Updated! Only levels of logic, not Clock to Out and Setup Clock names and time of active edge. Includes Clock Phase Data path with Cross Probing Links to Floorplanner or Synthesis Tool (In Timing Analyzer) Web link to graphical picture of delay type! (In Timing Analyzer)

6.xi Timing and Constraints 25

DCM CLKIN CLK0

ff_0f

ff_90 Q D Q

clk20g clk20_90g

CLK90

15 ns

10 5 15

20 25

30 35

40

CLK0 CLK90
Requirement is difference between clock edges Clock edge and time of active edge

New!
6.xi Timing and Constraints 26

The path requirement will automatically be reduced by half if a two-phase clock is detected

Single-Phase Maximum

Two-Phase Maximum
================================================================================ Timing constraint: TS_CLK = PERIOD TIMEGRP "CLK" 6 nS HIGH 50.000000 % ; 3 items analyzed, 0 timing errors detected. Minimum period is 2.618ns. -------------------------------------------------------------------------------- 6ns is the maximum allowed PERIOD declared in the UCF Slack: 1.691ns (requirement - (data path - negative clock skew)) Source: a2 TRCE cut the spec in half (6ns/2=3ns) for this path Destination: a3 Requirement: 3.000ns Two-phase clock is indicated here Data Path Delay: 1.309ns (Levels of Logic = 2) Negative Clock Skew: 0.000ns This indicates the magnitude of the path delay between Source Clock: CLK_BUFGP falling at 3.000ns flops. There is no adjustment to this figure. Destination Clock: CLK_BUFGP rising at 6.000ns Data Path: a2 to a3 Delay type Delay(ns) ---------------------------Tcko 0.320 net (fanout=1) 0.778 Tdick 0.211 ---------------------------Total 1.309ns

Logical Resource(s) ------------------a2 a2 a3 -----------------------------(0.531ns logic, 0.778ns route) (40.6% logic, 59.4% route)

This indicates that the worst-case period for this ENTIRE spec is 2.618ns (1.309ns x 2). If there had been a single-phase path in this PERIOD spec that was 3ns, it would have been reported as the worst-case value, if it were 2ns, it would not. This is the remaining slack (6ns/2 - 1.309ns = 1.691ns).

6.xi Timing and Constraints 27

Source

Destination

DATA_IN CLK

DATA

1 ns

DATA_OUT

2 ns

10

12

CLK
(at source FF)

CLK
(at destination FF)

DATA_IN
(at source input FF)

DATA1 DATA0 DATA0 DATA0

DATA2 DATA1 DATA1 DATA1

DATA
(at source output FF)

DATA
(at destination input FF)

DATA_OUT
(at destination output FF)

6.xi Timing and Constraints 28

2ns

Hold Errors shown after the associated PERIOD constraint

Hold equation = Data - Clock Skew Clock skew is greater than data delay Clock to Out is part of data delay FF Hold Time, often this is negative

6.xi Timing and Constraints 29

Support for families that have the Interactive Datasheet Information in software help
not web

New

6.xi Timing and Constraints 30

If this property is set to TRUE, the PERIOD specifications created at the DCM output will be adjusted accordingly
DCM

clk20

CLKIN CLK0

clk20_0 clk20_90

CLK90

User entered constraint on DCM clock input


NET "clk20" TNM_NET = "clk20"; TIMESPEC "TS_clk20" = PERIOD "clk20" 20 ns HIGH 50 %;

Translate step generates DCM clock constraints


CLK0: TS_clk20_0=PERIOD clk20_0 TS_clk20*2.000000 HIGH 50.000000% CLK90: TS_clk20_90=PERIOD clk20_90 TS_clk20*2.000000 PHASE + 5.000000 nS HIGH 50.000000%
6.xi Timing and Constraints 31

Timing Report documentation was re-written Documentation shows an actual report with explanations about each section

6.xi Timing and Constraints 32

OFFSETs allows the user to specify the internal data delay from/to the I/Os with respect to the clock
OFFSET IN BEFORE OFFSET OUT AFTER

Alternatively, OFFSETs allows the user to specify external data and clock relationships for the timing on paths to and from the I/Os. The software determines the internal requirements
OFFSET IN AFTER OFFSET OUT BEFORE

Clock delay is used in the equation

6.xi Timing and Constraints 33

Internal delays determined by the tools

OFFSET IN
d2

OFFSET OUT
d3

d4 d1

DEV1
CLK

FPGA

DEV2

6.xi Timing and Constraints 34

The OFFSET constraints defines the relationship between the data and the initial edge of the clock at the pins of the FPGA
The OFFSET Constraint does not optimize paths clocked by an internally generated clock.

The initial edge of the clock is defined with the PERIOD constraint using HIGH/LOW keyword
Initial edge rising (default)
TIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %;

Initial edge falling


TIMESPEC TS_clock = PERIOD clock_grp 10 ns LOW 50 %;
6.xi Timing and Constraints 35

The OFFSET IN constraint covers paths from the input pads to synchronous elements taking clock delay into account. The OFFSET IN constraint does NOT optimize paths clocked by internally generated clocks
ADATA CLKA
FLOP1 D Q FLOP2 D Q FLOP3 D Q

OUT1

BUS [7..0]
CLKB CDATA

BUFG

FLOP4 D Q

FLOP5 D Q

OUT2

= Unconstrained Data Path


BUFG

= Constrained Data Path

6.xi Timing and Constraints 36

Setup = Data Delay + FF Setup - Prorated (Clock Delay)


The longer the clock delay, the smaller the external setup time therefore clock delay is good for fast setup times TRCE/Timing Analyzer uses a prorating factor on the clock delay and a maximum delay for the data delay. A setup violation in the device could be caused by the the data delay, at the maximum (slow) and the clock delay, running faster than the maximum.

What is the prorating factor?


85% for Global Routes 80% for Local Routes
Note: Prorating is only done for VirtexII and newer families.
6.xi Timing and Constraints 37

Hold reported in datasheet section of the report and in the detailed section with the fastpaths option enabled. Hold = Clock Delay + FF Hold - Prorated (Data Delay)
The longer the data delay, the smaller the hold time therefore data delay is good for hold times TRCE/Timing Analyzer uses a prorating factor on the data delay and the maximum delay for the clock delay. A hold violation in the device could be caused by the clock delay can be at the maximum (slow) and the data delay running faster than the maximum.

What is the prorating factor?


85% for Global Routes 80% for Local Routes
Note: Prorating is only done for VirtexII and newer families.
6.xi Timing and Constraints 38

NET CLK PERIOD = 20nS HIGH; NET Din OFFSET = IN 2nS BEFORE CLK;
UPSTREAM DEVICE

FPGA
Din

CLK CLK

In other words: The designer guarantees that the data will be valid here, at its input data pad, 2ns BEFORE the reference clock edge arrives here, at its clock pad.

Reference clock edge specified with HIGH keyword in clock PERIOD Data created from upstream device on this falling edge.
6.xi Timing and Constraints 39

Data registered into FPGA on this falling edge.

2ns

Valid

clock_in
10 ns 3ns

data
TIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %; OFFSET = IN 3 ns BEFORE clock;

The initial edge of the clock defines time 0ns PERIOD defines the rising edge is the initial edge at time 0ns The OFFSET constraint is in reference to time 0ns Data is valid 3ns before the initial edge of the clock
Slack = (Requirement - (Data Path - Clock Path - Clock Arrival)) Clock Arrival will be 0 ns since initial edge is rising edge
6.xi Timing and Constraints 40

clock_in
10 ns 3ns

clk90 data Data is valid 3ns before rising edge of clock


TIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %; OFFSET = IN 3 ns BEFORE clock; Slack = (Requirement - (Data Path - Clock Path - Clock Arrival)) Clock Arrival will be 2.5 ns

6.xi Timing and Constraints 41

clock_in
10 ns 3ns

clk0 data Data is valid 3ns before rising edge of clock


TIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %; OFFSET = IN 3 ns BEFORE clock; Slack = (Requirement - (Data Path - Clock Path - Clock Arrival)) Clock Arrival will be Fixed Phase Shift Amount

6.xi Timing and Constraints 42

clock_in
10 ns 2ns 3ns 3ns

data_rising data_falling Data valid 3ns before rising and falling edge
TIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %; OFFSET = IN 3 ns BEFORE clock; OFFSET = IN -2 ns BEFORE clock TIMEGRP falling_ffs_grp;
Note: Data is valid 2ns after the initial (rising )edge therefore use -2

Slack = (Requirement - (Data Path - Clock Path - Clock Arrival)) Clock Arrival will be 0 ns for rising edge and 5 ns for falling edge
6.xi Timing and Constraints 43

Slack equation Clock name and time of active edge Data Path Delay Clock Path Delay

6.xi Timing and Constraints 44

TIMESPEC TS_CLK20 = PERIOD CLK20_grp 20 HIGH 50%; NET DATA OFFSET = IN -2 BEFORE CLK20;
0 5 10 15 20 25 30 35 40

CLK20 CLK20_90 2ns DATA


Clock edge and time of active edge

6.xi Timing and Constraints 45

NET CLK PERIOD = 20nS HIGH; NET Din OFFSET = IN 16nS AFTER CLK;
UPSTREAM DEVICE

FPGA
Din

CLK

CLK

In other words: The Data to be registered in the FPGA will be available on the FPGA s input Pad 16ns AFTER the reference clock pulse is seen by the Upstream Device. For the purposes of the OFFSET constraint syntax, assume no skew on CLK between the chips. A PERIOD constraint is required to indicate when the subsequent clock pulse will be seen by the FPGA to clock in the Data.

Reference clock edge specified with HIGH keyword in clock PERIOD Data Out of DEV1 on this edge.
6.xi Timing and Constraints 46

16ns

Valid

Data registered in FPGA on this edge.

The OFFSET OUT constraint covers paths from synchronous elements to output pads taking clock delay into account. The OFFSET OUT constraint does NOT optimize paths clocked by internally generated clocks

ADATA CLKA

FLOP1 D Q

FLOP2 D Q

FLOP3 D Q

OUT1

BUS [7..0]
CLKB CDATA

BUFG

FLOP4 D Q

FLOP5 D Q

OUT2

= Unconstrained Data Path


BUFG

= Constrained Data Path

6.xi Timing and Constraints 47

NET CLK PERIOD = 20nS LOW; NET Din OFFSET = OUT 5nS AFTER CLK

FPGA

DOWNSTREAM DEVICE

In other words: The Data to be registered in the Downstream Device will be available on the FPGA s data output pad 5ns AFTER the reference clock pulse is seen by the FPGA, at its clock pad.

Falling reference clock edge specified with LOW keyword in clock PERIOD

Data created from FPGA on this falling edge.

5ns

Valid

Data registered into downstream device on this rising edge.

6.xi Timing and Constraints 48

clock_in
10 ns 3ns

data
TIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %; OFFSET = OUT 3 ns AFTER clock;

The initial edge of the clock defines time 0ns PERIOD defined with HIGH means the rising edge is the initial edge at time 0ns The OFFSET constraint is in reference to time 0ns Data is valid 3ns after the initial edge
Slack = (Requirement - (Clock Arrival + Clock Path + Data Path)) Clock Arrival will be 0 ns since initial edge is a rising edge
6.xi Timing and Constraints 49

clock_in
10 ns 5ns

clk90 data Data is valid 5ns after rising edge of clock


TIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %; OFFSET = OUT 5 ns AFTER clock; Slack = (Requirement - (Clock Arrival + Clock Path + Data Path)) Clock Arrival will be 2.5 ns

6.xi Timing and Constraints 50

clock_in
10 ns 5ns

clk0 data Data is valid 3ns before rising edge of clock


TIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %; OFFSET = OUT 5 ns AFTER clock; Slack = (Requirement - (Clock Arrival + Clock Path + Data Path)) Clock Arrival will be Fixed Phase Shift Amount

6.xi Timing and Constraints 51

clock_in
10 ns 3ns

8ns 3ns

data_rising data_falling Data is valid 3ns after rising and falling edge
TIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %; OFFSET = OUT 3 ns AFTER clock; OFFSET = OUT 8 ns AFTER clock TIMEGRP falling_ffs_grp ; Slack = (Requirement - (Clock Arrival + Clock Path + Data Path)) Clock Arrival will be 0 ns for rising edge and 5 ns for falling edge
6.xi Timing and Constraints 52

Slack equation Clock name and time of active edge Clock Path Delay Data Path Delay

6.xi Timing and Constraints 53

TIMESPEC TS_CLK20 = PERIOD CLK20_grp 20 HIGH 50%; NET DATA OFFSET = OUT 17 AFTER CLK20;
0 5 10 15 20 25 30 35 40

CLK20 CLK20_90

17ns
DATA DATA

Clock name and time of active edge

6.xi Timing and Constraints 54

NET CLK PERIOD = 20nS HIGH; NET Din OFFSET = OUT 15nS BEFORE CLK;

d4

FPGA
This says, Data will be valid here, 15nS BEFORE the clock arrives here!

..

In other words: The Data to be registered in the Downstream Device will be available on the FPGA s output Pad 25ns BEFORE the clock pulse is seen by the Downstream Device. For the purposes of the OFFSET constraint syntax, assume no skew on CLK between the chips. A PERIOD constraint is required to indicate when the reference clock pulse was seen by the FPGA to clock out the Data.

Data Out of FPGA on this edge.

15ns

Data Into DEV2 on this edge.

Valid

6.xi Timing and Constraints 55

14ns
D Q

Determined by tools 40ns


D Q

Determined by tools 25ns


D Q D Q

CLOCK

Upstream Device

XILINX DEVICE

Downstream Device

The following two UCF files are equivalent:


NET CLOCK PERIOD=40; ##External (shown in diagram) TIMEGRP ADD_IN_GRP OFFSET = IN 14 AFTER CLOCK; TIMEGRP ADD_OUT_GRP OFFSET = OUT 25 BEFORE CLOCK; NET CLOCK PERIOD=40; ##Internal (not shown in diagram): TIMEGRP ADD_IN_GRP OFFSET = IN 26 BEFORE CLOCK; TIMEGRP ADD_OUT_GRP OFFSET = OUT 15 AFTER CLOCK;
6.xi Timing and Constraints 56

The BEFORE and AFTER variations of the OFFSET are related by the total period

Global: All inputs/outputs are offset relative to a clock.


For example: OFFSET = IN 2ns BEFORE clk1
Indicates that all inputs will have data present at the pad at least 2ns before the reference edge of clk1 arrives at the pad.

Grouped: User specified group of pads


For example: TIMEGRP my_input_pad OFFSET = IN 2n BEFORE clk1
Indicates that all inputs will have data present at the pad at least 2ns before the reference edge of clk1 arrives at the group my_input_pad of pads.

Net-Specific: A specific input/output is offset relative to a clock.


For example: NET DATA_IN OFFSET = IN 2ns BEFORE clk1
Indicates that DATA_IN will have data present at the pad at least 2ns before the triggering edge of clk1 arrives at the data_in pad.

6.xi Timing and Constraints 57

Data Path Groups allow the user to define a specific set of input pads to which an OFFSET constraint applies. Consider the following example.
TIMEGRP DATA_GRP = PADS(DATA*); NET CLK PERIOD = 20nS; TIMEGRP DATA_GRP OFFSET = IN 10 BEFORE CLK;

Data1 Data2 Data3

Out1 Out2 Out3 Result

You can also add a clock register time group. Input D TIMEGRP BEF = FFS(Out*); TIMEGRP DATA_GROUP OFFSET = IN 10 BEFORE CLK BEF; This restricts the constraint to registers B, E, and F.

6.xi Timing and Constraints 58

Clock register time groups allows the user to define a specific set of registers to which an OFFSET constraint applies based on a clock edge. Consider the following example.
NET CLK PERIOD = 20nS; OFFSET = IN 4nS BEFORE CLK TIMEGRP AB; OFFSET = IN 6nS BEFORE CLK TIMEGRP C; DATA A CLK
You can define time groups for the registers A,B, and C, even though these registers have the same data and clock source. TIMEGRP AB = RISING FFS; TIMEGRP C = FALLING FFS; This allows the user to perform two different timing analysis for the registers.

6.xi Timing and Constraints 59

Global OFFSET constraints


OFFSET = in 5 ns before clock OFFSET = out 7 ns after clock

Specific OFFEST constraints


TIMEGRP my_pads_grp OFFSET = in 5 ns before clk;
my_pads_grp_ is a user defined group.

NET my_input_net OFFSET = in 5 ns before clk;


NOTE: OFFSET constraints have to reference a clock net that exist at a pad. Internally generated clocks can not be used in OFFSET specification
OFFSET = out 7 ns after clock;
6.xi Timing and Constraints 60

Wildcard Grouping Specification


NET ADDR_<*> TNM = ADDR_IN_GRP; TIMEGRP ADDR_IN_GRP OFFSET = IN 15 AFTER clk50; NET ADDR_<*> TNM = ADDR_OUT_GRP; TIMEGRP ADDR_OUT_GRP OFFSET = OUT 35 BEFORE clk50;

Global Control
OFFSET = IN 35 ns BEFORE COMP OFFSET = OUT 30 ns AFTER COMP clk50 clk50 ; ;

6.xi Timing and Constraints 61

Handled as clock phase instead of clock delay Must have following two DCM attributes:
PHASE_SHIFT={-255/255} CLKOUT_PHASE_SHIFT=FIXED or VARIABLE

NGDBUILD adds phase to the PERIOD constraint using the PHASE keyword Example from NGDBUILD report file
CLK0: TS_fixed_phase_clk_0=PERIOD fixed_phase_clk_0 TS_dcm_clk_in*1.000000 PHASE + 0.781250 nS HIGH 50.000000%

6.xi Timing and Constraints 62

Slack is 8.414ns Fixed Phase Shift accounted in Clock Arrival Time

DCM delay does not contain Fixed Phase Shift: (-3.301 + 0.781 = -2.520) Total Clock Delay

6.xi Timing and Constraints 63

2.5

5
DATA
D Q

CLK 1ns DATA_IN -1.5ns

CLK
D Q

Create Period
NET CLK TNM_NET = CLK_GRP; TIMESPEC "TS_CLK" = PERIOD CLK_GRP" 5 ns HIGH 50%;

Create Groups
INST DATA_IN[*] TNM = DATA_IN; TIMEGRP FF_RISING = RISING CLK_GRP ; TIMEGRP FF_FALLING = FALLING CLK_GRP;

Create OFFSET constraint


TIMEGRP DATA_IN OFFSET IN = 1 BEFORE CLK TIMEGRP FF_RISING; TIMEGRP DATA_IN OFFSET IN = -1.5 BEFORE CLK TIMEGRP FF_FALLING;
6.xi Timing and Constraints 64

2.5

5
DATA
D Q

CLK 1ns DATA_IN -1.5ns

CLK
D Q

Create Period
NET CLK TNM_NET = CLK_GRP; TIMESPEC "TS_CLK" = PERIOD CLK_GRP" 5 ns HIGH 50%;

Create Groups
INST DATA_IN[*] TNM = DATA_IN; TIMEGRP FF_FALLING = FALLING CLK_GRP;

Create OFFSET constraint


OFFSET IN = 1 BEFORE CLK; TIMEGRP DATA_IN OFFSET IN = -1.5 BEFORE CLK TIMEGRP FF_FALLING;
6.xi Timing and Constraints 65

2.5

5
DATA_HI
D Q

CLK 1.25ns DATA_OUT 3.75ns


CLK

DATA_OUT DATA_LO
D Q

Create Period
NET CLK TNM_NET = CLK_GRP; TIMESPEC "TS_CLK" = PERIOD CLK_GRP" 5 ns HIGH 50%;

Create Groups
INST DATA_OUT[*] TNM = DATA_OUT; TIMEGRP FF_RISING = RISING CLK_GRP ; TIMEGRP FF_FALLING = FALLING CLK_GRP;

Create OFFSET constraint


TIMEGRP DATA_OUT OFFSET OUT = 1.25 AFTER CLK TIMEGRP FF_RISING; TIMEGRP DATA_OUT OFFSET OUT = 3.75 AFTER CLK TIMEGRP FF_FALLING;
6.xi Timing and Constraints 66

2.5

5
DATA_HI
D Q

CLK 1.25ns DATA_OUT 3.75ns


CLK

DATA_OUT DATA_LO
D Q

Create Period
NET CLK TNM_NET = CLK_GRP; TIMESPEC "TS_CLK" = PERIOD CLK_GRP" 5 ns HIGH 50%;

Create Groups
INST DATA_OUT[*] TNM = DATA_OUT; TIMEGRP FF_FALLING = FALLING CLK_GRP;

Create OFFSET constraint


OFFSET OUT = 1.25 AFTER CLK; TIMEGRP DATA_OUT OFFSET OUT = 3.75 AFTER CLK TIMEGRP FF_FALLING;
6.xi Timing and Constraints 67

IO Timings are reported in the Datasheet Report


Setup/Hold for Inputs
Setup = data path - clock path - clock arrival + uncertainty Hold = clock path + clock arrival + uncertainty - data path

Clock to Out for Outputs


Clk2Out = clock path + data path + uncertainty

Numbers do include any clock phase Numbers do include clock delay


This includes delay introduced by DESKEW_ADJUST

Setup and Hold are calculated using MAX-MAX* numbers


Note: MAX* are prorated values for VirtexII and newer families
6.xi Timing and Constraints 68

Offset only covers IO timing with External clocks Use FROM-TO constraint to cover IO clocked by internal clocks (clocks generated by LUT or FF)
Create Groups
INST DATA_OUT[*] TNM = DATA_OUT;

Create FROM:TO constraint


TIMESPEC TS_DATA = FROM FFS TO DATA_OUT 3;

6.xi Timing and Constraints 69

Creating Groups and Using FROM:TO constraints

A FROM-TO constraint defines the delay between two groups of logic


Logic paths typically start and stop at pads, registers, latches, RAM, multipliers, CPUs and high speed IOs (MGT)

It is used to constrain the following types of paths:


Multi-cycle paths --If not expected to meeting the original single cycle clock period Data paths between unrelated clocks False Paths --If paths/net that are known not to have a timing requirement

No HOLD violation check is done for FROM:TO paths

6.xi Timing and Constraints 71

Timing constraints are applied to logic paths Logic paths typically start and stop at pads, and synchronous elements The tool recognizes the following keywords to define endpoints or time groups: PADS All I/O pads FFS All flip-flops LATCHES All latches RAMS All RAM elements BRAMS_PORTA All Port A Dual Block RAM elements BRAMS_PORTB All Port B Dual Block RAM elements HSIOS All High Speed I/O elements (RocketI/O) CPUS All PowerPC elements MULTS All Multiplier elements Keywords can be used globally, and to create design sub-groups
6.xi Timing and Constraints 72

User created groups


Combinations of existing groups Groups by pattern matching on net names Groups by hierarchy

Use the TNM/TNM_NET attribute to create User Defined Groups All elements tagged with the same TNM/TNM_NET name are considered a group

6.xi Timing and Constraints 73

[NET|INST|PIN] object_name TNM = predefined_group identifier ;


object_name is the name of the element or signal to be grouped predefined_group is an optional keyword identifier can be any combination of letters, number, or underscores
Do not use reserved words such as FFS, LATCHES, RAMS... This variable is case sensitive (TNM=abc TNM=ABC)

TNM can be applied to any net, element pin, primitive or macro Pronounced Tee-Name

6.xi Timing and Constraints 74

NET clock TNM=clk_group; Any Keyword element can be made into a group for timing purposes In this example the net clock is traced forward to the two flip-flops (FFS). These flip-flops are timing-named (TNM) with the name clk_group . clk_group can now be referenced by this TNM in TIMESPECs
D Q D Q

OUT1 CLOCK

OUT2

6.xi Timing and Constraints 75

NET clock TNM=clk_group; These timing groups can overlap, meaning a FFS, LATCHES, etc. can belong to multiple groups if necessary to describe your design s timing Time constraints are case sensitive (TNM=abc TNM=ABC) Groups are ideal for identifying groups of logic that work at different speeds .(multi-cycle paths and other slow exceptions).

6.xi Timing and Constraints 76

NET MYDATA TNM=DATA_GRP;


The two RAMS and Flip Flop are include in the DATA_GRP group

NET MYDATA TNM=RAMS FI_CORE;


MYDATA

Only the two RAMS are included in the FI_CORE group because of the predefined group: RAMS

6.xi Timing and Constraints 77

NET clock TNM_NET=clk_group; TNM_NET is equivalent to TNM on a net except for pad nets. If you place a TNM on a pad net, it will trace backwards to the pad and not trace forward through the buffer to the next synchronous element. TNM_NET was created for this purpose. If you place a TNM_NET on a pad net, it will trace through the buffer to the next synchronous element. TNM_NET is extremely useful for synthesis designs. The ports are directly connected to pads. TNM_NET can be used in UCF or NCF only.
6.xi Timing and Constraints 78

NET PADCLK TNM = PADGROUP;


will contain the IPAD symbol only

NET INTCLK TNM = FFS FLOPGROUP;


will include FF1 and FF2 into the group called FLOPGROUP

NET PADCLK TNM_NET = FFS FLOPGROUP;


also includes FF1 and FF2 into the group called FLOPGROUP

PADCLK
IPAD BUFG

INTCLK

FF1
C

FF2
C

6.xi Timing and Constraints 79

The TNM attribute on a macro places all elements IN the macro (at all levels of hierarchy) into the same group Paths are traced downward rather than forward along a net

6.xi Timing and Constraints 80

INST macro1 TNM = LATCHES latchgroup; all LATCHES in the macro called macro1 will be in a group called latchgroup INST mymac TNM = RAMS memories; all RAMS in the macro called mymac will be in a group called memories INST tester TNM = coverall; PADS, LATCHES, RAMS, and FFS will be in a group called coverall;

6.xi Timing and Constraints 81

Each element may belong to more than one group Groups elements of one group without the elements that belong to another group Syntax: TIMEGRP group1 = existing_grpA EXCEPT existing_grpB ; group1 is the new group being defined that includes existing_grpA minus common elements between existing_grpA and exisiting_grpB exisiting_grpA and existing_grpB can be any valid TNM, predefined group, or TIMEGRP attribute
6.xi Timing and Constraints 82

TIMEGRP newgrp_name = existing_grp1 existing_grp2 [existing_grp3 . . . ] ; newgrp_name is a unique new group name existing_grp are existing groups
Includes predefined groups, groups created with TNMs or the TIMEGRP attribute. Names of the existing groups must match the existing group names exactly (ie case sensitive). Order in the existing_grp list is not important

6.xi Timing and Constraints 83

Combining Groups: TIMEGRP manyffs = ffs1 ffs2 ffs3 ; TIMEGRP biggergroup=smallgroup1 mediumgroup2; Grouping by exclusion (EXCEPT): TIMEGRP group1= group2 group3 EXCEPT group4 group5; TIMEGRP selective= setB setC setD setE EXCEPT setA; TIMEGRP some_types= type2 EXCEPT type1 type2 type3;

6.xi Timing and Constraints 84

The (*) and (?) wildcard characters can be used to select elements The (*) specifies an unlimited number of characters The (?) specifies a single character Example:
*DATA? : means any name that begins with any number of characters, followed by DATA and ends with a single character. Includes: Does NOT include:
MYWRONGDATA1 MYDATA4 BASEDATAB BAD_DATA_56 MYDATASYS HIDATABASE9

6.xi Timing and Constraints 85

Higher Priority then PERIOD and OFFSET constraints Pull a paths out of lower priority constraints Give a tighter constraint to a specific path It s used to constraint the following types of paths:
False Paths Multi-cycle path
Source flop and destination flop have the same clock but the requirement is different then the period constraint.

Cross clock domain paths


Source and destination flops have different clocks.
6.xi Timing and Constraints 86

The FROM:TO constraint covers paths between groups taking clock skew into account.

ADATA CLKA

FLOP1 D Q

FLOP2 D Q

FLOP3 D Q

OUT1

BUS [7..0]
CLKB CDATA

BUFG

FLOP4 D Q

FLOP5 D Q

OUT2

= Unconstrained Data Path


BUFG

= Constrained Data Path

6.xi Timing and Constraints 87

TIMESPEC TS_F2F=FROM FFS TO FFS 30; The word TIMESPEC defines the type of specification The Spec s name must start with TS any alpha-numeric after TS is fine. Recommendation: Make the name something you will remember later. FROM --designates the origin group of the path TO --designates the destination group of the path 30; in ns by default, is the specification. You can use MHz, or even another time spec like TS_C2S/2 or TS_C2S*2 to relate the timing constraints

6.xi Timing and Constraints 88

Clock skew is used in FROM-TO constraints Clock skew = (destination clock delay - source clock delay) Positive clock skew is truncated to 0 in the timing report for setup paths
Positive clock skew is used in hold time calculations

TRACE/Timing Analyzer will automatically account for clock skew on all clocks

6.xi Timing and Constraints 89

UCF TIMESPEC command using default keywords: TIMESPEC TS_C2S=FROM FFS TO FFS 30; TIMESPEC TS_P2S=FROM PADS TO FFS 25; TIMESPEC TS_P2P=FROM PADS TO PADS 26; TIMESPEC TS_C2P=FROM FFS TO PADS 9;
TS_P2S
D Q

TS_C2S TS_C2P
D Q

OUT1 CLK

OUT2

TS_P2P
6.xi Timing and Constraints 90

Purely combinatorial delay paths start and end at I/O pads and are often left unconstrained by users Placing a FROM:TO constraint on pads-to-pads is necessary if there is a timing requirement TIMESPEC TS_P2P = FROM PADS TO PADS 15 ns;
ADATA CLKA
FLOP1 D Q FLOP2 D Q FLOP3 D Q

OUT1

BUS [7..0]
CLKB CDATA

BUFG

FLOP4 D Q

FLOP5 D Q

OUT2

= Unconstrained Data Path


BUFG

= Constrained Data Path

6.xi Timing and Constraints 91

Slack equation Source and Destination elements are PADS

Data Path Delay

6.xi Timing and Constraints 92

Use register s output net names to create groups. TIMESPEC TS_MYBUS = FROM FFS(DATA0<*>) TO FFS(MY_REG*) TS_CLK*2;

MY_REG_0

TS_MYBUS

reg0
MY_REG_1
D Q

reg1
DATA0(3:0)
D Q

MY_REG_2

CNT16

reg2
MY_REG_3
D Q

reg3

6.xi Timing and Constraints 93

Use the symbol/instance name (INST) to create groups. INST CNT16/* TNM=CNT25; INST reg* TNM=MYREG; TIMESPEC TS_MYBUS= FROM CNT25 TO MYREG TS_CLK*2;
D Q

MY_REG_0

TS_MYBUS

reg0
MY_REG_1
D Q

reg1
DATA0 CNT16
D Q

MY_REG_2

reg2
MY_REG_3
D Q

reg3

6.xi Timing and Constraints 94

Slow Exceptions are FROM-TOs that define a different delay for portion of the design. The majority of the design uses PERIOD. Preferred methodology --PAR and TRCE will execute faster.
Example 1: Using FROM-TO s only -- Not recommended method
30 ns
IN CLK
D Q D Q

60 ns
D Q

OUT

FROM flop1 TO flop2 30

FROM flop2 TO flop3 60

Example 2: Using PERIOD with a FROM-TO Slow Exception -- BEST


30 ns
IN CLK
D Q D Q

60 ns
D Q

OUT

NET CLK PERIOD=30

FROM flop2 TO flop3 60

6.xi Timing and Constraints 95

Forward trace on the clock enable to create a slow exception NET CLK_EN TNM = SLOW; NET CLK TNM = FAST; TIMESPEC TS01=PERIOD FAST 30; TIMESPEC TS02=FROM SLOW TO SLOW TS01*2;
30 ns
IN CLK
D Q D Q

60 ns

TS02
TNM=FAST TNM=SLOW

D CE

OUT TNM=FAST TNM=SLOW

TNM=FAST

CE

CLK_EN

Timespecs applying to elements with more than one TNM will be resolved with a priority system .discussed later.
6.xi Timing and Constraints 96

Constrains the path through specific logic. The TPTHRU attribute is attached to net/instance/macro
NET $3M17/ON_THE_WAY TPTHRU = ABC; TIMESPEC TS_FIFOS=FROM RAMS(FIFORAM<*>) THRU ABC TO FFS(MY_REG*) 25;
FIFORAM MYFIFO MY_REG_1
D Q D TPTHRU=abc Q

MY_REG_0

reg0

reg1
MY_REG_2
D Q

reg2

6.xi Timing and Constraints 97

You can create subgroups based on names with EXCEPT keyword Example: (Assume this design has several data busses that all start with
DATA . Use the EXCEPT command to create a group with all the pads except the data pads.)

TIMEGROUP CTRL_PADS = PADS EXCEPT (DATA*); TIMEGROUP DATAPINS = PADS(DATA*); TIMESPEC TS_IO1=FROM CTRL_PADS TO FFS 20; TIMESPEC TS_IO2=FROM FFS TO CTRL_PADS 20; TIMESPEC TS_IO3=FROM CTRL_PADS TO CTRL_PADS 30; TIMESPEC TS_IODATA=FROM DATAPINS TO FFS 15;
6.xi Timing and Constraints 98

Define groups with RISING and FALLING keywords TIMEGRP RFFS = RISING FFS; TIMEGRP FFFS = FALLING FFS; Define timing constraints TIMESPEC TS_R2F=FROM RFFS TO FFFS 30;
D Q D Q

Remember, the PERIOD constraint will automatically account for twophase clocks.
6.xi Timing and Constraints 99

Allows definition of non-synchronous points into synchronous points for multi-cycle constraints and timing analysis. Commonly used with three-state buffers. Example: NET $3M17/BLUE TPSYNC = BLUE_S ; TIMESPEC TS_1A=FROM FFS TO BLUE_S 15 ;
$3M17/BLUE
D Q

comb_b

TS_1A

RAM/ FFS/ PADS/ LATCH

6.xi Timing and Constraints 100

Allows the definition of non-synchronous elements as through points in a multi-cycle constraint


Commonly used in designs with bi-directional bus with sets of registers in different blocks.

NET DATA_BUS<*> TPTHRU = DATABUS; TIMESPEC TS_TIG=FROM FFS THRU DATABUS TO FFS 23; Control Status
Register Registers

Control_Enable

Status_Enable

DATA_BUS(7:0)

6.xi Timing and Constraints 101

Slack equation

Requirement is twice TS_clk (10ns)

Data Path Delay

6.xi Timing and Constraints 102

Define clock groups NET CLK_A TNM=A_GRP; NET CLK_B TNM=B_GRP; Define timing constraints (Recommended Way) TIMESPEC TS_CLKA=PERIOD A_GRP 20; TIMESPEC TS_CLKB=PERIOD B_GRP TS_CLKA*2; Or TIMESPEC TS_CLKA=PERIOD A_GRP 20; TIMESPEC TS_CLKB=PERIOD B_GRP 20; TIMESPEC TS_CLKA2B=FROM A_GRP TO B_GRP 20;
D Q D Q D Q

OUT1 CLK_A CLK_B


D Q

6.xi Timing and Constraints 103

CLKDV/CLKFX frequencies can be unrelated to the input clock, even when Translate relates them If there are paths between the two unrelated clock domains, they should be TIGed. UNRELATED
DATA CLK_0
D Q D Q

NET CLK_0 TNM = CLK0_GRP; CLK_FX NET CLK_FX TNM = CLKFX_GRP; TS_TIG0 = TIMESPEC FROM CLK0_GRP TO CLKFX_GRP TIG; TS_TIG1 = TIMESPEC FROM CLKFX_GRP TO CLK0_GRP TIG;

6.xi Timing and Constraints 104

2.5

5
DATA_HI
D Q

CLK 1.25ns DATA_OUT 3.75ns

DATA_OUT CLK DATA_LO


D Q

Create Period
NET CLK MAXSKEW = 2ns; NET CLK TNM = CLK_GRP; TIMESPEC "TS_CLK" = PERIOD CLK_GRP" 5 ns HIGH 50%;

Create Groups
INST DATA_OUT[*] TNM = DATA_OUT;

Create FROM-TO constraint


TIMESPEC TS_DDR_OUT = FROM CLK_GRP TO DATA_OUT 1.25;

6.xi Timing and Constraints 105

The TIG constraint removes any constraints from being applied to the specified path Paths can be specified between groups
Shows up in timing report

Nets can be specified


Does not show up in timing report

Example:
TIMESPEC TS_IGNORE = FROM GROUP1 TO GROUP2 TIG ; NET SLOW_NET TIG;

6.xi Timing and Constraints 106

{NET|PIN|INST} name TIG = group1 [ group2

];

name is the element, net, or instance name that is to be ignored group_name is an option field which ignores the net, instance, or pin in the listed group. All paths that fan forward from the net or instance will not have any timing constraints applied to them
The paths will be treated as if they don t exist

6.xi Timing and Constraints 107

Ignore a signal of the design


NET CHIP_MODE TIG;

Ignore a signal from a specific timespec


NET SLOW_SIG TIG=TS_01;

Ignore false paths between synchronous elements


TIMESPEC TS_TIG1=FROM FFS(REGA*) TO FFS(REGB*) TIG; Note: May have to use TNM or TNM_NET to create groups.

6.xi Timing and Constraints 108

Signal Skew may be constrained using the MAXSKEW constraint NET $1I3245/$SIG_6 MAXSKEW=3; I.e. specifies a maximum of 3ns difference between the source of net $1I3245/$SIG_6 and all its destinations is permissible May use to control skew of logic driven clocks (or any clock using non-global resources) Cannot constrain skew of global nets (Makes no sense as skew is fixed)

6.xi Timing and Constraints 109

Instead of the MAXSKEW constraint, there a clock skew constraint: USELOWSKEWLINES - NET $1I3245/$SIG_6 USELOWSKEWLINES; USELOWSKEWLINES will force PAR to place a net on the low-skew routing lines in the Virtex/Virtex-E/II/IIP/Spartan-II architecture If the net drives only clock loads, it will force PAR to place a net on unused BUFG resources

6.xi Timing and Constraints 110

It is legal to constrain the same paths more than once Known as a constraint conflict Multiple sources constraining the same path Multiple constraints on one net within one source Resolution of conflicting constraints from multiple sources: Lowest Priority input netlist or .ncf file .ucf file Highest Priority .pcf file (usually from MAP) Note: this priority only applies to timespecs with identical TSidentfiers (e.g. TS_03 = ) You can explicitly assign priorities within same constraint type Syntax (SOME_NORMAL_TIMESPEC) PRIORITY integer Low numbers specify high priority (1 to 2 million)
6.xi Timing and Constraints 111

When two constraints constrain the same path, the path will be analyzed by the constraint with higher precedence
TIMESPEC "TS_clk" = PERIOD "clk" 7 ns; TIMESPEC "TS_TIG" = FROM "neta_grp" TO FFS TIG;

A FROM-TO has a higher precedence than a PERIOD constraint Two identical constraint types
Constraint later in .PCF takes all paths

6.xi Timing and Constraints 112

Within a particular source:


Highest Priority Timing ignores (TIG) FROM-THRU-TO specs Source and destination defined by user Source or destination defined by user Source and destination are pre-defined groups FROM-TO specs Source and destination defined by user Source or destination defined by user Source and destination are pre-defined groups OFFSET specs Specific data IOB Time group of data IOBs All data IOBs PERIOD specs

Lowest Priority
6.xi Timing and Constraints 113

OFFSETs
global
OFFSET = in 5 ns before clk;

specific
TIMEGRP my_pads OFFSET = in 5 ns before clk;

PERIOD
With DCM
TIMESPEC TS_myperiod = PERIOD clk_grp 5 ns HIGH 50%;

Without DCM (relate clocks)


TIMESPEC TS_myperiod = PERIOD clk_grp 5 ns HIGH 50%; TIMESPEC TS_my2period = PERIOD clk_grp TS_myperiod*1 HIGH 50%;

FROM:TO
TIMESPEC TS_myperiod = FROM grp1 to grp2 TIG;
6.xi Timing and Constraints 114

The tools will allow the user to prorate timing delay characteristics based on known environmental parameters. This is available only in the Virtex family. Voltage: Allows the user to specify the operating voltage. UCF syntax: VOLTAGE = value [units] Temperature: Allows the user to specify the operating temperature. UCF syntax: TEMPERATURE = value [C|F|K] Celsius is the default.

6.xi Timing and Constraints 115

Using LOC, BLKNM, and other physical constraints

LOC constraint used to locate/assign pins: From a Schematic attach the attribute LOC=P12 to the pins you wish to lock down I/O constraint based on net name in the .UCF file NET IOBLOCK/DATA0_IN LOC=P12; I/O constraint based on the instance name in the .UCF file INST IOBLOCK/DATA_IN_PAD LOC=P12; PAR produces a .PAD file. The .PAD file can be used to verify the assigned pins. Constraints Editor, Pin-out Area Constraints Editor (PACE), and Floorplanner can be used to locate/assign pins.

6.xi Timing and Constraints 117

LOC constraint used to locate: BUFTs, FFs, MAPs, CLBs, PADs, WANDs, decoders, global buffer single components (e.g. CLBs) INST U45 LOC=CLB_R1C5; ranges of components (but not IOs) INST U46 LOC=CLB_R2C2:CLB_R4C6; multiple sites for single component INST U50 LOC=CLB_R1C1, CLB_R2C1; I/O constraint based on net name NET IOBLOCK/DATA0_IN LOC=P12;
6.xi Timing and Constraints 118

Area groups are used to specify a group of logical blocks that are packed into separate physical areas by the mapper - INST <logical_block> AREA_GROUP = <group_name>; For the 4KX architecture, TBUFs and CLBs are supported in an area group. For Virtex E/II/IIP/Spartan-II architecture, both TBUFs and SLICES are supported. If the AREA_GROUP is attached to a hierarchical block, all logical blocks within that block are assigned to the group. If a symbol contains a LOC and is part of an area group, the LOC constraint will take priority and the symbol will be removed from the area group. Timegrps can be used to create area groups, more detail to follow
6.xi Timing and Constraints 119

After defining the area group, the range of the group, and compression of the group into a percentage of the total CLBs can be defined - AREA_GROUP <group_name> RANGE = <range>; - AREA_GROUP <group_name> COMPRESSION = <percent>; - The <range> defines the physical area for the area group. - If the logic in the group exceeds the range, map will error. - The <percent> defines the percentage of CLBs within the particular <range> to compress the logic of the area group into. Area groups with a compression factor are not affected by the -c option in map Area groups without a compression factor are affected by the -c option in map

6.xi Timing and Constraints 120

INST state_machine_X AREA_GROUP=group1; AREA_GROUP group1 RANGE=CLB_R1C1:CLB_R10C10; AREA_GROUP group1 RANGE=TBUF_R1C0:TBUF_R10C10; AREA_GROUP group1 COMPRESSION=0; - Assign all logical blocks in state_machine_X to the area group group1 - Place CLB logic in the physical area between CLB 1,1 and CLB 10, 10 - Place TBUFs in the physical area between TBUF 1,0 and TBUF 10, 10 - Do not compress unrelated logic within this area group. Note that since compression is defined, ungrouped logic will not be combined with logic in group1

6.xi Timing and Constraints 121

a variety of mechanisms for defining and manipulating the members of timing groups for the definition of area groups. TIMEGRP timing-group-name AREA_GROUP = areagroup-name ;
Where timing-group-name is the name of a previously-defined timing group Where area-group-name is the name of a new area group to be defined from the timing group contents.

During NGDBUILD, the area group definition will be expanded into explicit AREA_GROUP properties on all members of the named timing group. It can be referenced in RANGE and other constraints in the usual fashion.
6.xi Timing and Constraints 122

PROHIBIT Disallows the use of these sites within PAR: CLBs, PADs, BUFTs, decoders, global buffer, function blocks/macrocells single components (e.g. CLBs) CONFIG PROHIBIT=CLB_R1C5; ranges of components (but not IOs) CONFIG PROHIBIT=CLB_R2C2:CLB_R4C6; I/O constraint based on net name CONFIG PROHIBIT=P12;
Note: CONFIG PROHIBIT has specific limits depending upon the device. Please reference the Libraries Guide for these limits.

6.xi Timing and Constraints 123

Force logic into the same CLB/SLICE. Sometimes MAP doesn t make the best decisions. This allows the user to map logic together. Syntax INST state_reg_1 BLKNM=STATE1; INST state_reg_2 BLKNM=STATE1; INST my_logic BLKNM=STATE1; This will force my_logic, state_reg_1, state_reg_2, and into the same CLB/SLICE ( STATE1 ).

Note: The remaining resources are still up for grabs by MAP (in this case, one of the FG s is still available).

6.xi Timing and Constraints 124

Physical implementation may be controlled in the UCF file, such as: FAST : Set Faster IO Slew rate e.g. INST $1I87/OBUF FAST PART e.g. BUFG e.g. INIT e.g. : Define Part-type to be used CONFIG PART=4005E-PQ160C-5; : Force signal to onto global net (CPLD only) INST clkgen/fastclk BUFG; : Define initial RAM/ROM Contents (primitives only) INST $1I3245/ROM2 INIT = 5555;

Such Physical constraints may be Architecture dependent

6.xi Timing and Constraints 125

fastpaths option
Breaks up the timing report into sections for setup and hold for all constraints Allows user look at data paths to see which paths almost had a hold violation

Offset VALID keyword


Allows user to specify the duration of the data window

Clock Uncertainty
6.xi Timing and Constraints 126

VALID specifies the duration of the incoming data window If not specified, it defaults to the OFFEST time Valid must be specified for hold checking VALID must be larger or equal to the offset time Example:
OFFSET = IN 5 ns VALID 9 ns BEFORE ClkExt
6.xi Timing and Constraints 127

Clock uncertainty used to increase timing accuracy by accounting for system and board level clock jitter Includes:
Clock input jitter (New PERIOD Constraint Keyword) System Jitter (New Constraint) DCM Jitter (Automatically calculated for Whitney and beyond) DCM Phase Error (Automatically calculated for Whitney and beyond)

Used in internal reg/reg and external setup/hold calculations Uncertainty reported for each path covered by OFFSET constraint Uncertainty reported even if value is zero Uncertainty components are not reported separately
6.xi Timing and Constraints 128

Constraint Example:
TIMESPEC "TS_SysClk" = PERIOD "SysClk" 20 ns HIGH 50 % INPUT_JITTER 100 ps;

What s wrong with this report ? Nothing !


Clock Uncertainty = 0.071ns but specified as 100 ps INPUT_JITTER Register to register clock uncertainty is a complex equation of jitter components
6.xi Timing and Constraints 129

UCF Constraint Example:


System_Jitter = 150 ps;

What s wrong with this report ? Nothing !


Clock Uncertainty reported as 0.075 ns, Jitter was specified as 150 ps I/O clock uncertainty is also a complex equation of jitter components
6.xi Timing and Constraints 130

Most generic timing constraints for fastest PAR runtime


NET CLK1 PERIOD = 40; OFFSET = OUT 13 AFTER CLK1; TIMESPEC TS01 = FROM PADS TO PADS 40;

6.xi Timing and Constraints 132

Clocks NET CLK TNM=CLK; NET CLK2 TNM=CLK2; TIMESPEC TS_CLK01=PERIOD CLK 40; TIMESPEC TS_CLK02=PERIOD CLK2 TS_CLK01*1.25; Ignore paths between 2 async clocks TIMESPEC TS_TIG1=FROM CLK TO CLK2 TIG; TIMESPEC TS_TIG2=FROM CLK2 TO CLK TIG; Generic path to outputs TIMESPEC TS_IO1=FROM FFS TO PADS 20; Two cycle path to slow outputs TIMESPEC TS_IO2=FROM FFS TO PADS(SLOW*) TS_IO1*2;

6.xi Timing and Constraints 133

Offset for late input signal NET LATE_INPUT OFFSET=IN 30 AFTER CLK; Ignore static input signal NET CHIP_MODE TIG; Static control registers INST CONTROL_BLOCK/CTRL_REG* TNM=CTRL_REG; TIMESPEC TS_CLK03 = FROM CTRL_REG TO FFS=TS_CLK01*2; Fast OBUF attached to component INST RAM_CS FAST; Prohibit Pins CONFIG PROHIBIT = P6;

6.xi Timing and Constraints 134

All Constraints accessible from single constraints file All Xilinx features may be constrained from constraints file Full TimeSpec support provided from Constraints file Improved TimeSpec capability provided The Constraints Guide has a full list of all supported constraints and examples of syntax at
http://toolbox.xilinx.com/docsan/xilinx5/data/docs/cgd/cgd0001_1.html

6.xi Timing and Constraints 135

Developmental System Reference Guide at:


http://toolbox.xilinx.com/docsan/xilinx5/data/docs/dev/dev0001_1.html

Constraints Guide at:


http://toolbox.xilinx.com/docsan/xilinx5/data/docs/cgd/cgd0001_1.html

Libraries Guide at:


http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0001_1.html

http://support.xilinx.com

6.xi Timing and Constraints 136

How to Properly Constrain a Design Using Timing Tools

Global constraints
Period
Use a period constraint for your input clocks. Let ngdbuild create constraints for clocks generated by a DCM Relate clocks if possible

Offsets

Use specific constraints


FROM:TO
Specific paths Multi-cycle paths Cross clock domain paths

Offsets
Specific paths

6.xi Timing and Constraints 138

(PERIOD)
Period constraint should account for the following
System frequency Clock jitter % for other variations
PERIOD = (System frequency clock jitter - % for variation)

References
Solution 13645 Tech Exclusive
"Jitter" http://support.xilinx.com/support/techxclusives/jitter-techX10.htm

Does Your Design Have Enough Slack?"

http://support.xilinx.com/support/techxclusives/slack-techX21.htm

On line presentation
6.xi Timing and Constraints 139

(OFFSET)
OFFSET IN should account for
Upstream trace delay Upstream device clock to out System frequency
OFFSET IN = (System frequency) Trace) (Upstream clock-to-out +

OFFSET OUT should account for


Downstream trace delay Downstream device setup System frequency
OFFSET OUT =(System frequency) Trace)
6.xi Timing and Constraints 140

(Downstream setup +

Re-design the failing section


Add pipeline registers Use one-hot state machines Use CASE statements instead of if/else trees

Change synthesis constraints to get better results

6.xi Timing and Constraints 141

Designs using the DCM


Follow the timing in the Source Sync Datasheet

Designs using local clocking


Use PERIOD, OFFSET IN for inputs
Manually calculate hold times with pro-rated number on data Manually adjust setup times with pro-rated number on clock

Use OFFSET OUT if clock comes from an external pin Use FROM-TO on data path, MAXSKEW on clock net if clock comes from an internal source

6.xi Timing and Constraints 142

Designers design with Asynchronous Reset, then want to constrain it synchronously By default, the async reset timing path is turned off There are two async reset paths
The async path through the register (Trq) The async reset recovery time (Trck/Tiorcko)

Typically, customers want the async turn off time


Setup time for FF to come out of reset (Trck)

6.xi Timing and Constraints 143

CLK RESET FF OUTPUT RESET

Trck

FF INPUT VALUE

Use PCF constraint after SCHEMATIC END to enable any delay value
SCHEMATIC END; ENABLE=Trck;

6.xi Timing and Constraints 144

CLK0 = 100 Mhz CLK2X = 200 Mhz

Frequency = ???

Which clock wins?


Last period constraint in the PCF

Use the PRIORITY keyword


NET CLK0 TNM_NET = CLK0_GRP; TIMESPEC "TS_CLK0" = PERIOD CLK0_GRP" 10 ns; NET CLK2X TNM_NET = CLK2X_GRP; TIMESPEC "TS_CLK2X" = PERIOD CLK2X_GRP" TS_CLK0/2 PRIORITY 1; Note: This does not work in 5.1i. It is fixed in 5.1i SP1

6.xi Timing and Constraints 145

When all the known timing constraints are entered, do a sanity check Create a timing report with unconstrained paths
Command line: -u n where n is the number of paths Timing Analyzer: Select Report Unconstrained paths

Unconstrained paths are grouped by clock making it easy to see the paths

6.xi Timing and Constraints 146

Paths that end at a synchronous element clocked by clk20g are grouped together regardless of clock relationships Period, OFFSET IN, OFFSET OUT for clk30g
Note: This may greatly increase runtime

6.xi Timing and Constraints 147

Suggestions on how to constrain a path Available on all unconstrained paths

6.xi Timing and Constraints 148

All paths are constrained


Check for unconstrained paths in Timing Analyzer or trce

All paths meet timing


Positive slack

Skew analysis
Perform hold time checks for all logic Run -fastpaths to see which paths almost had a hold violation
6.xi Timing and Constraints 149

Design is correctly constrained but has timing errors What tools are available to help fix the errors?
Timing Analyzer Constraints Improvement Wizard Cross Probing to the Floorplanner
Select the design.ncd in Timing Analyzer to start Floorplanner Or load the same design.ncd in Timing Analyzer and Floorplanner

Cross Probing to the Synthesis


See XAPP406 (http://support.xilinx.com/xapp/xapp406.pdf)

Timing Driven Pack in MAP

6.xi Timing and Constraints 150

Generate a timing report


Analyze -> Against Timing Constraints

Display an existing timing report


File -> Open

Highlights failing constraints in red


Is this a valid path? Is this a valid requirement for source and destination clocks? Are Logic Levels correct or can they be reduced?

Shows timing paths Sorts timing paths


To determine unique timing failures Sort by Source or Destination Name Filtering in or out paths of interest Remove paths that do not matter
6.xi Timing and Constraints 151

6.xi Timing and Constraints 152

Shows timing paths in the Floorplanner Need to turn on net highlighting in the Floorplanner
Edit -> Preferences -> Ratnest Select Display nets connected to selected logic

Open the design in the Floorplanner Click on Hyperlinks in the Timing Report to highlight in the Floorplanner

6.xi Timing and Constraints 153

Clicking on the Data Path will highlight the path in the Floorplanner

6.xi Timing and Constraints 154

Timing constraints directly influence packing decisions


(Packing is the operation of combining LUTs, FFs, etc. to form slices)

Placer generates intermediate placement


Path slack is calculated Slack used to determine optimized packing configurations

6.xi Timing and Constraints 155

Non-Timing Driven Path

6.xi Timing and Constraints 156

Timing Driven Pack Typical Pack

6.xi Timing and Constraints 157

User timing constraints are recommended


Auto timespec capability will be used in lieu of user generated constraints

Use timing switch on map command line Available in ProjNav from map properties dialog after enabling Advanced Property Display Level

6.xi Timing and Constraints 158

Tradeoffs:
Runtime is always negatively impacted
Can grow by over 2-3x

Memory usage increases Be careful of trying to chase performance via command line settings. Analyze first!

Benefits:
Benchmark data for typical designs shows overall 5-8% improvement in QOR A few very large, very tightly packed designs show >10-15% improvement in performance

6.xi Timing and Constraints 159

Bad Packing
Two LUTs that are packed together and nets go to different locations

Bad Placement
Logic placed far away from each other

Poor IO Timing
FF in IOB to meet IO timing or in CLB to meet internal timing

High Fanout Net


Net going to different places on the chip

Too many levels of logic


Too much logic delay to meet timing

6.xi Timing and Constraints 160

Most of the path in the same area with one part in a different area Example
A blue LUT is packed with a red LUT The blue LUT needs to be in the middle of the device, the red LUT needs to be at the bottom Creates a placement problem

6.xi Timing and Constraints 161

Use map -timing to get a better packing based on timing Use AREA GROUPS on different parts of design to prevent packing
Do not need range constraint to affect packing INST modulea AREA_GROUP = modulea; INST moduleb AREA_GROUP = moduleb;
Note: AREA_GROUP will be discussed in the Physical Constraint section

6.xi Timing and Constraints 162

Logic is scattered through out the design Example:


The blue LUTs are not in a tight group Net lengths are always multiple CLBs long

6.xi Timing and Constraints 163

Use a higher PAR effort level Use AREA GROUPS to locate different parts of the design
Use PACE or the Floorplanner to create an AREA GROUP floorplan

6.xi Timing and Constraints 164

The register is located in the CLB array, not in the IOB Example:
The blue FF is in the CLB array, not packed in the IOB

6.xi Timing and Constraints 165

Place the FF in the IOB


Use map switch map -pr i|o|b (input, output or both) Use IOB constraint INST data_r IOB=TRUE

6.xi Timing and Constraints 166

A single net goes to different parts of the design Example:


The blue FF drives logic in the red logic and the green logic

6.xi Timing and Constraints 167

Duplicate the source of the net in the source code Make sure the new net goes to logic that is placed together

6.xi Timing and Constraints 168

A path goes through too many logic levels Example


The yellow components are located near each other. Nets have similar lengths

6.xi Timing and Constraints 169

How to Properly Constrain a Modular Design Using Timing Tools

Constraints to be familiar with OFFSETs


Constrain input and output paths (Pad to Register, Resister to Pad) OFFSET constraints tell the tool what the external data and clock relationship is.

PERIOD
Constrains register to register paths

FROM:TO
Constrain more specific paths like multi-cycle, cross clock domain, and false paths.

6.xi Timing and Constraints 171

In a typical non modular design the source and destination of all data starts or ends at a real components such as a PADs, FFs, RAMs, Multipliers . In a Modular design the source and destination of data entering or leaving a module can be a Pseudo source or a Pseudo load. Any path that starts or ends at a Pseudo driver or Pseudo load will be left unconstrained
6.xi Timing and Constraints 172

Constrained Paths (OFFSET IN)


OFFSET IN
Top level OFFSET IN constraint still covers PAD-to-FLOP paths and the clock paths in a module. The source of data has to be a PAD and not a Pseudo Driver.

FLOP IOPAD

FLOP

Clock PAD

6.xi Timing and Constraints 173

Constrained Paths (OFFSET OUT)


OFFSET OUT
Top level OFFSET OUT constraint still covers Flop-To-PAD paths and the clock path in a module Destination of data has to be a PAD and not a Pseudo Load.
Module FLOP FLOP IOPAD

Clock PAD

6.xi Timing and Constraints 174

Constrained Paths
OFFSETs
If the source of data entering a module is a Pseudo driver then that input data path will not be covered by your top level offset constraint If the destination of data leaving a module is a Pseudo load then that output data path will not be covered by your top level offset constraint
Pseudo Driver
FLOP FLOP

Pseudo Load

6.xi Timing and Constraints 175

Constrained Paths
Asynchronous Paths
Top level PAD-to-PAD constraints still cover paths that start at a PAD and end at a PAD Asynchronous Paths that start or end at a Pseudo driver or Pseudo load will not be constrained by the top level PAD-to-PAD constraint.
IOPAD IOPAD

Pseudo Driver

Pseudo Load

Pseudo Driver

6.xi Timing and Constraints 176

Constrained Paths
Period
Register-to-register paths are covered by the top level period constraint Pseudo Driver to System flops are left unconstrained System Flops to Pseudo Loads are left unconstrained
Pseudo Driver
FLOP FLOP

Pseudo Load

6.xi Timing and Constraints 177

6.xi Timing and Constraints 178

Synchronous paths that start or stop at a PIN of a module be constrained with an OFFSET constraint
TIMEGRP pseudo driver OFFSET = IN 5 ns after clk;

Asynchronous paths that start or stop at a PIN of a module can be constrained with an FROM:TO constraint.
TIMESPEC TS_asynch_path = FROM grp1 TO grp2;

6.xi Timing and Constraints 179

To identify a specific pin on the module for reference in an OFFSET of FROM:TO constraint use a TPSYNC constraint.
NET module_port TPSYNC = synch_point ; TIMEGRP synch_point OFFSET = IN 5n before clk
Module

Pseudo Driver
Modular_port

FLOP

TYPSYNC point

6.xi Timing and Constraints 180

Module

Pseudo Driver
IN_port

FLOP

FLOP
OUT_port

Pseudo Load

Clock PAD

OFFSET IN (Will constrain the green path)


NET IN_port TPSYNC = pseudo_in_grp ; TIMEGRP pseudo_in_grp OFFSET = IN 2 ns before clk;

OFFSET OUT (Will constrain the red path)


NET OUT_port TPSYNC = pseudo_out_grp ; TIMEGRP pseudo_out_grp OFFSET = out 2 ns after clk;
6.xi Timing and Constraints 181

Pseudo Driver
IN_port1

Module

Pseudo Load
OUT_port

Pseudo Driver
IN_port2

FROM:TO (will constrain the red path)


NET IN_port1 TPSYNC = asynch_in_grp ; NET IN_port2 TPSYNC = asynch_in_grp ; NET OUT_port TPSYNCH = asynch_out_grp; TIMESPEC TS_asynch_path = FROM asynch_in_grp TO asynch_out_grp ;

6.xi Timing and Constraints 182

Launch Constraints Editor (CE) and load the active module ngd and ucf file. CE will show all the port of the active module in the ports tab
Ports on the module that are connect to PADs within the module will have a pin location that was defined in the initial budgeting Ports on the module that are connected to a Pseudo driver or a Pseudo load will be marked as N/A in the location column.
6.xi Timing and Constraints 183

6.xi Timing and Constraints 184

Other information for Constraints

6.xi Timing and Constraints 185

.
1) create_clock -period 125 -waveform {0 62.5} find(port,"CLK") 2) set_input_delay 125 -clock "CLK" find(port,"NOTRST") 3) set_output_delay 125 -clock "CLK" find(port,"GAG<0>") .dc file 1) TIMESPEC TS_CLK = PERIOD : "CLK": 125 : HIGH : 62.5; 2) NET "CLK" TNM = "CLK"; 3) NET "NOTRST" OFFSET = IN : 125 : AFTER : "CLK"; .ncf file 4) NET "GAG<0>" OFFSET = OUT : 125 : BEFORE : "CLK";

6.xi Timing and Constraints 186

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