Академический Документы
Профессиональный Документы
Культура Документы
ISSUES
Finite Gain & GBW of Op-amp Quantizer Non-linearity RC-time constant variations Excess Loop Delay Clock Jitter
Feedback Coefficients
Ksig K1 K2 K3 K51 K61 K71 K4 K52 K62 K72 K82 K92 = 1/4 =1 = 3/2 =1 = -1 =2 = -4/3 =1 = 1/3 = -1/2 = 7/24 =1 = -1/4
Other Parameters
MSA SNR = 0.89 V = 133 dB
CIRCUIT LEVEL implementation will be done in this semester in 130nm technology, while targeting TAPE-OUT.
References
Understanding Delta-Sigma Data Converters Richard Schreier & Gabor C. Temes. Delta-Sigma Data Converters, Theory, Design and Simulation Richard Schreier, Gabor C. Temes & Steven R. Norsworthy. Delta-Sigma Toolbox Richard Schreier. A Cascaded Continuous Time Sigma-Delta Modulator with 80 dB Dynamic Range Maurits Ortmanns, Markus Kuderer, Yiannos Manoli & Friedel Gerfers. A Case Study on a 2-1-1 Cascaded Continuous-Time Sigma-Delta Modulator Maurits Ortmanns, Friedel Gerfers, & Yiannos Manoli. Optimal Parameters for Delta-Sigma Modulator Topologies Augusto Marques, Vincenzo Peluso, Michel S. Steyaert, & Willy M. Sansen.
References
Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta Sigma Modulators Prabu Sankar and Shanthi Pavan. Excess Loop Delay in Continuous-Time DeltaSigma Modulators James A. Cherry and W. Martin Snelgrove. A Power Optimized Continuous-Time ADC for Audio Applications Shanthi Pavan, Nagendra Krishnapura, Ramalingam Pandarinathan, and Prabu Sankar Theory, Practice, and Fundamental Performance Limits of High-Speed Data Conversion Using Continuous-Time Delta-Sigma Modulators James A. Cherry Compensation of the Influence of Finite GBW on CT-SDM Maurits Ortmanns, Friedel Gerjers, Eannos Manoli A Clock Jitter Insensitive Multi-bit DAC Architecture for High-Performance Low-Power CTSDM Gerfers, M . Ortmanns, P Schmitz, Z Manoli & K. M. Soh
Thank You