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Courses In Electrical Engineering

ENSET BAMBILI FIELD PROGRAMMABLE DEVICES AND APPLICATIONS

By Jean-Paul NGOUNE DIPET I (Electrotechnics), DIPET II (Electrotechnics) DEA (Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.

FPDs and applications_ENSET Bambili_Jean-Paul NGOUNE.

Chapter Two
FINITE STATE MACHINES
2.0 Specific objectives: At the end of this chapter, the student will be able to: Define Finite State Machine, Know the structure and the specificities of different types of FSM; Know how to design a Finite State Machine.

2.1 Introduction: All programmable logic designs can be specified in Boolean form. However, some designs are easier to conceptualise and implement using non-Boolean models. The State Machine is one of such model. A Finite State Machine (FSM) is a type of sequential circuit that is designed to sequence through specific patterns of finite states in a predetermined sequential manner. In fact any circuit with memory (sequential) is a Finite State Machine. FSMs are basic tools for hardware design; they represent the transformation between inputs and outputs for sequential systems. There are two types of FSM, Mealy and Moore. The aim of this chapter is to introduce the concept of Finite State Machine and to know how to design it.

2.2 A simple Finite State Machine: The counter. The basic element for the design of a counter is a flip-flop. Below is presented the symbol and the truth for a J-K flip-flop.
J Clock /Q Positive edge triggered J-K flip-flop Q

FPDs and applications_ENSET Bambili_Jean-Paul NGOUNE.

Clock

J 0 0 0 0 1 1 1 1

K 0 0 1 1 0 0 1 1

Qn 0 1 0 1 0 1 0 1

Qn+1 0 1 0 0 1 1 1 0

Truth table for a J-K flip-flop. This truth table can be summarised into a transitioning table that gives the behaviour of the present (Qn) and the future (Qn+1) state of the flip-flop output for any input combination.

Qn 0 0 1 1

Qn+1 0 1 0 1

J 0 1 x x

K x x 1 0

Transitioning table for a J-K flip-flop Let us realise a modulo-5 synchronous counter using J-K flip-flops. The following procedure is to be followed: Identify all the finite states of the counter; Determine the number of flip-flops to be used to represent all the states; Establish the table of next states; Sort the equations of the inputs of the flip-flops using k-map; Draw the logic diagram.

FPDs and applications_ENSET Bambili_Jean-Paul NGOUNE.

Solution 1. A modulo-5 counter is used to count from 0 to 4; that is 0,1,2,3 and 4. Then we have 5 finite states. 2. We know that a state vector with a length of n bits (number of flip-flops) has 2n different states. So 5 = 2n, hence 2<n<3 (22<5<23). We deduce that at least 3 flip-flops will be necessary to represent all the states of the counter. 3. Table of next states (Truth table). We will use the transitioning table of the J-k flip-flop in order to determine the behaviour of the inputs J and K of the three flip-flops when the counter is transitioning from one state to another.

states 0 1 2 3 5

Q2 0 0 0 0 1

Q1 0 0 1 1 0

Q0 0 1 0 1 0

Q2+ 0 0 0 1 0

Q1+ 0 1 1 0 0

Q0+ 1 0 1 0 0

J2 0 0 0 1 x

K2 x x x x 1

J1 0 1 x x 0

K1 x x 0 1 x

J0 1 x 1 x 0

K0 x 1 x 1 x

Current state

Next state

Inputs

4. Let us now sort the equations of the inputs using k-map:


Jo qo q1q2 Ko

0 1

00 1 x

01 0 x

11 x x

10 1 x

qo q1q2

0 1

00 x 1

01 x x K0 1 01 x x Q0

11 x x

10 x 1

J0
J1 qo q1q2

Q2
K1

0 1

00 0 1 J1

01 0 x Q0

11 x x

10 x x

qo q1q2

0 1

00 x x K1

11 x x

10 0 1

J2 qo q1q2

K2

0 1

00 0 0 J2

01 x x Q0Q1

11 x x

10 0 1

qo q1q2

0 1

00 x x

01 1 x

11 x x

10 x x

K2

1
4

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5. We can then draw the logic diagram of the synchronous counter modulo 5.
Vcc

Q2

J2
Vcc

Q1

J1

Q0

J0

Q'2

K2

Q'1

K1

Q'0

K0

Clock

Q2

Q1 These are also the outputs

Q0

Figure 2.1: Logic diagram of a synchronous counter modulo 5.

Exercise 2.1: Design a synchronous counter modulo 7 using J-K flip-flops.

2.3 structure of Finite State Machines: As we said before, there are two types of FSM, Mealy and Moore. The Moore FSM has outputs that are function of current state only. The Mealy FSM has outputs that are function of the current state and primary inputs.

Inputs Next State Logic (Combinational) Next state Currrent state register (Sequential)

Current state

Output Logic (Combinational)

Outputs

Clock

Figure 2.2: Basic structure of a Moore FSM.


FPDs and applications_ENSET Bambili_Jean-Paul NGOUNE.

Inputs Next State Logic (Combinational) Next state Currrent state register (Sequential)

Current state

Output Logic (Combinational)

Outputs

Clock

Figure 2.3: Basic structure of a Mealy FSM.

A Finite State Machine consists of three main parts: Sequential Current State Register: The register, a set of n-bit flip-flops (state vector flip-flops) clocked by a single clock signal is used to hold the state vector (current state or simply state) of the FSM. A state vector with a length of n-bit has possible binary patterns, known as state encoding; that

is, an FSM whose state vector is made up of n flip-flops can have up to states. Often, not all the patterns are needed, so the unused ones should

be designed not to occur during normal operation (this was the case for the modulo-five synchronous counter designed above). Combinational Next State Logic: An FSM can only be in one state at a given time, and each active transition of the clock causes it to change from its current state to the next state, as defined by the state logic. The next state is a function of the FSMs inputs and its current state. Combinational Output Logic: Outputs are normally a function of the current state and possibly the FSMs primary inputs (in the case of a Mealy FSM).

2.4 Moore and Mealy Machine diagrams For any given state, there is a finite number of possible next states. On each clock cycle, the state machine branches to the next state. One of the possible next states becomes the new present state, depending on the inputs present on the clock cycle. The following diagram shows all the possibilities when moving from present to next state

FPDs and applications_ENSET Bambili_Jean-Paul NGOUNE.

State 4

State 5

State 6

State 7

Figure 2.4: Possibilities of present and next states

On a well-drawn state diagram, all possible transitions will be visible, including loops back to the same state. From this diagram it can be deduced that if the present state is State 5, then the previous state was either State 4 or 5 and the next state must be either 5, 6, or 7.

2.4.1 Moore machine diagram:

The Moore State Machine output is shown inside the state bubble, because the output remains the same as long as the state machine remains in that state. The output can be arbitrarily complex but must be the same every time the machine enters that state.

FPDs and applications_ENSET Bambili_Jean-Paul NGOUNE.

State 1
q,r

a,b
Input condition that must exist in order to execute these transitions from State 1

i,j
Output condition that results from being in a particular present state

State 2
x,y Figure 2.5: Moore machine diagram

2.4.2 Mealy Machine diagram: The Mealy State Machine generates outputs based on: The Present State, and The Inputs.

So, it is capable of generating many different patterns of output signals for the same state, depending on the inputs present on the clock cycle. Outputs are shown on transitions since they are determined in the same way as is the next state.

State 1

a,b q,r

i,j x,y

Input condition that must exist in order to execute these transitions from State 1

Output condition that results from being in a particular present state

State 2
Figure 2.6 : Mealy machine diagram

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The Moore machine describes outputs as concurrent statements depending on state only.

transition condition 1 state 1 / output 1 transition condition 2


The Mealy machine describes outputs as concurrent statements depending on state and inputs.

state 2 / output 2

transition condition 1 / output 1 state 1 transition condition 2 / output 2


2.5 How to design a Finite State Machine. Here is an example of designing of a Finite State Machine worked out step by step from start to finish.

state 2

Step One: Describe the machine in words. In this example, we will be designing a controller for an elevator. The elevator can be at one of two floors: Ground or First. There is one button that controls the elevator, and it has two values: Up and Down. Also, there are two lights in the elevator that indicate the current floor: Red for Ground and Green for first. At each time step, the
FPDs and applications_ENSET Bambili_Jean-Paul NGOUNE.

controller checks the current floor and current input, changes floors and lights in the obvious way. Step Two: Draw the FSM diagram.

The diagram is that of a Moore FSM. In this diagram, the bubbles represent the states, and the arrows represent state transitions. The arrow labels indicate the input value corresponding to the transition. For instance, when the elevator is in the Ground state, and the Input is Up, the next state is First. The information in the brackets indicates the output values for the lights in each state.

Step Three: Select the numbers to represent states and values. Before converting the above FSM diagram to a circuit, we need to represent every value in our example as a binary number. Here are some convenient numbers to use. Ground = 0 First = 1 Down = 0 Up = 1 Off = 0 On = 1

So here is the FSM diagram with the words replaced by numbers

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Step Four: Write the truth table. From the diagram, it is easy to read off the correct truth table.

Current state Input Next State Red Green 0 0 1 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 1 1

Step Five: Draw a big picture view of the circuit: Here is the Finite State Machine Circuit, with many details missing. The variable names have been abbreviated. The dashed boxes indicate the parts (let us call them sub-circuits) that we still need to design.

All FSM circuits will have a form similar to this. Our example has two states, and so we need only one D flip-flop (or J-K). An FSM with more states would need more flip-flops ( m flops). Our example has one input (labelled I in the figure), but in general, there may be many inputs or none at all. Also, an FSM may not have any output, in which case the output sub-circuit would be omitted. In our example, the output sub-circuit has two outputs, R and G. To make things simpler, let us break this into further sub-circuits: a sub-circuit that computes R, and a sub-circuit that computes G. This is shown below:
2 n , m being the number of finite states and n the number of flip-

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After making this change, every dashed box (sub-circuits that we need to design) has exactly one output. This is the easiest form to work with.

Step 6: Find Boolean expressions For each sub-circuit that we need to design (NS, R and G), we will write a Boolean expression that expresses its output as function of its inputs. We derive these expressions from the truth table we wrote in step 4.
NS R G CS .I CS .I CS .I CS .I CS .I CS .I I CS CS I CS I I I CS CS CS I

Step 7: Draw the rest of the circuit. The only thing left to do is to draw the sub-circuits represented by our Boolean expressions.

Naturally, a more complicated example will require more gates, but the same method will be applied.

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2.6. Conclusion. Finite State Machine concept have been presented and discussed. Moore and Mealy FSM have been characterised and their respective machine diagrams presented. We have also presented the procedure to follow for the designing of a Finite State Machine. The focus of the next chapter will be the designing of Finite State Machines using VHDL (Very high speed Hardware Description Language).

REVIEW QUESTIONS:
1. Design a modulo-8 synchronous counter us J-K flip-flops. Design a modulo-8 asynchronous counter using J-K flip-flops. Compare the two counters.

2. Conceive a machine that is capable of detecting the sequence 0-1-1-0 on its single input (x). When the sequence occurs, the machine should output a 1 at its unique output (y). A chronogram describing the functioning of the machine is given below. Notice that in the sequence 0-1-1-0-1-1-0, the sequence occurs twice! Use a Moore machine for your conception.

3. Conceive a machine that sales Poly-cola drinks. A bottle of Poly-cola costs 100F. The Machine accepts coins of 25F and 100F. When the machine receives exactly 100F, it ejects a bottle of Poly-cola. If the machine receives more than 100F, it ejects the money and returns to its initial state. There are two inputs: 25F and 100F. Those inputs pulse to 1 at each clock cycle in order to indicate that the money has been received. There are two outputs: eject a bottle and eject the money; when they receive a pulse of 1 during a clock cycle, they eject a bottle or money respectively.

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25F 100F CLK

Bottle Money

a) Conceive this machine as a Moore machine; b) Conceive this machine as a Mealy machine; c) Which of the two machines costs less? (in terms of number of flip-flops to be used).

References: 1. Actel HDL coding: Style guide, Actel Corporation, Mountain view, CA 94043. 2. Sundar Rajan, Essential VHDL: RTL synthesis. 3. Steve Golson, State Machine Design Techniques for Verilog and VHDL

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ABOUT THE AUTHOR

NGOUNE Jean-Paul was born in Forek-Dschang, Republic of Cameroon in 1984. He is a holder of a Master Degree in electrical engineering, obtained in 2010 in the Doctorate School of the University of Douala. He is also a holder of a DIPET II and a DIPET I respectively obtained in 2009 and 2007 in the Advance Teaching School for Technical Education (ENSET de Douala). He is currently a permanent teacher of Electrical Engineering at the Government Technical High School of Kumbo, North-West region, Cameroon. His domain of research concerns the improvement of energy

conversion techniques for an efficient generation of electrical energy from renewable sources (especially wind and solar energy, small and medium scale hydropower) and digital designing using FPDs. The author is looking for a Ph.D program in his domain of research (he has not yet found it). Any suggestion for this issue will be warmly welcome.

NGOUNE Jean-Paul, P.O. Box: 102 NSO, Kumbo, Cameroon. Phone: (+237) 7506 2458. Email : jngoune@yahoo.fr Web site: www.scribd.com/jngoune

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