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Wikipedia The Free On-line Encyclopedia VHDL - Verilog -

What is HDL
In electronics, a hardware description
g g y g g language or HDL is any language from a class of computer languages for formal description of electronic circuits. The two most widely-used and well-supported HDL varieties used in industry are:

VHDL (VHSIC hardware description language) Verilog is a hardware description language (HDL)

used t model electronic systems. Th l d to d l l t i t The language (sometimes called Verilog HDL) supports the design, verification, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction.



Verilog is a hardware description language (HDL) Verilog is used by several companies in the commercial chip design and manufacturing sector today It is rapidly overtaking the rival HDL today. called VHDL Verilog allows a designer to develop a complex hardware system, e.g., a VLSI chip containing millions of transistors, by defining it at various levels of abstraction

at the (highest) behavioral, or algorithmic, level the design consists of Clike procedures that express functionality without regard to implementation at the dataflow level the design consist of specifying how data is processed and moved between registers at the gate level the structure is defined as an interconnection of logic gates at the (lowest) switch level the structure is an interconnection of transistors

Structural Level



Verilog allows the designer to simulate and verify the design at each level EDA (electronic design automation) tools help the designer to move from higher to lower levels of abstraction

Behavioral synthesis tools create dataflow descriptions from a behavioral description Logic synthesis tools convert an RTL description to a switch level interconnection of transistors, which is input to an automatic place and route tool that creates the chip layout

With Verilog and EDA tools one could sit at a computer at home, design a complex chip, email the design to a silicon foundry in California, California and receive the fabricated chip through regular mail in a few weeks! The Verilog environment is that of a programming language. Designers, particularly with C programming experience, find it easy to learn and work with


Government Developed Ada based Strongly Type Cast Case-insensitive Difficult to learn More Powerful



Commercially Developed C based Mildly Type Cast Case-sensitive Easier to Learn Less Powerful

Learning Verilog

Verilog is essentially a programming language similar to C with some Pascal-like constructs The best way to learn any programming language is from live code We will get you started by going through several example programs and explaining the key concepts We will not try to teach you the syntax line-by-line: pick up what you need from the books and on-line tutorials Tip: Start by copying existing programs and modifying them incrementally making sure you understand the output behavior at each step Tip: The best way to understand and remember a construct or keyword is to experiment with it in code, not by reading about it We shall not design at the switch (transistor) level in this course the lowest level we shall reach is the gate level. The transistor level is more appropriate for an electronics-oriented course



How to learn Verilog by yourself ?


Simulation and Synthesis Modules and Primitives Styles Structural Descriptions Language Conventions Data Types Delay Behavioral Constructs Compiler Directives Simulation and Testbenches


Simulation and Synthesis

Simulation tools typically accept full set of Verilog yp y p g
language constructs Some language constructs and their use in a Verilog description make simulation efficient and are ignored by synthesis tools Synthesis tools typically accept only a subset of the full Verilog language constructs

In this lecture, Verilog language constructs not

supported in Xilinx ISE are in red italics

Modules are basic building blocks of Verilog g g Description of the logic being modeled is placed
inside modules Module definition starts with keyword module Ends with the keyword endmodule

M d l d l ti cannott b nested Modules declarations be t d

Modules are:
Declared Instantiated


Module Example
module hello; initial begin $display(Welcome to the MSEE Class!); $display(Good luck to all Participants); $finish; end endmodule


Module Ports

Modules communicate with the outside world through p ports Module port are similar to pins in hardware

For Example:
module dff (q, qn, d, clk); input d, clk; output q, qn; reg q, qn; always @(posedge clk) begin q = d; qn = ~d; end endmodule


Port Types

Inputs are values being provided to the

Outputs are values being driven by the

Ports that act as input and output ports

Module Declaration

Annotated Example
/* module_keyword module_identifier (list of ports) */ module C_2_4_decoder_with_enable (A, E_n, D) ; input [1:0] A ; // input_declaration input E_n ; // input_declaration output [3:0] D ; // output_declaration assign D = {4{~E_n}} & ((A == 2'b00) ? 4'b0001 : (A == 2'b01) ? 4'b0010 : (A == 2'b10) ? 4'b0100 : (A == 2'b11) ? 4'b1000 : 4'bxxxx) ; // continuous_assign endmodule


Module Declaration

Identifiers - must not be keywords! Ports

First example of signals Scalar: e. g., E_n Vector: e. g., A[1:0], A[0:1], D[3:0], and D[0:3] Range is MSB to LSB Can refer to partial ranges - D[2:1] Type: defined by keywords
input output inout (bi-directional)

Module Instances Modules can be instantiated within other

modules to create a hierarchy

module top; reg data_in, clock; wire data_out, data_outb; dff D_flipflop(data_out, data_outb, data_in, clock); .. ..



Top data_outb


Module Instantiation

ExampleC_4_16_decoder_with_enable (A,, E_n,, D)) ; module (

input [3:0] A ; input E_n ; output [15:0] D ; wire [3:0] S; wire [3:0] S_n; C_2_4_decoder_with_enable C 2 4 decoder with enable DE (A[3:2] (A[3:2], C_2_4_decoder_with_enable D0 (A[1:0], C_2_4_decoder_with_enable D1 (A[1:0], C_2_4_decoder_with_enable D2 (A[1:0], C_2_4_decoder_with_enable D3 (A[1:0], endmodule

E n S); E_n, S_n[0], D[3:0]); S_n[1], D[7:4]); S_n[2], D[11:8]); S_n[3], D[15:12]);

Gate Level
and nand and, or, nor xor, xnor buf , not bufif0, bufif1, notif0, notif1 (three-state) *mos where * is n, p, c, rn, rp, rc; pullup, pulldown;
*tran+ where * is (null), r and + (null), if0, if1 with both * and + not (null)

Switch Level




No declaration; can only be instantiated and(out, in1,in2) ( ) All output ports appear in list before any input ports Optional drive strength, delay, name of instance Example: and N25 (Z, A, B, C); //instance name Example: and #10 (Z, A, B, X); // delay (X, C, D, E); //delay /*Usually better to provide instance name for debugging.*/ Example: or N30 (SET, Q1, AB, N5), N41 (N25, ABC, R1); Example: and #10 N33(Z, A, B, X); // name + delay


Structural - instantiation of primitives and

modules d l RTL/Dataflow - continuous assignments Behavioral - procedural assignments



Style Example - Structural

module full_add (A, B, CI, S, CO) ; input A, B, CI ; output S, CO ; wire N1, N2, N3; half_add HA1 (A, B, N1, N2), HA2 (N1, CI, S, N3); or P1 (CO, N3, N2); endmodule

module half_add (X, Y, S, C); input X, Y ; output S, C ; xor (S, X, Y) ; and (C, X, Y) ; endmodule

Style Example - RTL/Dataflow

module fa_rtl (A, B, CI, S, CO) ; input A, B, CI ; output S, CO ; assign S = A ^ B ^ CI; //continuous assignment assign CO = A & B | A & CI | B & CI; //continuous assignment endmodule



Style Example - Behavioral

module fa_bhv (A, B, CI, S, CO) ; input A, B, CI ; output S, CO ; reg S, CO; // required to hold values between events.

always@(A or B or CI) //; y @( ) ; begin S <= A ^ B ^ CI; // procedural assignment CO <= A & B | A & CI | B & CI; // procedural assignment end endmodule 47


Concurrent Blocks
Blocks of code that seem to execute in the
same point in time



Concurrent Blocks

initial always

Continuous assignments


Procedural blocks

Two Types
iinitial: executes only once at time zero ii l l i always: block is active throughout the simulation

Within each block, all statements executed






Initial Block

Executes once at time zero

module test; reg a, b; wire out; 2inputAND (out, a, b); // AND gate instance initial begin a = 0; b = 0; end endmodule


Always Block
Definition Executes every time a specified event occurs e.g clock edge Syntax
always @ (sensitivity list / event) begin end

module ANDgate; wire a, b; always @ (a or b) begin b i out = a & b; end endmodule



Continuous Assignments

Continuous assignments
Single statement which executes continuously
and does not wait for any event to occur Syntax
assign a = b + c;


Concurrent Execution
All procedural blocks execute concurrently All you to modell the inherentt concurrency Allows t d th i h
in hardware All procedural blocks are activated at time 0, waiting to be executed upon specified conditions






Signal Values and Resolution

0 1 x z
Zero Low False Logic low Ground VSS Negative Zero, Low, False, low, Ground, VSS,

One, High, True, Logic High, Power, VDD, VCC,

Positive Assertion

U k Unknown: O Occurs at Logical C fli t which cannot b t L i l Conflict hi h t be


Hi-Z: High Impedance, Tri-stated, Disabled Driver


Sensitivity List

Signals or events that trigger the execution

of a statement or a block of statements f t t t bl k f t t t Constantly monitored by the simulator A large sensitivity list degrades simulation performance

Example: always @ ((posedge clock or reset) l d l k t)



Numbers in Verilog

Format number of bits radix value
Value Number of bits Radix

Number of bits and radix are optional Default no. of bits = 32, default radix = decimal Letter used for radix b binary, d decimal, o octal, h hexadecimal. Case insensitive. White spaces OK, except between and radix Examples,

8b10100101 16habcd b 101 1bz 1b x 1 b 1 8b101xx101 // 8-bit binary number (165) // 16-bit hex number (abcd) // 32-bit binary number (5) // 1 bit binary number (z) // 1 bit binary number (x) // Illegal // 8-bit binary number


Data Types in Verilog

Wire C Connect modules or primitives in a design t d l i iti i d i Cant retain their value Registers Can hold their value Integers g
32 bit signed numbers



Data Types in Verilog: Wire

Wire: Connects modules or primitives Wires cant store their values, must be driven Wire can be one bit wide or more than one bit wide (vector) Examples, wire a; // declares a as a wire wire x, y, z; // declares x, y, z as three wires wire [7:0] b, c, d; // declares b, c, d as three 8-bit vector wires

default data type in Verilog module ports are implicitly defined as wire by Verilog


Data Types in Verilog: Wire

Wire (example 1):
c is explicitly defined
as a wire three other wires in this module, y, a, b, are also port modules y, a, b are implicitly defined as wires
a b c

module nand_gate (y, a, b); input a, b; output y; wire c;

and2_gate U1 (c, a, b); not_gate not gate U2 (y c); (y,




module nand_gate


Data Types in Verilog : Reg

Registers (unlike wires) can store values Registers can be one bit, or more than one bit
(vectors) Driven Outputs need to be of type reg Examples, reg a;; g // declares a as a register g reg x, y; // defines x and y as two registers reg [4:0] b; // declares b as a 5-bit (vector) register


Data Types in Verilog (contd.)

Registers (example):

The output port q is defined as a one bit register q is assigned the value of input d at the positive edge of the input clk
module dff(q, d, clk); input q, clk; output q;

d q clk

d-val d val x d-val

reg q;

always @ (posedge clk) q = d;




Data Types in Verilog (contd.)

Integers: Integers are 32 bit wide in Verilog Integers are signed numbers example, integer j, k, l; // declares three integers Keyword integer, NOT int Main difference between integer and reg is, integer is signed, reg is unsigned Integers cannot have bit-selects ie. J [4:0] Integers are not recommended for synthesis

Data Types in Verilog (contd.)

Integer: examples.

integer j, k, l; // declares j, k, l as three integer // assigns 5 to j

24 4 0

j = 32d5;

0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 1

k = 32b110;
28 24

// assigns 6 to k
4 0

0 0 0 0 0 0 0 0

0 0 0 0 0 1 1 0

l = -32d5;
28 24

// assigns -5 to l (2s complement)

4 0 65

1 1 1 1 1 1 1 1

1 1 1 1 1 0 1 1


Difference between scalar and a vector

Scalar: reg a, b; Vector: reg [4:0] A, B;



No explicit data type Must be stored in reg whose size is

8*(num. of characters) reg [255:0] buffer; //stores 32 characters



Constants (Paramters)

Declaration of parameters
parameter A = 2b00, B = 2b01, C = 2b10; parameter regsize = 8;
reg [regsize - 1:0]; /* illustrates use of parameter
regsize */


Operators in Verilog
Shift Logical g Conditional Negation Relational Replication Concatenation Equality Unary Reduction Bit-wise



Shift operator
The left shift operator (<<) shifts the left operand
left by the number of bit positions specified by the right operand. The right shift operator (>>) shifts the left operand right by the number of bit positions specified by the right operand.

E Example: l
module shift; initial begin $display (8b00011000 << 2); // 01100000 $display (8b00011000 >> 3); // 00000011 end endmodule


Logical Operator
Logical operators (&&, ||) produce a scalar value
(0, 1, X). (0 1 or X)

module logical_block; initial begin $display (2b00 && 2b10); $display (2b01 && 2b10); $display (2b00 || 2b00); $display (2b01 || 2b00); (2 b01 2 b00); $display (2b00 && 2b1x); $display (2b1z && 2b10); end endmodule // 0 // 1 // 0 // 1 // x // x



Conditional Operator
The conditional operator (?:)
Also called ternary operator, operator Syntax:

Must have 3 operands. It selects from two operands, based on a third.

<conditional expression> ? <true_expression> : <false_expression>

It can be thought of as if-else statement.

if (conditional_expression) LHS = true_expression; else LHS = false_expression; false expression;

An unknown conditional expression can still

produce a known value if all possible selections are identical.

Conditional operator

Example 1
module tristate (O, I, E); output O; t tO input I, E; assign O = E ? I : 1bz; endmodule

Example 2
module mux41 (O,S,A,B,C,D); output O; input A B C D; A, B, C, input [1:0] S; assign O = (S == 2d0) ? A : (S == 2d1) ? B : (S == 2d2) ? C : D; endmodule


Lab 2: Ternary Operator

Objective: Write a module for a 8 to 1 mux. mux Specification:
module 8to1(in0,in1,in2,in3,in4,in5,in6,in7,select, out) ; input [2:0] select; input in0,in1,in2,in3,in4,in5,in6,in7; output out; endmodule


Other Operators

Negation operator:

(!) logical (~) bitwise Reduces an operand to its logical inverse. Example:
$display ( !4b0100 ); // 0 $display ( !4b0000 ); // 1 $display (~4b01xx ); //10xx

Relational Operators p

Less than (<), Less than or equal to (<=), Greater than or equal to (>=), Greater than (>). Example: if (A >= 2b11) then B = 1b1;



Operators: Replication

Replication operator
Replicates an expression a fixed number of
times to form a new vector quantity. ({n{}}) Example regA = 2b11; b = {4{ A}} // b = 11111111 bus {4{regA}}; bus


Operators: Concatenation

Concatenation operator
Allows you to select bits from different vectors
to join then into a new vector. {} concatenation Example new_vector[8:0] = {regA[4:2],regB[1:2],1b0,regC[3:0]};



Other operators

Logical equality(==) operator

Evaluates to be true if LHS is equal to the RHS. Logical L i l equality(==) operator evaluates t b unknown (X) if either lit ( ) t l t to be k ith LHS or RHS have an x Operation is inverse for the inequality (!=) operator.
$display ( 4b0011 == 4b1010 ) ; // 0 $display ( 4b0011 != 4b1x10 ) ; // x

Case equality (===) Case inequality (!==)

operators are the same as the logical equality except that they perform definitive match of bit positions that are Z or X. Example valid = (A == 2b11) ?1: 0;

Bit-Wise Operators

Bit-wise operators perform bit-wise manipulations on two operands ( p (vectors) ) They compare each bit in one operand with its corresponding bit in the other operand to calculate each bit of the result
~ & | ^ ~^ / ^~ not and or xor xnor

rega 4b1001; regb 4b1010; regc 4b11x0; rega & 0; rega & regb; rega | regb; regb & regc; regb | regc;

//0000 //1000 //1011 //10x0 //1110



Unary Reduction Operator

Unary reduction operators operate on all bits of
a single operand(vector) to produce a single bit single-bit result (scalar)
~ & | ^ ~^/ ^~ not and or xor xnor

Example: p
rega 4b0100; regb 4b1111; &rega ; |rega ; ^regb ; ~|rega ; ~&rega ; //0 //1 //0 //0 (nor) //1 (nand)


The difference between Scalar value and Vector value The difference between ~ and ! The difference between & and &&



Operator precedence
------------------------------------------------------------------------------Type of Operator Symbols ------------------------------------------------------------------------------ Concatenate & replicate {} {{ }} Unary ! ~ & ^ ^~ | Arithmetic * / %+ Logical shift << >> Relational < <= > >= Equality == != === !== Binary bit-wise & ^ ^~ | Binary logical && || Conditional ?: -----------------------------------------------------------------------------82

Expressions with Operands Containing x or z

If any bit is x or z result is all xs z, xs. Divide by 0 produces all xs.

If any bit is x or z, result is x.

== and != If any bit is x or z, result iis x. d! i lt === and !== All bits including x and z values must
match for equality


Expressions with Operands Containing x or z

Bitwise Shifts Reduction
Defined by tables for 0, 1, x, z operands. Defined by tables as for bitwise operators. z changed to x. Vacated positions zero filled. If conditional expression is ambiguous (e.g., x or z),
both expressions are evaluated and bitwise combined as follows: f(1,1) = 1, f(0,0) = 0, otherwise x.


Simulation Time Scales

Compiler Directive `timescale <time_unit> /
<time_precision> <time precision> time_unit - the time multiplier for time values time_precision - minimum step size during simulation - determines rounding of numerical values Allowed unit/precision values: All d it/ i i l {1| 10 | 100, s | ms | us | ns | ps}



Simulation Time Scales (continued)

Example: p
`timescale 10ps / 1ps nor #3.57 (z, x1, x2); nor delay used = 3.57 x 10 ps = 35.7 ps => 36 ps

Different timescales can be used for different

sequences of modules q The smallest time precision determines the precision of the simulation.

Blocking Assignments
Identified by = Sequence of blocking assignments executes
sequentially Example:
always @(posedge clk) begin b = 0; c = 0; b = a + a; c = b + a; d = c + a; end


Non-Blocking Assignments

Identified by <= Sequence of non-blocking assignments executes q g g concurrently Example 1:
always @(posedge clk) begin

b <= 0; c <= 0; b <= a + a; c <= b + a; d <= c + a;

end /*Calculates b = 2a, c = b + a, d <= c + a. All values used on RHS are those at posedge clock. Note that there are two assignments to b and c. Only the last one is effective. */


Blocking Assignments - InterAssignment Delay

Delays evaluation of RHS and assignment to LHS y g


always @(posedge clk) begin b = 0; c = 0; b = a + a; // uses a at posedge clock #5 c = b + a; // uses a at posedge clock + 5 d = c + a; // uses a at posedge clock + 5 end /*c = 2 a(at posedge clock)+ a(at posedge clock + 5) d = 2 a(at posedge clock) + 2 a(at posedge clock + 5)*/


Blocking Assignment - IntraAssignment Delay

Delays assignment to LHS and subsequent y g q

statements, not evaluation of RHS

always @(posedge clk) begin b = 0; c = 0; b = a + a; // uses a at posedge clock t d l k c = #5 b + a; // uses a at posedge clock d = c + a; // uses a at posedge clock + 5 end /* c = 3 a(at posedge clock) d = 3a (at posedge clock)+ a (at posedge clock + 5)*/

Non-Blocking Assignment Inter-Assignment Delay

Delays evaluation of RHS and assignment to LHS Delays subsequent statements


always @(posedge clk) begin b <= 0; c <= 0; b <= a + a; // uses a at posedge clock t d l k #5 c <= b + a; // uses b and a at posedge clock + 5 d <= c + a; // uses a at posedge clock + 5 end /*c = b(at posedge clock + 5) + a(at posedge clock + 5) posedge clock + 5) + a (at posedge clock +5) */

d = c(at


Non-Blocking Assignment Intra-Assignment Delay

Delays only assignment to LHS


always @(posedge clk) begin b <= 0; c <= 0; b <= a + a; // uses a at posedge clock c <= #5 b + a; // uses a and b at posedge clock < d <= c + a; // uses a and c at posedge clock end /* Calculates *c(posedge clock + 5) = b(at posedge clock) + a(at posedge clock); d(posedge clock) = c(at posedge clock) + a (at posedge clock) */

Control Constructs in Verilog

We will cover four control constructs in Verilog: 1. if-else 2. case 3. while 4. 4 for



Control constructs (if-else)

if (condition) procedural_block1 else procedural_block2
module mux (y, a, b, sel); input a, b, sel; output y; reg y;

Condition can be an expression or just a value a 0 or unknown is FALSE, 1 or more is TRUE No then or endif in Verilog! If nested ifs are used, else belongs t i b l to immediately di t l preceding if
sel a b y

always @ (a or b or sel) if (sel) y = a; else y = b;


module mux

Lab 3: If-else


Use if-else construct to compare two 8-bit inputs a and b. b There are three one bit outputs g(reater), l(ess), g(reater) l(ess) e(qual)
Condition a>b a<b a=b None of the above g l e 1 0 0 1 0 1 0 1 0 0 1 1

a[7:0] b[7:0]

a>b a<b a=b

g l e



Control constructs (case)

case (condition) value1: procedural_block1 value2: procedural_block2 .. valuen: procedural_blockn default: procedural_block endcase

module mux4a (y, a, b, c, d sel); input a, b,c, d; input [2:0] sel; output y; reg y; always @(a or b or c or d or sel) case (sel) 3b000 : y = a; 3b001 : y = b; 3b010 : y = c; 3b011 : y = d; default : y = 1bx; endcase endmodule sel[2:0] a b c d y

Condition can be an expression or just a value A procedural block matching the value of the expression is executed Default statement is executed if there are no matches Unlike C, no break!

module mux4a


Control constructs (casez, casex)

case statement matches x with x and z with z to be true case does not allow wild character (?) In casez, ? or z will match to any value , i.e. use ? or z for dont cares In casex, ? Is not supported. Use x or z to indicate dont cares
Value 0 1 x z ? case casez casex 0 0 0 1 1 1 x x 01xz z 01xz 01xz unused 0 1 x z unused
module counta(clk, rst, ld, up, din, dout); input clk, rst, ld, up; input [15:0] din; output [15:0] dout; reg [15:0] dout; always @(posedge clk) casez ({rst, ld, up}) 3b1zz : dout = 8b0; 3b01? : dout = din; 3b001 : dout = dout + 1; 3b000 : dout = dout - 1; default : dout = 8bx; endcase endmodule

Summary of Case Values and Match per Case Type



Lab 4: Case

Objective: Use case construct to create an 8-bit counter with a two bit control input c, 8-bit data input din, 8-bit data output dout. All operations are synchronous w.r.t +ve edge clock clk.
c[1:0] dout(n+1) Comment 00 din Load data 01 dout(n)+1 Increment by 1 10 dout(n)-1 Decrement by 1 11 0 Reset






Control constructs (for loop)

Structure: for (expr1; expr2; expr3) procedural_block1 expr1 is initialization expression which is executed when the loop is entered the first time expr2 is the condition which is evaluated and if TRUE the for loop is entered (or re-entered) t d) expr3 is the increment which is performed after the loop is executed The three expression dont need to refer to the same reg or variable
// add the 5 LSBs of 16 bit input module counter (sum, datain, clk); input clk; input [15:0] datain; output [2:0] sum; reg [2:0] sum, i;

always @ (posedge clk) for (i=0; i<5; i = i+1) sum = sum + datain[i]; endmodule



Lab 5: for loop


Use a for loop to detect number of times 010 pattern is found in 32 bit i i a 32-bit input din. The patterns can overlap each other, ex. t di Th tt l h th 01010 counts as two patterns. The 4-bit output is named count




Control constructs (while loop)

while (condition) procedural_block1
count=1 count=2 count=3

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read next number at posedge clock

Condition is evaluated if evaluated, TRUE the loop is entered While loop is executed as long as condition remains TRUE Not Synthesizable

/* counts the number of leading zeros in 16 bit input */ module zerocount (count, datain, clk); input clk; input [15:0] datain; output [4:0] count; reg [4:0] count; reg [15:0] din_reg; always @(posedge clk) begin count = 0; din_reg = datain; while ((din_reg[15]==0) && (count < 16)) count = count+1; din_reg = din_reg << 1; end // while end // always endmodule




Lab 6 : while loop

Use while loop to design a circuit which divides a 16-bit input din by 3. The 15-bit output result holds the result of the division, and 2-bit output remainder the remainder. di i i d 2 bit t t i d th i d Hint: Use successive subtractions to get the result and the remainder. You can assume that din is always a positive number.

result[14:0] din[15:0] remainder[1:0]


Testbench Approach

Use Verilog module to produce testing

environment i l di stimulus generation i t including ti l ti and/or response monitoring
Stimulus Response

UUT Module M d l

Testbench Module


1. 2. 3. 4. 4 5. 6.
IEEE, 1364-1995 IEEE Standard Description Language Based on the Verilog(TM) Hardware Description Language. Synopsys, FPGA Compiler II/FPGA Express: Verilog HDL Reference Manual, Version 1999.05, May 1999. Thomas, D. E., and P. R. Moorby, The Verilog Hardware Description Language, 4th Ed., Kluwer Academic Publishers, 1998. Smith, D. R., and P. D. Franzon, Verilog Styles for Synthesis of Digital Systems, Prentice Hall, 2000. Ciletti, Michael D., Modeling, Synthesis, and Rapid Prototyping with the Verilog DHL, Prentice Hall, 1999. Palnitkar, Samir, Verilog HDL: A Guide to Design and 104 Synthesis, Sunsoft Press, 1996.