Академический Документы
Профессиональный Документы
Культура Документы
Kaijian Shi
Synopsys Professional Services Dallas, USA kaijian@synopsys.com
David Tester
Structured Custom Cambridge, UK david.tester@structured-custom.com
ABSTRACT
65nm and beyond CMOS designs are commonly implemented with tapless library cells which do not have built-in well taps. To maintain proper transistor back biasing and prevent latch-up, special tap cells need to be inserted at intervals satisfying the tap rules. In power-gating designs, the tap cell insertion becomes complicated due to not only co-existence of always-on and powergated domains but also different supply voltages applied to different domains. This paper describes a domain-based tap insertion methodology and implementation techniques to ease the complicity and minimize risks of incorrect tap insertions in power gating designs.
Table of Contents
1. 2. 3. 1. 2. 4. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Introduction ........................................................................................................................... 3 Tapless design and conventional tap insertion method......................................................... 3 Tap insertion requirements in power-gating designs ............................................................ 5 ALWAYS-ON TAP CELL........................................................................................................ 5 ALWAYS-ON WELL TAP POWER CONNECTIONS .................................................................... 6 Challenges in tap insertions in power-gating designs ........................................................... 6 DOMAIN-BASED TAP TYPE SELECTION ................................................................................ 6 DOMAIN-BASED TAP POWER LOGIC CONNECTIONS.............................................................. 6 DOMAIN-BASED TAP POWER PHYSICAL CONNECTIONS ........................................................ 7 OFF-GRID TAP INSERTION AND POWER CONNECTIONS ......................................................... 8 Domain-based tap type selection method ............................................................................. 8 Domain-based tap cell logic PG connection method ............................................................ 9 Domain-based tap cell physical PG connection method..................................................... 10 Off-grid tap insertion and power connections .................................................................... 12 Results ................................................................................................................................. 13 Summary ............................................................................................................................. 14 References ........................................................................................................................... 15 Author biographies.............................................................................................................. 15
SNUG 2011
1. Introduction
65nm and beyond CMOS designs are commonly implemented with tapless library cells for low cost in silicon area. The tapless cells do not have built-in taps that connect n-well and p-substrate to the power and ground rails. To prevent latch-up and maintain proper transistor back biasing, special tap cells are inserted in the layout at the required interval to connect n-wells to VDD and p-substrate to VSS based on tap rules defined in the technology DRC file. In a traditional single voltage domain design standard cells are all connected to VDD and VSS rails that are always active when the chip is powered on. As the result, the tap insertion in traditional design was relatively easy and could be done reliably by the ICC tap insertion flow. However, the tap cell insertion becomes complicated in power-gating designs which often contain both always-on and shutdown blocks where power can be turned off. For a power-gating block, special taps (always-on taps) are required to prevent latch-up and maintain proper transistor back biasing when power supplies to the standard cells in the block are turned off, while Power-Management (PM) cells in the block are active. Also, the tap cells need to be logically and physically connected to the correct power supplies to ensure power integrity. As the result, a domain-based PM tap insertion flow becomes both necessary and critical in a tapless power-gating design until such an automated flow is implemented in ICC in the future. This paper describes the domain-based tap insertion method and implementation techniques which have been integrated in our low-power design flow and have been used successfully in a number of production low-power designs. In the rest of the paper, the normal tap design and tap insertion method are outlined first. Then, special requirements for tap insertion in power-gating designs are outlined. Design of always-on taps and challenges in the PM tap insertion are explained. Next, the domain-based PM tap insertion method is described in detail with supporting scripts and an example is provided to demonstrate the method.
SNUG 2011
To maintain required transistor back bias and prevent latch-up, n-well in a standard cell is extended at cell boundary to form continuing wells when the standard cells (including filler cells) are abutted in the design. The wells are connected to VDD and VSS supplies by tap cells inserted at interval based on the tap rule defined by the technology to get well bias and prevent latch-up. The tap cell is a simple standard cell which has an n-well tap connected to VDD rail and a psubstrate tap connected to VSS rail as shown in Fig. 1.
When integrated in the design, the tap cell VDD and VSS rails are aligned with the rails of the design, as shown in Fig. 2, to connect VDD and VSS power supplies along the standard cell row. Substrate and n-well connections are provided by taps within the tap cells. Tap insertion in normal SOC design is not complicated since EDA tools usually provide a facility to insert the tap cells and guarantee meeting tap rules defined in the technology DRC runset. In ICC, this is done by the command add_tap_cell_array. Power connections of the taps are automatically provided through the cell row VDD and VSS rails.
SNUG 2011
SNUG 2011
2. Always-on well tap power connections Having the always-on tap cells inserted within the shutdown blocks, the next task is to connect their well tap pins to always-on power supplies. The power and ground rails that provide the power supplies to standard cells in the power-gated domain can no longer be used for tap power supply because they would be turned off in the shutdown mode. Consequently, an always-on tap grid needs to be created to acomplish the required tap power connections. Moreover, the tap cells are often inserted at irregular grid pattern in complex design to satisfy the tap rules. This results in challenges in the always-on tap power connections to ensure that all the tap cells are connected to the always-on power supplis. The details of the challenges are described in the following sections.
SNUG 2011
ICC hooks up both VDD and VDDC pins of the always-on taps to the global power supply net VDD. This is due to command limitation that only one power connection option is available in the command while the always-on tap needs two power connnections. Case 2: Do not connect power in add_tap_cell_array and then use derive_pg_connection to do logic connections
add_tap_cell_array (without derive_pg_connection -connect_power_name option)
In this case, the tap insertion did not hook up tap power pins as instructed. The hook up is done by the following command derive_pg_connection. Unfortunately, derive_pg_connection connects power pins of the physical only cells to domain primary power net which is the switched vdd in the power-gated domain. Consequently, both VDD and VDDC pins of the always-on taps are connected to switched supply vdd. This is incorrect. The issue is getting worse in ICC2010.12 where add_tap_cell_array automatically connects all power pins to domain primary power even if the always-on supply net VDD is defined in option "-connect_power_name" due to a tool bug. It is worth noting that the tap cells are physical cells which do not have signal pins nor a logical function.Consequently, they are not compiled into standard cell libraries like other powermanagement cells for physical synthesis. 3. Domain-based tap power physical connections The always-on tap power physical connections are also challenge. Since always-on power grid may not close to the always-on taps, the power routes from the always-on taps to the always-on grid could result in considerable impact on signal routing. Good planning considering both the tap insertions and tap power connections is needed to address the issue.
SNUG 2011
4. Off-grid tap insertion and power connections Off-grid taps are often inserted in designs containing macros in order to satisfy the n-well and substrate tap spacing rules in the DRC deck. In the example shown in Fig. 4 containing RAM macros those taps inserted in the RAM channel and right side of the RAM block boundary are at a half of the tap pitch to properly connect to the n-well tap and substrate tap connectivity of the standard cells in the regions. The off-grid taps do not have an always-on power supply, because they are not covered by the always-on tap grid which is commonly built alinged with taps at the tap pitch. Consequently, we need facilities to detect the off-grid taps and provide always-on power routes to connect their power pins correctly. Currently, ICC does not provide such facilities.
SNUG 2011
foreach domain $domain-list { set tap_cell [select_tap $domain] insert_tap_cells $tap_cell $domain }
$domain
SNUG 2011
In the second method, we define tap power connection by the -connect_power_name vdd option in add_tap_cell_array to get logic PG connections in the tap insertion. To resolve the issue that both always-on and switched VDD pins are connected to the switched-vdd net due to the command limitation that only one power connection is allowed, we disconnect the always-on pin connections and reconnect them to the always-on power supply.
proc always_on_tap_pg_connect {domain} { add_tap_cell_array -voltage_area $domain.voltage_area \ -connect_power_name $domain.switched_vdd \ more options disconnect_net $domain.switched_vdd $always_on_tap_VDDC_pins derive_pg_connection -cells $always_on_tap_cells \ -power_net vdd -power_pin VDDC }
The first method decouples the logic PG connection from tap insertion. The issue of logic PG connection due to the derive_pg_connection limitation is resolved by the multi-pass workaround. However, this method does not work in ICC 2010.12 release where add_tap_cell_array will perform logic connection regardless if the connect_power_name option is defined or not. Unfortunately, the connections are incorrect as both VDD and VDDC pins are connected to switched-vdd. The second method still works in ICC 2010.12 release, as it will reconnect the incorrectly connected pin.
In the method, the VDDC pins of the always-on taps are routed to the always-on vertical straps close to the taps, as shown by the green horizontal routes in Fig. 5., by the net mode preroute_standard_cell.
SNUG 2011
The default width of the route is the minimum metal width defined in the technology file. Since taps consume little current, the minimum width should be fine to satisfy IR-drop and EM constraints provided no other cells were connected to the routes. If needed, the route width can be change by the h_width option in preroute_standard_cell. The advantage of the method is that it is simple to implement. However, the net mode routes result in noticeable routing resource usage due to metal routes of every tap pins to the vertical always-on power straps, especially when the vertical straps are not close by. This shortcoming is overcome by the second method. In the second method, a custom always-on tap grid is built to leverage the always-on power connection at switch cell VDDC pins that are available next to the tap cells. The objective of the method is to minimize power routing impact on signal routing. Taps VDDC pins are via connected to the lower layer vertical straps which connect at 6 rows internval to the switch cell VDDC pins to get always-on VDD supply. The pseudo-code of the method is described below.
proc always_on_tap_pg_route {domain} { create vertical lower layer straps within domain voltage area at tap pitch and aligned with the tap array columns foreach tap_array_column { foreach switch cell close to the tap_array_column { create a horizontal lower layer stub to connect the switch always-on pin and vertical tap strap } } }
SNUG 2011
The clip in Fig. 6 illustrates the custom always-on tap physical connections of the method.
The advantage of the method is the low utilization of lower layer horizontal routing resources which are valuable to signal routing. However, the method relies on the ability to leverage existing always-on power routes at switch cells close-by. Therefore, it is not such a flexible approach as the first method. Moreover, the tap pitch might have to be adjusted to make the taps aligned with the switch horizontal pitch to ensure short stub connections between the taps and the switches.
SNUG 2011
proc
detect_off_grid_always_on_taps { foreach tap $always_on_taps { if no metal strap at next layer over the VDDC pin of the tap { append the tap to collection off_grid_always_on_taps } } return $off_grid_always_on_taps
} proc fix_off_grid_always_on_taps { set off_grid_taps [detect_off_grid_always_on_taps] set sorted_off_grid_taps [sort_collection $off_grid_taps bbox_llx bbox_lly] foreach tap_column in $sorted_off_grid_taps { create vertical always-on strap next to the column } preroute_standard_cells -mode net -nets \ -port_filter_mode select -port_filter VDDC \ -cell_master_filter_mode select \ -cell_master_filter $always_on_tap_master_cell \ -h_width $tap_route_h_width \ -do_not_route_over_macros }
9. Results
The methods described in the paper have been implemented in a UPF DC/ICC flow for production low-power design. Three chips have been successfully taped out using the UPF flow. To illustrate the methods, a small design was created which has an always-on domain at bottomleft corner and a shutdown domain which takes the rest of the design and in rectilinear shape. The domain-based tap insertion and PG grid generation methods were applied to the design transparently as it has been integrated into the UPF flow and fully automated. The results are shown in Fig. 7. In the always-on domain, normal taps were selected and inserted. Simple cell rail connections completed the task of physical PG connections of the taps. In the shutdown domain, the always-on taps were inserted at 60um pitch defined by the tap rule. A column of offgrid taps were inserted at a half tap pitch in the middle of the domain to satisfy the tap requirement in the standard cell region from right side of the always-on domain. The custom always-on tap grid method was used in this case to leverage existing always-on grids on the switch cells. The vertical straps were correctly created over the all taps including the off-grid taps. The horizontal stubs were also inserted connecting the vertical straps to the switch alwayson power pins to get power supply to the taps.
SNUG 2011
10. Summary
Most sub-65nm production SOC designs are implemented with tapless library cells for silicon area efficiency. The tap cell insertion flow becomes complicated and risk-prone in power-gating designs where always-on and shutdown blocks co-exist and different types of tap cells need to be implemented in different domains accordingly. Furthermore, the logic and physical PG connections of these tap cells becomes no longer straight forward and could result in chip failure if not implemented correctly. This paper addresses these challenges in the tapless power-gating design by a domain-based tap insertion method and implementation techniques including domain-based tap type selection, always-on tap logic PG connection and PG grid generation, and off-grid tap detection and fix. The method and implementation techniques have been integrated into a UPF DC/ICC flow and have been used successfully in a number of production low-power designs.
SNUG 2011
11. References
IC Compiler user manual.
SNUG 2011