EE157 Digital Design Laboratory

Dennis Silage, PhD

Silos Verilog Simulation

EE157 Digital Design Laboratory will utilize two computer-aid-design (CAD) software programs for the compilation, synthesis and verification of combination and sequential digital logic circuits in the Verilog behavioral language. Initially Silos by Simucad (www.simucad.com) will provide a complete Verilog synthesis and simulation environment that is not hardware dependent and that students can utilize on their own PCs and in the Laboratory. Later, the Xilinx WebPack v6.1i Verilog CAD environment will be used in the Laboratory to design logic circuits for the Digilent DigiLab IIE complex programmable logic device (CPLD) hardware boards. Silos is available as Silos2001, which can operate under Windows 95 and 98, and Silos2003, which can operate under Windows 2000 and XP. Both versions of Silos are similar and provide an easy environment for learning and analysis. If you wish, Silos can be installed and registered on your PC. Of course, the Laboratory PCs also have Silos available. This Silos Tutorial will synthesis a combinational (Figure 2.32) and a sequential (Figure 8.48) digital logic circuit from the textbook to illustrate the Silos CAD process. The first project to be synthesized is the combination logic circuit in Figure 2.33 and listed in Figure 2.32. The textbook CDROM has the Verilog code file for this combinational logic circuit under the folders Verilog, Chapter 2, and fig2_32 and named example2. Copy this file to the a:\ floppy drive since the CDROM version is a read-only file. Using the a:\drive here is good practice because in the Laboratory you will not be able to store your programs and data on the c:\ hard drive. Next, right-click on the highlighted file and select Properties (Figure 1). Unclick the Read-Only and Archive properties and click OK (Figure 2). This file is now available to a text source editor, such as Notepad, and the Silos application. Using a source editor, such as Notepad available under StartPrograms Accessories, open the source file example2, and save it using the All Files designation with the extension .v (for Verilog): examples.v (Figure 3). You can add any comment statements (beginning with //) at this time also. Note that the

default extension for Notepad is .txt (for Text) and the Silos CAD application requires .v. Table 1 shows the example2.v source code.

Figure 1

Figure 2 The example2.v source code also requires a stimulus file to provide digital logic input signals and to analyze outputs. Using the Notepad editor, enter the stimulus file as shown in Table 2. Using Verilog keywords, the outputs of the module under test (in this case example2.v) are designated as wire and the inputs are designated as reg (for register). It is not necessary to declare a wire variable in the parameter list of the stimulus module.

The module under test is evoked by calling it by name with an arbitrary identifier (in this case M1). This is so that the same module can be called multiple times in a design. The Verilog keyword initial initializes the digital logic signals and beginend encapsulates the stimulation. The input variables x1 x2 x3 x4 (= X) are arbitrarily made to count from 0 0 0 0 (X = 0) to 1 1 1 1 (X = 15).

Figure 3 //Figure 2.32 example2.v module example2 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; output f, g, h; and (z1, x1, x3); and (z2, x2, x4); or (g, z1, z2); or (z3, x1, ~x3); or (z4, ~x2, x4); and (h, z3, z4); or (f, g, h); endmodule Table 1 This X count is sufficient to stimulate all the inputs and observe all the outputs of the module under test. Of course, the Silos CAD environment will do that for us.

The module stimulus module name, stimulus, is arbitrary as is the name of the stimulus file on the a:\ drive: stimex2.v. Now we can evoke the Silos CAD design environment. Start SSE from the Silos installation directory, maximize, and execute ProjectNew (Figure 4). Provide a name for the project with the extension .spj (as in name.spj). A good choice would be example2.spj, since this is the name of the Verilog source file.

//Stimulus for Figure 2.32 stimex2.v module stimulus; wire reg f, g, h; x1, x2, x3, x4; //outputs of the module under test //inputs of the module under test //evoke the module

example2 M1(x1, x2, x3, x4, f, g, h); initial begin x1 = 0; x2 = 0; x3 = 0; x4 = 0; x1 = 1; x1 = 0; x2 = 1; x1 = 1; x1 = 0; x2 = 0; x3 = 1; x1 = 1; x1 = 0; x2 = 1; x1 = 1; x1 = 0; x2 = 0; x3 = 0; x4 = 1; x1 = 1; x1 = 0; x2 = 1; x1 = 1; x1 = 0; x2 = 0; // X = 0

#1 #2 #3 #4 #5 #6 #7 #8

// X = 1 // X = 2 // X = 3 // X = 4 // X = 5 // X = 6 // X = 7 // X = 8

#9 #10 #11 #12

// X = 9 // X = 10 // X = 11 // X = 12

#13 #14 #15 end endmodule

x3 = 1; x1 = 1; x1 = 0; x2 = 1; x1 = 1;

// X = 13 // X = 14 // X = 15

Table 2

Figure 4 The Project Files dialog box will be shown (Figure 5). Locate the project files (here on the a:\ drive) and select (highlight) each file and then click Add. The two design files, example2.v and stimex2.v, will be listed as Files/Directories in Group (Figure 5). Click OK to save the project definition. FileOpen can be used to display a window for each of the source files in the design, if warranted. The windows can be moved around the design area and resized, as in a normal Windows environment (Figure 6). New source files can also be entered or existing source files can be edited in these windows in the Silos CAD environment. Notepad can be used as an alternate editor. Next, evoke the Load/Reload File token on the Task Bar (between the Save (floppy disk) and the GO token). Check for any errors in the Output window that

appears (Figure 7). If there are syntaxial errors in the source code, the line numbers where the error occurs will be noted in the Output window.

Figure 5

Figure 6 Then open the Data Analyzer and Explorer tokens on the Task Bar (the two tokens to the right of the GO token) (Figure 8). Highlight the module name and drag and drop the all the input and output signals to be displayed to right side of the Data Analyzer window.

Close the Explorer Window and move and resize the Data Analyzer window to display the signals. Execute the simulation, as specified by the stimulus module, by the GO token. The results are displayed in the Data Analyzer window.

Figure 7

Figure 8 The Data Analyzer window can be maximized and the timescale changed (with other cursor functions) by right-clicking on the time axis (Figure 9). The time axis can be expanded or compressed to view details, the cursors will read-out the current logic Values, and the time between cursors (Tdelta) (Figure 10).

Figure 9

Figure 10 Consult the on-line Silos tutorials on the Data Analyzer and Explorer Windows for addition details on their use and features. On-line Help also includes extensive tutorials and a Verilog language reference. Using the same Silos CAD process, we can now synthesize and simulate a sequential digital logic circuit (Figure 8.48). This circuit is a register shifter with parallel load (L) and enable (E) (Table 3). Note the use of the Verilog keyword parameter to specify the size of the registers R and Q. This would allow us to

conveniently change the size of these registers without a large amount of source code editing. //Figure 8.48 shiftrne.v module shiftrne (R, L, E, w, Clock, Q); parameter n = 8; input [n-1:0] R; input L, E, w, Clock; output [n-1:0] Q; reg [n-1:0] Q; integer k; always @(posedge Clock) if (L) Q <= R; else if (E) begin for (k = n-1; k > 0; k = k-1) Q[k-1] <= Q[k]; Q[n-1] <= w; end endmodule Table 3 The stimulus file stimslr.v (Table 4) can be entered in the Silos CAD environment with FileNew or with Notepad. The stimulus process here is arbitrary but must exercise the digital logic circuit to verify that it works. Note the separate stimulus process for the Clock signal, which changes state (by the Verilog operator for inversion ~) every 1 unit of time. Here we first set the parallel data load register R, the load data command L, the shift enable command E, and the serial data w to 0. The parallel data load command is enabled at time 1 (L = 1) and the register data R changes to 12 (C hexadecimal) at time 5. At time 10, the parallel data load command is disabled (L = 0), the serial data is set to 1 (w = 1) and shift is enabled (E = 1). We should observe the process indicated by the stimulus file in the Data Analyzer window as signal waveforms (Figure 11) to verify the performance of the digital logic circuit. Especially note that the parallel data starts at C hex and progress to FF hex as a continuous data value of 1 in shifted into the 8 bit Q

register. The Verilog meta-command $finish arbitrarily ends the simulation at time 30 here.

Figure 11 //Stimulus for Figure 8.48 stimslr.v module stimulus; parameter n=8; wire [n-1:0]Q; reg [n-1:0]R; reg L, E, w, Clock; //outputs of the module under test //inputs of the module under test //inputs of the module under test

shiftrne M1(R, L, E, w, Clock, Q); //evoke the module initial begin Clock = 0; R = 0; L = 0; E = 0; w = 0; L = 1; R = 12; L = 0; w = 1; E = 1; $finish; // parallel input data // load data // enable shift // serial input data

#1 #5 #10 #30

end always begin #1 Clock = ~ Clock; end endmodule Table 4 The Silos CAD Verilog environment is a user-friendly environment for designing and verifying digital logic circuits. However, it is hardware independent. The Xilinx WebPack v6.1i Verilog CAD environment in the Laboratory, which is somewhat more elaborate, will be used with the Digilent DigiLab IIE hardware boards featuring the Xilinix Spartan XC2S200E CPLD, a donation from the Xilinx University Program. Question or comments? silage@temple.edu