MIPRO 2011, May 23-27, 2011, Opatija, Croatia

FPGA Implementation of BPSK Modem for Telemetry Systems Operating in Noisy Environments
Pero Krivi, Goran timac
University of Zagreb, Faculty of electrical engineering and computing, 2011 Abstract BPSK modulation is widely used approach in industrial telemetry systems for digital communication over noisy channels due to inherent high noise immunity and low bit-error rate (BER). The most critical part of the BPSK modem implementation in a programmable digital system is the design of demodulator part. We studied characteristics and trade-offs for two commonly used approaches to the BPSK demodulator implementation, which are both suitable for efficient field-programmable gate array (FPGA) implementation: the incoherent BPSK demodulator, based on the complex product demodulation, and the coherent BPSK demodulator, based on the carrier synchronization using internal phase-lock loop (PLL) (Costas Loop) and numerically controlled oscillator (NCO). We employed correlation filter and integrator for symbol synchronization. We compared overall characteristics for both approaches, in terms of robustness in noisy environments and FPGA implementation complexity. Index Terms telemetry systems, BPSK modulation, coherent /incoherent demodulation, symbol synchronization procedure. The FPGA usage for such implementation is significantly lower comparing to the more complex coherent approach, because the process of coherent demodulation includes a carrier synchronization with the internal phase-lock loop (PLL) (Costas loop) and numerically controlled oscillator (NCO). Although the theory describing the operating principles of both demodulators is well known, there are many practical difficulties which arise in practical implementation of mathematical formulas in the FPGA hardware. One possible solution for design and implementation of Costas loop in FPGA technology was developed in [3]. Other approach by using CIC decimator is described in [4]. Some solutions use DSP controllers for target hardware, as in [5]. There are also numerous SoC solutions for implementation of Costas loop, as in [6]. The goal of our research was to develop a working solution for PLC over the DC lines, suitable for a direct FPGA implementation. The main problem that we encountered was the lack of quality documentation and literature which describes all important steps for an efficient BPSK modem implementation in FPGA. We also developed our preamble detection correlation method. We shall first present mathematical background for both approaches, then elaborate our FPGA implementation and provide simulations results where we compare the overall characteristics of both approaches, in terms of the robustness in noisy environments and the FPGA implementation complexity. II. BPSK MODEM MODEL In this section we present the theoretical background, and BPSK modem models, which are necessary to understand the operating principles behind our proposed solutions. The brief overview of both approaches is presented, while the further mathematical details behind each operating principle could be found in relevant references. A. Coherent demodulation 1) Carrier synchronization The first step in the coherent BPSK demodulator implementation is to establish the method for carrier synchronization. To achieve that it is necessary to generate an auxiliary signal with the same phase as the carrier. The carrier synchronization process is based on the Costas loop [2]. Costas loop is a type of the phase locked loop (PLL) that enables a proper phase locking when the modulation signal

I. INTRODUCTION The motivation for our research was to develop the customized digital communication system whose main purpose is to provide means for power-line communication (PLC) over the DC power supply lines. The solution for this problem can be easily adapted to other similar applications, whenever a telemetry system needs to communicate over the noisy channel with AC coupling. An efficient DC power-line communication system with similar goals was previously developed at MIT [1]. The physical communication layer is based on the BPSK (Binary Phase Shift Keying) modulation principle, which exhibits relatively low BER under low SNR conditions [2]. Two well-known demodulation procedures were investigated, namely coherent and incoherent BPSK demodulation. For each demodulation approach the accompanying algorithms suitable for the efficient FPGA implementation were developed. The incoherent demodulation algorithm offers very simple FPGA implementation, while the coherent demodulation approach results in better overall characteristics, but with a price of more complex design implementation. The incoherent approach solves the problem by employing the straightforward complex product demodulation mathematical

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changes its polarity. The block diagram describing the Costas loop is given in Fig. 1 while the more elaborated description of this method is given in [2] and [8].

estimate the time instant when integrator should be reset. The correlation of I & D signal and correlator impulse response is observed, and at the point of the maximum correlation, we can start a bit slicing. The maximum is a consequence of the predetermined preamble of the NRZ signal which carries the useful message.

Fig. 1: The Costas loop block diagram

The goal of the Costas loop is to extract the demodulated signal at the in-phase branch of the loop. The numerically controlled oscillator must generate a sine signal in phase with the input signal to achieve that goal. NCO can be implemented in FPGA using direct digital synthesis (DDS) approach. NCO is controlled via feedback over the loop filter. After multiplying the input signal and the signals from the NCO in I and Q branches, and low-pass filtering the result signal in both branches, there is a signal dependent on the phase difference between the input and the NCO signal. By multiplying filtered signals in I and Q branch, the phase difference is doubled (that is why the multiplier on the right is called phase doubler) and the obtained error signal is used to control the oscillator. The proper design of the loop filter in the feedback of the Costas loop is crucial for success of the demodulation, as discussed in [9]. In this application, we developed the loop filter as a zeroorder filter (gain block). Value for this filter gain is determined by examining the complete system stability in zdomain, as described in [9]. 2) Symbol synchronization The output of the PLL is a demodulated signal, with noisy non-return-to-zero (NRZ) waveform. It is necessary to slice and extract data bits from that signal in order to decode the actual data payload contained in the received message. This can be difficult task in the presence of large noise and the impulse disturbances that could be encountered in noisy industrial environments. The procedure which ensures the accurate reading of the message bits is called the symbol synchronization. Demodulated signal from the Costas loop is taken to the input of the next block Integrate & Dump (I & D). This block behaves as an ordinary integrator, but has a possibility to reset itself. The purpose of the reset is to set an integrator value to the zero at the moments of bit transition. A bit value is then easily determined, inquiring the prefix of the accumulated sum in the integrator, as shown in Fig 2. However, hitting the reset time is a complex process and in fact it is the very essence of the symbol synchronization algorithm. In our solution we employ the correlation to

Fig. 2: The output of the Integrate and dump block

The model of the complete receiver (demodulator, integrator and correlator) was tested and simulated with Matlab, using the Fixed-Point Toolbox. The simulation results in Matlab confirmed expectations of theoretical model, as described further in section IV. B. Incoherent demodulation The incoherent demodulator was implemented by employing the complex product demodulation principle. The received modulated signal Uul (1) (1) is multiplied by a complex exponential Uc (2) (2) with the same frequency as the carrier. The phase difference between these two signals is unknown beforehand. U1 (3) is product from multiplying Uul and Uc . (3) From the resulting signal U1 high frequencies components are removed by means of low-pass filtering. The absolute value (5) of the remaining low-frequency component (4) (4) (5) is calculated to recover the original signal U.

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The behavior of the described incoherent demodulator model was simulated in Matlab. Unwanted transition glitches at the bit boundaries, which manifest as an oscillation, were spotted and corrected by means of low-pass filtering. The simulation revealed that the third order low-pass filter is enough for this purpose. The simulated model gives BER less than 0.1 in the environment with SNR higher than 5 dB. Due to the fact that non-linear distortion does not disturb the system because a binary signal is used, square root method was not implemented to simplify hardware implementation. The incoherent demodulator model is depicted in Fig. 3.

The first step in practical implementation of proposed demodulators was to ensure the proper data acquisition of the received modulated signal. A/D and D/A conversions, and PGA gain programming, were obtained by using the finite state machine. Due to the fact that ADC uses a 34-cycle communication sequence and that the main clock frequency is 50 MHz, sampling rate could not be higher than 1.47 MHz.

Fig. 5: Block diagram of the incoherent receiver Fig. 3: Complex product demodulator block diagram

The Manchester coding for signal was used to keep the model implementation as simple as possible, especially for symbol synchronization task. The preamble detection was achieved by using the simplified correlation filter which is described in III. Two periods of the carrier signal were used to transfer one data bit.

III. FPGA IMPLEMENTATION We developed VHDL modules for implementation of both coherent and incoherent receiver, corresponding to the block diagrams in Fig. 4 and Fig. 5, in the target FPGA hardware. The models were adapted for the implementation in Spartan 3A family. The core of the starter kit board is Xilinx XC3S700A integrated circuit. Beside the denoted FPGA chip, three more components were necessary to complete the realization of the receivers: analog-to-digital converter (ADC), digital-to-analog converter (DAC) and programmable-gain amplifier (PGA). These components are connected to the FPGA chip through the SPI bus interface. More details about the starter kit board Spartan 3A development kit are available in [10] and [11].

The incoherent demodulator process the acquired ADC samples through several blocks, as shown in Fig. 3. For creating I-Q signals, 18x18 multipliers from FPGA chip were used together with numerically-controlled oscillator, described in [13]. This component uses a look-up table stored in the internal block RAM to generate sine and cosine signal. Amplitude resolution is adjusted to 12 bits. Quality of discrete sinusoidal wave is measured with Spurious Free Dynamic Range (SFDR) which was evaluated with 80 dBc. The 14-bit products were filtered using third order low-pass FIR filters in order to eliminate the images from the mixing. After using squaring method on I and Q signals and adding them together, moving average filter is used to remove undesirable oscillations. Moving average filter is built as shift register with adder on each spot. Its output is 15-bit demodulated signal. To retrieve the original message from the demodulated signal, few more VHDL modules are necessary. The finite state machine is the core element for bit synchronization. Logic transition is often used as a help to reconstruct a synchronizing clock. It is important to detect inter-bit transition and not between-bit transition (which occurs at 0-0 and 1-1 pairs). This is accomplished with FSM state where the transition detection is forbidden. This state needs to last more than a half bit and less than a whole bit duration. Transitions are detected with simple derivation logic. Last element is preamble detecting module (Fig. 6). It compares internally stored preamble with bit stream in shift register and looks for maximum (with adjustable threshold), it works as correlation filter. When control logic detects preamble, output buffer is enabled, otherwise it is in high impedance state. For coherent procedure similar VHDL modules were used, with difference in stricter demands on filters and NCO. Therefore NCO from [12] with 16 bit amplitude resolution was used, and it provided 120 dBc SFDR. A FIR filter used in a Costas loop is of fourth order.

Fig. 4: Block diagram of the cohorent receiver

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Fig. 6: Preamble detector in incoherent procedure

IV. RESULTS In this section, the simulation results for both coherent and incoherent procedure are presented. For the coherent procedure, it is necessary to examine the stability criteria of Costas loop first. One must be sure that the loop filter keeps the NCO in a desired working area. For the 1st order Costas loop, like the one that was used in this work, the working area is defined around the fixed frequency with no larger shifts allowed. We show a stable behavior of the loop through a decay of an error signal (Fig. 7). Error signal, as described in section II. A., is the output of the phase doubler, and the input to the loop filter. As we can see from the Fig. 7, the error signal decays to zero, indicating the stability of Costas loop.

Fig. 8: Demodulated BPSK signal at the output of the Costas loop.

These results are a confirmation of a demodulators correct work. Symbol synchronization circuit was tested under conditions of different SNR, bit length, preamble shape and carrier frequency. Finally, a compromise is achieved regarding discussion in V. The system is able to recognize sent message of length up to 100 bits without breaking synchronization. Also, with some set ups, modulation signal with SNR less than -8 dB is possible to recover. Incoherent procedure is much simpler, therefore it needs less hardware resources then coherent one, less hardware resources imply lower power consumption which is often very important element in hardware design. This incoherent procedure can recover message with at least 5 dB SNR with acceptable BER (less than 0.1) . BER is calculated as a function of SNR with a fixed parameter of symbol length. As a discussed in a section IV, symbol length in BPSK communication has a great impact on an accuracy of a message recognition. BER calculations under different symbol lengths are presented in a Fig. 9 and in a Fig. 10 for incoherent procedure. Symbol length is expressed as a number of carrier periods per symbol. Simulation results are in accordance with theoretical expectations described in [2].
-1 -2 -3 -4 -5 BER [10y] -6 -7 -8 -9 symbol length: 10 symbol length: 20

Fig. 7: Error signal at the output of a phase doubler

As a response to a BPSK signal at the input of a receiver, A demodulated signal is provided at the output of In-phase branch of the loop. One example of the demodulated signal is given in Fig. 8. Light oscillations, visible in the figure, here are due to two reasons: added noise in transmission channel and finite attenuation of component on doubled carrier frequency in a FIR filter.

-10 -11 -10

10

20 SNR [dB]

30

40

50

Fig. 9: Bit-error rate with change in parameter symbol length expressed as a number of carrier periods for coherent procedure

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REFERENCE ES
[1] Wade, E. R., DC powerline communication System using a c Transmission Line Transformer for High Degree of Freedom Application, MIT, 2000 ems, 4th edition, 2001. Haykin, S., Communication Syste Yuan, H., Hu, X., Huang, J., Desi and Implementation of Costas ign Loop Based on FPGA, IEEE N Roddewig, M., Zekavat, S. A., Nooshabadi, S., Design of a Costas Loop Down Converter, IEEE Power Line Communication fo Lighting Applications Using or BPSK with a Single DSP Contr roller, Application Report, Texas Instruments, 2006. Digital Costas Loop HSP50210, Datasheet, Intersil, 2008. D R. E. Best, Phase-Locked Loops, McGraw-Hill M D.H. Wolaver, Phase-Locked Circ Design, Prentice Hall, 1991. cuit Hagemann E., Costas Loop, 2001

[2] [3] [4] [5]

[6] [7]

Fig. 10: Bit-error rate with change in parameter sy ymbol length expressed as a number of carrier periods for incoh herent procedure

[8] [9]

G [10] Spartan-3A Start Kit Board User Guide, 2007 [11] Spartan 3A/3AN Starter Kir Board Schematic, 2007 d [12] Dodig I., Power Line Communica ation, 2009.

V. CONCLUSION The idea of our work was to develop an algorithm of efficient BPSK transmission optimized for a FPGA mponent of this implementation. Especially important com project was an adequate simulation or mathe ematical model to describe the actual process of exchanging info ormation between two or more nodes, as well as the implem mentation of the hardware itself. For the theoretical study and simulation was d used Matlab R2009b and for implemen ntation Spartan 3 development interface and software tool Xilin ISE 9.2i. nx Regarding simulation results presented in section IV., we n can derive these conclusions: it is possib to design a ble coherent demodulation with symbol synchron nization processes to establish an effective physical layer of a communication based on BPSK procedure. As it is known, un nder the different SNR conditions, different efficiency, seen through bit-error ow ratio, is achieved. In this work, we showed ho a border of an acceptable BER can be shifted towards lowe levels of SNR. er Modifying symbol length, we can control a success of a bit recognition. With proper preamble wavefor and correlator rm design, it is possible to increase communicat tion efficiency in highly noised environment. Probability of inc correct bit slicing is extremely reduced if we adapt paramet ters like symbol length and preamble shape to the noise leve in the channel. el Doing that, we directly reconfigure preferenc of correlation ces filter and maximum trigger level. In a case of higher noise e levels, enlargement of symbol length enchants BER performances of a communication. Tra ade off to the enlargement is loss in a transmission speed As one of the d. conclusions we can claim that speed is rever rsely proportional to the quality of communication.

[13] Molnar G., FPGA implemen ntacija oscilatora, Zagreb, 2007.

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