NanoPack

www.nanopack.org

Large Scale Integrating IP Project: Nano Packaging Technology for Interconnect and Heat Dissipation
One of the major limitations to continued performance increases in the semiconductor and power electronics industries is integration density and thermal management. Continued transistor downscaling is quickly reaching its limits forcing a new focus on heterogeneous integration and 3D packaging in order to further push performance and density. Improved thermal management and integration densities increase energy and

Complex heterogeneous electronics systems contain multiple interfaces manufacturing efficiency and component reliability. In NanoPack we develop new technologies and materials for low thermal resistance interfaces and Transient thermal electrical interconnects. Modeling and simulation tester (MicReD) techniques with world class supercomputers will be combined with the development of experimental test structures to measure the performance of new interface technologies and validate design tools. Finally the technology will be demonstrated in high power radio frequency switches, microprocessors and hybrid vehicle power electronics. A340/A380 Avionics Computers

Three parallel approaches will be pursued to improve thermal and electrical performance: Enhancement of bulk conductivity of filled systems, reduction of bondline thickness, and optimization of nanoscale thermal and electrical contact surfaces.

NANOPACK Technology Base Bulk Conductivity

Higher particle fill New materials

Thickness
Reduce bondline Improve planarity

Nanoscale Optimization
Surface coatings Phonon coupling

Simulation of micro- and nanoscale structures Evaluation of materials and test systems Application of technology to demonstrators

Nanopack fills several gaps reported by the ITRS roadmap and covers several ENIAC strategic research agenda focus topics in the heterogeneous integration area. The NanoPack consortium consists of 4 major industrial partners, 4 innovative SMEs, and 6 academic groups in total representing 8 European countries: Thales Research and Technology, Paris, France (coordinator) Berliner Nanotest and Design GmbH, Berlin, Germany Budapest University of Technology and Economics, Budapest, Hungary Catalan Institute of Nanotechnology, Bellaterra, Spain Chalmers University of Technology, Gothenburg, Sweden Electrovac AG, Klosterneuburg, Austria Foab Electronic AG, Hisings Backa, Sweden Fraunhofer Insititut IZM, Berlin Germany IBM Zurich Research Laboratory, Rschlikon, Switzerland Institut dElectronique de Microtechnologies et de Nanotechnologie, Lille, France MicReD Ltd. Budapest, Hungary Robert Bosch GmbH, Stuttgart, Germany Thales Avionics, Paris, France VTT Micro and Nanoelectronics, Espoo, Finland

BME

Background picture: Fractal interface from thermal cycling of a particle filled paste interface as seen in a phase contrast microscope