Intro To SystemVerilog

SystemVerilog for Verification

Day One

Welcome
Welcome to the Intro to SystemVerilog for Verification class Requirements
Some HDL programming experience Some Unix experience Familiarity with some Unix editor Unix account in Folsom, Chandler, Dupont, or Penang.

Assumes use of Modelsim.

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Scope Of Course
Introduction to SystemVerilog for verification Hands-on lab assignments Students will not be SystemVerilog experts at the end of this class. Class is an introduction only. Advanced classes go into more details.
Next Classes: Functional Coverage/Temporal language/Checkers How to write a SV Test How to write an SV BFM

Length: 2 days
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Typographic Conventions
Regular Text Courier Bold Course Content Code examples, command line keyboard input Screen output Placeholders for data user should input
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Courier Regular Italic

What is SystemVerilog
SystemVerilog is an IEEE extension to the Verilog language. SystemVerilog adds testbench features such as classes, constraints, and temporal expressions to Verilog.

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Getting More Information

SystemVerilog LRM
http://www.eda.org/sv/SystemVerilog_3.1a.pdf

AVC Wiki
http://wwwfmec.fm.intel.com/twiki/bin/view/Chipset/SystemVerilog

Comprehensive information on SV:

http://carmel.fm.intel.com/sites/CPDCDTG/DATE/FEDAO/SystemVerilog%20Deployment%20Doc %20Lib/Forms/AllItems.aspx

Additional Information
www.accellera.org
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Using SystemVerilog
To setup your environment to use SystemVerilog, type the following at the unix prompt:

% source <local site specific setup

script>

Next, create a training directory, and create a work library:

% mkdir svtraining; cd svtraining % vlib work % vmap work work

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Hello World
module helloWorld(); initial begin: hello $display("Hello World"); end: hello endmodule: helloWorld

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Compiling SystemVerilog
To compile your program, type the following:
% vlog hello.sv

Note: If you do not name your file ending in .sv, you must use the sv option to vlog. To run your program, use the following command:
% vsim -c -do "run -all;q -f" helloWorld
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Commenting Your Code

Like C++, SystemVerilog supports two types of comments
/* Block comments that can span * multiple lines */ // And single line comments $display(hello); // This is a comment

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Lab 1: Hello World

Create a module that prints Hello World using the $display command.

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Basic Data Types

Integer Data Type

shortint int longint byte bit logic reg integer time 2-state (1, 0), 16 bit signed 2-state, 32 bit signed 2-state, 64 bit signed 2-state, 8 bit signed 2-state, user-defined vector size 4-state (1,0,x,z) user-def 4-state user-defined size 4-state, 32 bit signed 4-state, 64 bit unsigned

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Signed/Unsigned
byte, shortint, int, integer and longint defaults to signed
Use unsigned to represent unsigned integer value
Example: int unsigned ui;

bit, reg and logic defaults to unsigned To create vectors, use the following syntax:
logic [1:0] L; // Creates 2 bit logic // vector

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Strings
string dynamic allocated array of bytes SV provides methods for working with strings Str1 == Str2 Str1 != Str2 <, <=, >, >= {Str1, Str2, Strn} Str1[index] Equality Inequality Comparison Concatenation indexing return 0 if out of range
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String Methods
len putc getc toupper tolower compare icompare substr atoi, atohex, atoct, atobin atoreal itoa hextoa octtoa bintoa realtoa

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Literal Values
Integer Literal Same as verilog
value unsized decimal value sizebase value sized integer in a specific radix Ex: 4b0101; 4hC; 32hDEAD_BEEF; 2b1Z

Real Literal
value.value Ex: 2.4 Base Exponent ( E/e)

Logic Value
0, 1, [z|Z], [x|X]
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Lab 2: Data Types

Write a top level module that displays the following output. Use of the following data types: 1. int both signed and unsigned 2. logic 3. string
int i, h; $display(%d %h, i, h); string str; $sformat(str, %b, l) $display(Logic value in upper case %s,str.toupper());

Hint:

Output: # The integer i is 0x00000014 # The unsigned integer ui is 0xdeadbeef # The logic L is 1Z # string str1 is "Hello World" # string str2 is "Cruel World

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Operators
Logic Operators
& + | ~ % ^ / ~& * ~| ~^ << >>

Arithmetic Operators
** <<< >>>

Assignment Operators
= += -= *= /= %= &= |= ^= <<= >>= <<<= >>>=

Example: a += 3; Equivalent to: a = a + 3;

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Operators
Auto-increment (++) Auto-decrement(--)
Example: a = 1; a++; a now contains 2.

Comparison Operators
== != === !== =?= !?= > < <= >= Example: a = 1'bZ; b = 1'bZ; if (a != b) $display(Z != Z); if (a === b) $display(Z === Z);
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Concatenation
The { } operator is used for concatenation. Example:
s = {Hello, , World}; v = {32b1, 32b10}; // v = 64b vector

Can also be used on left hand side:

{a, b, c} = 3b111;

Sizes of assignment have to match. If LHS is smaller then assignment gets truncated.
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Lab 3: Operators
Write a SystemVerilog module to calculate the following, and print the result as an integer to the screen:
(1101001 XOR 11111001) 5 Ignore remainder.

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Flow Control Constructs

How to go with the flow

SystemVerilog additions
Verilog includes: if-(else-(if)), case, forever, repeat, while, for, ?: (ternary) SystemVerilog:
Enhances for Adds do..while, foreach

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if
Verilog if expressions Then branch taken for any nonzero known value of expr (no x or z), equivalent to expr != 0 Chain if statements:
if (expr) begin end else if (expr) begin end else begin end

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?:
Operator, but conditional
expr ? then_val : else_val

Some call this the ternary operator, in the same vein as unary and binary, with 3 operands. Ex: var_m = (x == 1) ? a : b;

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case
4-value exact matching, runtime evaluation, no fallthrough, bit length of all expressions padded to same length
case (expr) item: begin statement end item2, item3, item4: begin statement end default: statement endcase
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casez, casex
Handle wild cards with either casez or casex casez: z bit in either item or expression will be treated as a match for that bit casex: z or x bits will both match
casex (8bx100z011 ^ reg_a) 8b1x1001?1: $display(x); 8b01z10zx1: $display(y); 8b11z01011: $display(z); endcase

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forever
Continuous execution, without end, of body statement(s) Used with timing controls Usually last statement in some block initial : clock_drive begin clk = 1b0; forever #10 clk = ~clk; end : clock_drive
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repeat
Repeat a block x times, no conditional test
repeat (expr) statement

What happens with expr = x or z? Example

x = 0; repeat (16) begin $display(%d, x++); end
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while
Executes statement as long as expr evaluates to true

while (expr) statement

Example:

while (reg_i) begin something_happens(); reg_i = reg_i 1; end

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for
C inspired for loop
for (initial_assignment; condition; step_assignment) statement

Equivalent to
begin initial_assignment; while (condition) begin statement; step_assignment; end end
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Enhanced for
SystemVerilog adds:
Loop variable declaration Multiple statements in init and step blocks (comma separated) ++ and -- operators (Mentioned in operator section)
for (int i; i < arr.size(); j+=2, i++) begin arr[i] += 200; arrb[i]--; end

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do..while
do statement while (expr); Whats the difference?
x = 0; 1) while (x) begin $display(%d, x); x--; end 2) do begin $display(%d, x); x--; end while (x);

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Lab 4: Flow control

Write a SystemVerilog module to display the first 20 Fibonacci numbers. Fn = Fn-1 + Fn-2 Hint: F1 = F2 = 1

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User Defined Types and Enumerated Types

User Defined Types

SystemVerilog supports a new keyword: typedef Syntax: typedef <base_data_type> <type_identifier>
// inch becomes a new type // these are 2 new variables of type inch

typedef int inch ; inch foot = 12, yard = 36;

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Copyright 2005 Mentor Graphics Corporation

Enumeration
Syntax: enum [enum_base_type] { enum_name_declaration {,enum_name_declaration} } enum_base_type: default is int Enumeration is a useful way of defining abstract variables.
NOTE:

Define an enumeration with enum enum {red, green, yellow} traf_lite1, traf_lite2; Values can be cast to integer types and auto-incremented enum { a=5, b, c} vars; // b=6, c=7

Default assigned values start at zero 0 1 2 enum {red, green, yellow} lite;

A sized constant can be used to set size of the type enum bit [3:0] { bronze=4h3, silver, gold} medal; // All medal members are 4-bits Define a new type typedef enum {NO, YES} bool; // bool is NOT a SystemVerilog type bool myvar; // but it just became one
myvar will now be checked for valid values in all assignments, arguments and relational operators
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Enumeration example
Modelsim now allows viewing of enum types in waveforms similar to VHDL enum types. To use enumerated types in numerical expressions the language provides the following functions: prev(), next(), first(), last(), num() and name().

Example
typedef enum {red, green, blue, yellow, white, black} Colors; Colors col_ps; Colors col_ns; always @(col_ps) col_ns = col_ps.next(); always @(posedge clk) col_ps <= col_ns;

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Casting

Casting
A data type can be changed by using a cast () operation. Syntax: <type>(<value/expression>) Examples:
int(2.0 * 3.0)// real to int casting 7(x-2)//number of bits to change size. signed(m)//changes m to signed inteltype(2+3)//casting to a user defined type [inteltype].
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Arrays

Packed/Unpacked Arrays
In packed arrays [range is on the left side of the identifier] all elements are glued together and can be overwritten by zero/sign extension of a single literal.
Ex: logic [3:0] m; m = 4b1100;

In unpacked arrays [range is on the right side of the identifier] each individual element is considered by itself without any relation to other elements.
Ex: logic m [5:0]; // each element is only 1-bit deep Ex: logic [3:0] m [5:0]

Arrays can have packed and unpacked dimensions.

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Array Literals and Default

To help in assigning literal values to arrays SV introduces the default keyword:
int k [1:1000] = '{default: 5}; // All elements 5

For more control, consider the dimensions of the array and use { } to match those dimensions exactly.
int k [1:3][1:4] = '{'{1,2,3,4},'{5,6,7,8},'{9,10,11,12}};

// 3 groups of 4

int m [1:2][1:3] = '{'{0,1,2},'{3{4}}};

// 2 groups of 3

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Dynamic Arrays
Syntax: data_type array_name[] ;

1st new array in SV, not synthesizable

Dynamic declaration of one index of an unpacked array

Declares a dynamic array array_name of type data_type

data_type array_name[] = new[ array_size ] [(array)] ;

Allocates a new array array_name of type data_type and size array_size Optionally assigns values of array to array_name If no value is assigned then element has default value of data_type

Examples:

bit [3:0] nibble[ ]; integer mem[ ]; int data[ ]; data = new[256]; int addr = new[100]; addr = new[200](addr);

// Dynamic array of 4-bit vectors // Dynamic array of integers // Declare a dynamic array // Create a 256-element array // Create a 100-element array // Create a 200-element array // preserving previous values in lower 100 addresses
Copyright 2005 Mentor Graphics Corporation

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Dynamic Arrays Methods

function int size() Returns the current size of the array int addr[ ] = new[256]; int j = addr.size(); // j = 256

function void delete() Empties array contents and zero-sizes it int addr[ ] = new[256]; addr.delete();
Cannot delete selected elements

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Dynamic Array Example

module dyn_arry (); bit data1 []; initial begin // create a 128 element array data1 = new [128]; $display("Size of array = %d", data1.size()); data2 = new[256](data1); $display("Size of array = %d", data2.size()); data1.delete(); $display("Size of array = %d", data1.size()); end endmodule

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Queues and Lists

3rd new array in SV, not synthesizable

SV has a built-in list mechanism which is ideal for queues, stacks, etc. A list is basically a variable size array of any SV data type. int q1[$]; int n, item; q1 = { n, q1 }; q1 = { q1, n }; item = q1[0]; item = q1[$]; n = q1.size; q1 = q1[1:$]; q1 = q1[0:$-1];
// $ represents the upper array boundary

// uses concatenate syntax to write n to the left end of q1 // uses concatenate syntax to write n to the right end of q1 // read leftmost ( first ) item from list // read rightmost ( last ) item from list // determine number of items on q1 // delete leftmost ( first ) item of q1 // delete rightmost ( last ) item of q1 // step through a list using integers (NO POINTERS)

for (int i=0; i < q1.size; i++) begin end q1 = { };

// clear the q1 list

Copyright 2005 Mentor Graphics Corporation

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Queue Methods
size() insert() Returns the number of items in the queue. If the queue is empty, it returns 0. Inserts the given item at the specified index position. Q.insert (i, e) => delete() Q = {Q[0:i-1], e, Q[i,$]} Prototype: function int size(); Prototype: function void insert (int index, queue_type item); Prototype: function void delete (int index); Prototype: function queue_type pop_front(); Prototype: function queue_type pop_back(); Prototype: function void push_front (queue_type item); Prototype: function void push_back (queue_type item);

Deletes the item at the specified index position. Q.delete (i) => Q = {Q[0:i-1], Q[i+1,$]}

pop_front()

Removes and returns the first element of the queue. e = Q.pop_front () => e = Q[0]; Q = Q[1,$]

pop_back()

Removes and returns the last element of the queue. e = Q.pop_back () => e = Q[$]; Q = Q[0,$-1]

push_front()

Inserts the given element at the front of the queue. Q.push_front (e) => Q = {e, Q}

push_back()

Inserts the given element at the end of the queue. Q.push_back (e) => Q = {Q, e}

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Copyright 2005 Mentor Graphics Corporation

Queue Example
module queues (); int q [$]; // declare the q initial begin: store_disp Push elements into the queue q.push_back(1); q.push_back(0); Display its contents $display("Size of queue = %0d", q.size()); Delete the element of queue at index 1 q.delete(1); Push to front of the queue q.push_front (0); Display all the contents in the queue for (int i = 0; i < q.size(); i++) $display("q[%0d] = %0d", i, q[i]); end: store_disp

//

// // // //

endmodule: queues
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Lab 6: Queues
Write a SystemVerilog program with specification as defined in lab6.sv The output will look as follows: # Loading work.lab6 # run all # Size of queue = 3 # q[0] = 0 # q[1] = 1 # q[2] = 3 # q -f
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Associative Arrays
Associative arrays are used when the size of the array is not known or the data is sparse. Syntax: data_type array_name [index_type]; In other words value_type array_name [key_type]; It implements a lookup table of the elements of its declared type. Data type used as an index serves as lookup key and imposes an order. Associative array do not have their storage allocated until it is used.

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Index Types
String Index Types
Ex: int a [string]; a[joe] = 21;

Integer Index Types

Ex: bit [1:0] a [int]; a[5] = 2b11;

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Associative Array Methods

Function
num() delete(<index>)

Use
Returns number of entries Index for delete optional. When specified used to delete given index else whole array. Returns 1 if element exists at index else 0 assigns to the given index variable the value of the first/last (smallest/largest) index in the associative array. It returns 0 if the array is empty, and 1 otherwise. finds the entry whose index is greater/smaller than the given index.

exists (<index>) first (<index>), last (<index>)

next (<index>), prev (<index>)

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Associative array methods - Example

module asoc_arry (); int db [string]; // Define an associative array initial begin: test string s; db ["joe"] = 21; // store values at indexes of associative array db ["jill"] = 19; // Display the size of the associative array $display("Size of hash = %0d", db.num()); if (db.exists("jill")) // check if index exists and change value begin db["jill"] = 25; end // print the contents of associative array if (db.first(s)) do begin $display("Name = %s -- Age = %0d", s, db[s]); end while (db.next(s)); end: test endmodule: asoc_arry Intel Confidential 56

Lab 7: Associative Arrays

1.

Define an associate array named 'assoc'

assoc has the following attributes: INDEX - Name of person VALUE - Age

2.

Make the following entries into assoc

NAME AGE ---------------John 25 James 30 Jane 24

3. 4.

Display the size of the hash using $display statement Check if name Jane exists in the associative array and if it does

change her age to 40.

5.

Print the contents of the associative array.

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Procedural Blocks

Triggering sensitivity
@(<signal>) waits for an edge on <signal> before executing the next statement Edge-sensitive signal detection @(posedge clk) waits for a rising edge clock @(negedge rstb) waits for a falling edge on rs wait(<signal>) waits for a condition to become true before executing the next statement. Level-sensitive signal detection If the signal is already true, execution continues without stopping

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Initial Block
An initial block starts at time 0, executes exactly once during a simulation, and then does not execute again. If there are multiple initial blocks, each block starts to execute concurrently at time 0. Each block finishes execution independently of other blocks. Multiple behavioral statements must be grouped, typically using begin and end.

Example
module stimulus; reg a,b; initial begin #5 a = 1b1; #25 b = 1b0; end endmodule

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Always Block
The always block statement starts evaluating sensitivity list at time 0 and executes statements in the always block continuously in a looping fashion. This statement is used to model a block of activity that is repeated continuously.
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Example
module clock_gen; bit clock; initial begin clock = 1b0; forever #10 clock = ~clock; end always @(posedge clk) begin <statements>; end endmodule

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Final Blocks
The final block is like an initial block, defining a procedural block of statements, except that it occurs at the end of simulation time and executes without delays. A final block is typically used to display statistical information about the simulation.
Example final begin $display("Number of cycles executed %d",$time/period); $display("Final PC = %h",PC); end

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Lab 8: Procedural Blocks

Create a SystemVerilog module: 1. Define an initial block such that it generates a clock clk time period = 10ns NOTE: Need to initialize clock even though the bit data type is automatically done. 2. Create an always blocks that stores the value of signal 'clk' into queue 'q' at positive edge of the clock. 3. Increment 'counter' when always block is triggered 4. When counter reaches 4 call $finish system call Hint: Use if statement 5. Define a final block to print the size of 'q' at the end of simulation Hint: Use final blocks Output: # Size of q = 4

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Types of Assignment
Blocking Nonblocking

Blocking Assignment
The simulator completes a blocking assignment (=) in one pass [execution and assignment]. Execution flow is blocked until a given blocking assignment is complete. If there is a time delay on a statement then the next statement will not be executed until this delay is over.
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Example
initial begin a = 30; #10; a = 5; c = #10 a; b = 2; end // at time 0 a = 30 //at time 10 a = 5, b = x, c = x // at time 20 a = 5, b = x, c = 5 // at time 20 a = 5, b = 2, c = 5
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Nonblocking Assignment
The simulator completes a nonblocking assignment (<=) in two passes.
Right-hand side of the assignment is sampled immediately. Assignment to the lefthand side is postponed until other evaluations in a given simulation time step are complete.
Example
initial begin a = 30; #10; a <= 5; c <= #10 a; b <= 2; end // at time 0 a = 30 //at time 10 a = 5, b = 2, c = x // at time 20 a = 5, b = 2, c = 30
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Tasks and Functions

Tasks
SystemVerilog makes a number of extensions to basic Verilog syntax.

automatic tasks allocate memory dynamically at call time.

Default port direction is input ANSI style portlists

Implied beginend

task automatic my_task( input int local_a, int local_b); if (local_a == local_b) Arguments can be ANY begin SV type, even structs, etc. my_task(local_a-1,local_b+1); return; // end this copy of task end global_a = local_a; return keyword is supported and global_b = local_b;
terminates task at that point

endtask

Full recursion is supported (automatic variables/arguments stored on stack) Can do concurrent calls Can do recursive calls
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Task usage examples [1]

Example of a static task
module task_reentry(); task reentry(); int counter = 0; counter++; counter++; counter++; counter++; counter++; $display("Value of counter = %0d", counter); endtask initial begin reentry(); reentry(); reentry(); reentry(); end endmodule: task_reentry

Example of an automatic task

module task_reentry(); task automatic reentry(); int counter = 0; counter++; counter++; counter++; counter++; counter++; $display("Value of counter = %0d", counter); endtask initial begin reentry(); reentry(); reentry(); reentry(); end endmodule: task_reentry

What will be the value of counter for each call to reentry()?

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What will be the value of counter for each call to reentry()?

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Task usage examples [2]

module task_function (); int i, j, z; initial begin i = 5; j = 3; end initial begin #10; tsk (i, z, j); $display("Z = %0d, J = %0d", z, j); // prints Z = 50, J = 4 end task tsk (input int t1, output int t2, inout int t3); t2 = 10 * t1; t3++; endtask: tsk endmodule
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Functions
automatic functions allocate memory dynamically at call time (full recursion). Default port direction is input (also supports output) ANSI style portlists Implied beginend

function automatic int factorial (int n); if (n==0) return(1); // factorial 0 is 1 else return(factorial(n-1)*n); endfunction

Arguments and return type can be ANY SV type, even complex structs, etc.

return(value) is supported and terminates function at that point

function void inverta(); a = !a endfunction reg a;

Return type of void means no return value! Recommended style (instead of writing a task) to guarantee a task executes with 0 delay.

initial inverta(); // function called like a task

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End
Copyright 2005 Mentor Graphics Corporation

Function usage examples

Example 1
function void show_packet(); $display("=================="); $display("Packet Type = %s", context_name); $display("Address = %h", addr); $display("Data = %h", data); $display("==================="); endfunction

Example 2
typedef enum {FALSE, TRUE} bool; bool cache_range; function bool is_cache_range (); if (addr > 0 & addr < 10) begin cache_range = TRUE; $display("addr in cache range = %d", addr); return TRUE; end else begin cache_range = FALSE; return FALSE; end endfunction

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Task and Functions Usage - Summary

Tasks Tasks can enable other tasks and functions Tasks may execute in non-zero simulation time. Tasks may have zero or more arguments of type input, output and inout. Functions Function can enable other functions only. Task cannot be called from functions. Functions should execute in zero simulation time. Functions have only one return value but SystemVerilog also allows functions to have input, output or inout types. Both tasks and functions support passing arguments by reference. By default arguments are passed by value. [Pass by reference not supported in Modelsim 6.1]

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Task and function argument passing

Passing by value is the default mechanism for passing arguments. Copies arguments passed into subroutine area. Changes to arguments in subroutine are not visible outside. When defined as automatic, each copy retains a local copy of argument.
Example
function int val (byte m [3:0]); <function body>; endfunction // a local copy of m is // created when val is // called.

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Default argument values Tasks/Functions

SV allows a subroutine declaration to specify default value for each argument. When subroutine is called, arguments with default values can be omitted from the call and corresponding default values are used. BKM: Default arguments should be optional arguments and should be the final set of arguments.

Example
task read (int j =0, int k,int data = 1); endtask // task can be called using // following default arguments read (, 5); // equivalent: read (0, 5, 1) read (2, 5); // equivalent: read (2, 5, 1) read (); // error since k has no default // value

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Lab 9a
Create a SystemVerilog module as described below:
1. 2. 3.

4. 5.

Define a queue 'q' of string type. Define a named initial block "store_info" Store the following values into the queue 1. index =0, str = "Intel Chandler" 2. index =1, str = "Intel Folsom" Display the size of the queue. Define a function named "change_str" which does the following: 1. Takes queue and index value as input 2. changes the value of str stored in queue at index 1 to "Intel Ireland" from "Intel Folsom. 3. returns the value of 1 indicating success.
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Lab 9b
6.

Define a task named show" which does the following:

1. 2. 3.

7.

q[%0d] = %s" Notes: "change_str" and show" are called from named initial block "store_info".
# # # # # #

Takes queue and return value from "change_str" as inputs The default inital value [task input argument: ret_value] shall be set to 0. When the return value from "change_str" function is 1, prints the elements stored in the queue using the following format:

Output:

Loading work.lab9 run all Size of storage q = 2 q[0] = Intel Chandler q[1] = Intel Ireland q -f

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Hierarchy
Who comes first

Modules
The basic hardware unit in Verilog. Hierarchy of design Ports represent communication
Inout Inputs Module Outputs

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Ports
Connections
Direction input, output, inout Type wire, bit, logic, user-defined, etc.

Examples:
input bit[3:0] x, y, z; input bit w[3:0]; output logic q; inout logic s; input int x; output reg r;

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Module syntax
module x (port_list); module_body endmodule : x Instantiation x x1 (port_binding_list);

Example
module cpu (inout logic[63:0] data, output logic[63:0] addr, output logic w_or_rb ); initial begin : place_holder $display(A NOTHING CPU); end : place_holder endmodule : cpu // Error prone cpu cpu_inst1(addr, data, w_or_rb); // Better cpu cpu_inst2(.addr(addr), .data(data), .w_or_rb(w_or_rb) ); // Newer cpu cpu_inst3( .* );

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Parameters
Generic parameters (ala VHDL generics) Elaboration time constants Separate ports on a module Example
module xyz #(parameter int width = 8) (input x[width-1:0], output y)); assign y[width-1:0] = x[width-1:0]^ 8hAE; endmodule xyz #(.width(14)) xyz1 (.x(inp), .y(outp));

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Multiple drivers
Most nets have only one driver Nets with multiple drivers need to have a resolution function In SystemVerilog there is a wire type that includes a resolution function Example
wire x; dut dut1(.outp(x)); dut dut2(.outp(x));
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Interfaces
Great coding efficiency can be achieved by modeling the blocks of a system at different levels of abstraction, behavioral, rtl, gate, etc. In Verilog, the I/O between these blocks has always remained at the lowest wire level. High-performance system-level simulation requires the abstraction of inter-block communication.
module mmu(d, a, rw_, en); output [15:0] a; output rw_, en; inout [7:0] d; ... endmodule module mem(d, a, rw_, en); input [15:0] a; input rw_, en; inout [7:0] d; ... Traditional endmodule Verilog module system; wire [7:0] data; wire [15:0] addr; wire ena, rw_; mmu U1 (data, addr, rw_, ena); mem U2 (data, addr, rw_, ena); endmodule interface interf; logic [7:0] data; logic [15:0] addr; logic ena, rw_; endinterface module mmu(interf io); io.addr <= ad; ... endmodule module mem(interf io); adr = io.addr; ... endmodule SystemVerilog module system; interf i1; mmu U1 (i1); mem U2 (i1); endmodule
Copyright 2005 Mentor Graphics Corporation

data

MMU

ad

addr rw_ ena

adr

MEM

interface

At its simplest an interface is like a module for ports/wires

8-84 SV for Verification Using Questa: Functional Coverage

IO Abstraction
source
reg a; a = 0;

sink

a
if ( a == 1)

Traditional Verilog approach Simple netlist-level IO source/sink can be abstracted but IO must stay at low level IO operations are cumbersome Simple bundle interface All accesses are through interface Simplifies source/sink declarations

source
intf.a = 0;

interface intf

sink
if ( intf.a == 1)

reg a;

source
intf.wrt_a(0);

interface intf

sink
if (intf.rd_a() == 1)

reg a;

task wrt_a(); task rd_a();

Enhanced interface with methods source/sink only call methods source/sink dont see low-level details like variables/structure, etc. Easy to swap interface abstractions without any effect on source/sink
Copyright 2005 Mentor Graphics Corporation

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Interface Characteristics
Interfaces bring abstraction-level enhancements to ports, not just internals. An interface may contain any legal SystemVerilog code except module definitions and/or instances. This includes tasks, functions, initial/always blocks, parameters, etc. Bus timing, pipelining, etc. may be captured in an interface rather than the connecting modules. Interfaces are defined once and used widely, so it simplifies design. e.g. Changing a bus spec (add a new signal?) means editing the interface only. Interfaces are synthesizable.

8-86 SV for Verification Using Questa: Functional Coverage

Copyright 2005 Mentor Graphics Corporation

Interface in hierarchy
Interfaces appear as normal module instantiations in design hierarchy. At the moment, interfaces cannot be instantiated in VHDL blocks.
Interface instances interface name: bfm_interface Instantiated twice: bi1, bi2

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modport
Different users of interface need different views
Master/Slave

Example
interface i2; wire a, b, c, d; modport master (input a, b, output c, d); modport slave (output a, b, input c, d); endinterface : i2 module m (i2.master i); endmodule: m module s (i2.slave i); endmodule: s module top(); i2 i(); m u1(.i(i.master)); s u2(.i(i.slave)); endmodule: top
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Restrict access to internal interface signals

Protect implementation signals from corruption

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Lab 10
Create modules moda and modb. moda has an input named a, and an output named b modb has an input named b, and an output named a Use an interface to connect

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Clocking blocks
Synchronous blocks can have race conditions when all trying to evaluate blocks in same time step Clocking blocks capture timing and synchronization requirements

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Clocking block syntax

clocking block_name clocking_event; item list; endclocking : block_name

clocking bus @(posedge clock1); default input #10ns output #2ns; input data, ready, enable=top.mem1.enable; output negedge ack; input #1 addr; endclocking
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Program Blocks
A program block is similar to a module. It is used for testbench code.
program helloWorld(); initial begin: hello $display("Hello World"); end initial begin: there $display(Hello There); end endprogram: helloWorld
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Program Blocks
Programs can be instantiated inside modules, but not the other way around. Program blocks may contain one or more initial blocks, but may not contain always, UDPs, modules, interfaces, or other programs. Programs may be explicitly exited using the $exit task. When all program blocks complete the simulation ends.
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Day Two

Classes
SystemVerilog and Object Oriented Programming Testbench Only

Object Oriented Primer

A Class is a description of some group of things that have something in common. Objects are individual instances of classes.

Objects/Classes have:
Data Operations/Methods

Example: A class might be Automobile. Instances of the Automobile class might be Joes car, Bobs car, Sallys truck, etc.

Color, speed, direction, etc.

Start, stop, increaseSpeed, turn, etc. Encapsulation:

Encapsulate implementation details internal to the object/class.

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Classes
Inheritance: (is-a relationship)
Allows users to extend existing classes, making minor modifications. Extending the Automobile class example, users might create subclasses for sedan, truck, van, etc. The van class might also have a minivan subclass. Etc. In these cases, the subclass IS-A superclass. i.e. a sedan is a Automobile. When using inheritance, the sub-class inherits all the parents public/protected data properties and methods. It is allowed to override them, or use them as-is.

Composition: (has-a relationship)

Composition is used for the case where one object HAS-A instance of another class. For example, an Automobile class might have 4 instances of a wheel class. In this case, a wheel is not an Automobile, so inheritance should not be used.
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Classes
Polymorphism:
Most common definition of polymorphism is the ability of the language to process objects differently depending on their data type or class. SystemVerilog can only process objects differently depending on their class.

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Class Format
class classname [extends superclass]; property declarations; constructor; methods; endclass: myPacket

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Example Class
class myPacket extends BasePacket; // inheritance byte data[$]; bit [3:0] command; function new(); command = IDLE; data = {1,2,3,4}; endfunction: new virtual task myTask(input byte a, output byte b); #10; b = a + 5; endtask: myTask; virtual function integer myFunc(int b); return(b 3); endfunction: myFunc endclass: myPacket

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Referencing Properties and Methods

Instance data properties and methods may be referenced/called using the . operator.
c = new; c.property1 = 10; c.property2 = 11; c.task1(); c.function1();

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Constructors
Example constructor
function new(); command = IDLE; data = {1,2,3,4}; endfunction: new // Creating an instance invokes the constructor: myInstance = new;

Constructors may take arguments.

function new(int a = 0, bit[12:0] addr = 0); endfunction: new

When extending a class constructor, call super.new().

function new(); super.new(); endfunction: new

Only one constructor per class allowed.

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this
The special variable this is a predefined object handle for the current object instance. It is optional, since the current instance is assumed if no variable is specified.
class myPacket extends BasePacket; int x, y, z; virtual function integer myFunc(); x = y + z; // Equivalent: this.x = this.y + this.z; myOtherMethod(); // Equivalent to: this.myOtherMethod(); endfunction: myFunc endclass: myPacket

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Static Properties
Static properties/data members are static to all instances of the class. This means that all instances share the same value of this variable. If one instance changes the value, it changes the value for all instances.
class StaticExample; static int staticProperty = 0; virtual function void showStaticProperty(); $display(Current value: %d,staticProperty); endfunction: showStaticProperty virtual function void setStaticProperty(int val); staticProperty = val; endfunction: setStaticProperty endclass: StaticExample

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Static Methods
Static methods do not require an instance of the class to operate on. Static methods may only modify static properties. To invoke a static method, use Classname::methodName
class StaticExample; static int staticProperty = 0; static function void staticMethod(); endfunction: staticMethod endclass: StaticExample StaticExample::staticMethod();

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Polymorphism
Instances of subclasses may be assigned to variables declared of the superclass type. This is useful for cases where the general algorithm is the same for all the subclasses, but only a few details need to change. If the subclass overrides a method specified in the superclass, the method defined in the class of the object instance is called.

class BaseClass; virtual function in myFunc(int b); return(b + 10); endfunction myFunc endclass: BaseClass class myFirstClass extends BaseClass; virtual function int myFunc(int b); return(b 3); endfunction: myFunc endclass: myFirstClass class mySecondClass extends BaseClass; virtual function int myFunc(int b); return(b + 3); endfunction: myFunc endclass: mySecondClass BaseClass bc; // Returns an instance myFirstClass bc = getFirstClassInstance(); $display(What do I print? %d ,bc.myFunc(6)); // Returns an instance mySecondClass bc = getSecondClassInstance(); $display(What do I print? %d ,bc.myFunc(6));
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Data Hiding and Encapsulation

To make data members visible only to the class, use the local keyword.
class myPacket extends BasePacket; local int x;

To make data members visible only to the class, or any subclasses, use the protected keyword.
class myPacket extends BasePacket; protected int x;

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Constant Class Properties

The const keyword may be used to make class properties unchangeable. const constants are different from ` define constants because the initial value may be determined at runtime, and may be different per class instance.
class myPacket extends BasePacket; const int size; // Assignment of constant value in // declaration makes it constant // to all instances. function new(int id); size = id * 4096; // Single assignment in // constructor OK

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Abstract Classes
The virtual keyword may be used on a class to make the class abstract. An abstract class may not be instantiated. Users must subclass the abstract class to create instances of the class.
virtual class BasePacket;

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Typedef Class and Forward References

Sometimes it is necessary to use a class before it has been defined. To do this, you can use a typedef forward reference, then later define the class. Example:
typedef class C2; // Forward declaration of C2 class C1; C2 c2Instance; endclass: C1 class C2; C1 c1Instance; endclass: C2
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Lab 11a: Classes

Create an Xaction class. The Xaction class should have the following Properties:
byte int data[$]; // Queue of bytes length; // Length in bytes

Methods:

// Sets data to value passed and // length to the size of queue passed. setData(byte d[$]);

// Returns formatted representation of // xaction. Format should be: // Len=X, Data=0xXXXXXXXX string toString();

Hint: $sformat(str,"Len=%d,
Xaction x;

DATA=0x%h",length,data);

Using your new class, run the following test code.

x = new; x.setData({1,2,3,4,5,6,7,8}); $display(%s,x.toString());

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Lab 11b: Classes

Modify lab10a and create a subclass of the Xaction class that has the following property added:
int iws; // Initiator wait states // Wait IWS time steps stall();

Add a task to the class that waits for the number of time steps specified in iws: Override the toString() method, add printing the iws value. Be sure to use super.toString, and not reimplement the toString of the parent class:
// Len=X, Data=0xXXXXXXXX, IWS=X

Execute the following testcode.

Xaction x; SubXaction s;

s = new; s.iws = 10; $display(current time = %t,$time); s.stall(); $display(current time = %t,$time); x = s; x.setData({5,6,7,8}); $display(%s,x.toString());

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Virtual Interfaces
Classes cannot have modules or interfaces, need a specialized mechanism Virtual interfaces provide a mechanism for separating test programs/BFM models from the actual signals. Virtual interfaces let BFM models manipulate virtual set of signals instead of actual RTL signals. Virtual interface is a variable that represents an interface instance. Syntax: virtual <interface name> <variable name>;
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Virtual Interfaces Example

// interface // definition interface Bus (input logic clk); bit req; bit grant; logic [7:0] addr; logic [7:0] data; endinterface: Bus // testbench // interface instance Bus infc_b (clk); // dut instance dut dut1 (infc_b, clk); // class instance BFM mybfm = new (infc_b); class BFM; virtual Bus bus; Xaction xaction; function new (virtual Bus b); // need to initialize virtual interface // in constructor bus = b; xaction = new; endfunction task req_bus(); @(posedge bus.clk); bus.req <= 1'b1; $display("Req = %b @ %0t", bus.req, $time); endtask: req_bus endclass: BFM
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Random Constraints
How to decide how random to be

Random data sources

Random exercise of stimulus allows easy cases to be done easily Ability to tune random stimulus usually gives more coverage with less work (be careful) Save the impossible cases until the Design Under Test (DUT) is healthier Works hand-in-hand with functional coverage

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Simplest randomness
$urandom system tasks $urandom() is SV, thread stable, deterministic $urandom returns unsigned 32-bit integers Procedural call can be inserted wherever needed

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More sophisticated mechanisms

Random variables (rand modifier classes only) Must be properties of a class, except for some explicit randomization Select new random value each time .randomize() is called Example:
class x; rand int a, b, c; endclass : x x x_inst = new; initial begin : random_loop forever @(posedge clk) x_inst.randomize(); end : random_loop
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Whats randc for?

Exhaustive permutations of a variable c is for cyclic, every value of the variable will be reached before any value is duplicated Caution special solver ordering for randc

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Constraints
Set of Boolean algebraic expressions Relationships between random variables and:
Other random variables Non-random state variables

Example:
constraint constraint constraint constraint a_le_b { a <= b; } c_eq_10 {c == 10;} b_in_range { b >= 2 && b <= 8; } all_gt_0 {a > 0; b > 0; c > 0;}

How many permutations are now possible?

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Constraints
Restrict range of possible values Can use state variables to restrict range of random variables Example:
int x[7] = {3,5,6,27,10,42,1}; int z = hff, w = 10; constraint c_within_set_of_x { c inside x; } constraint b_between_w_z { b <= z && b >= w; }

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Conflicting constraints
What happens when you impose constraints that conflict in some way? Example:
constraint x_gt_y { x > constraint y_gt_z { y > constraint z_gt_x { z > if ( x_inst.randomize() begin end -solvefaildebug
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y; } z; } x; } == 0 ) // Solver error

Modelsim cmdline setting

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Constraint operators
Any Verilog boolean expression
i.e. x < y+b-c*10>>20

Other constraint operations set membership implication iterative constraint variable ordering functions

within -> or ifelse foreach solve before func_x()

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Implication constraint
Uses one boolean to decide if another constraint must hold
(trans_size == SMALL) -> (length < 10) (trans_size == MED) -> (length >= 10 && length <= 100) (trans_size == LARGE) -> (length > 100)

Advanced note:
a -> b is equivalent to !a || b

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Loop/array constraints
Constrain every element of an array in some fashion, including reference to other elements of array
constraint foreach A[i] } constraint foreach (k < } c1 { ( A[i] ) inside {2, 4, 6, 8, 10}; c2 { ( A[k] ) A.size-1) -> A[k+1] > A[k];

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Arguments to .randomize()
Normal form of .randomize()
No arguments, randomize class members according to declaration modifiers

Optional arguments
Specify the variables which are random Can make rand override declaration type for this call Declares entire set of random variables for this run of Constraint Solver null argument forces checking constraints only Cannot change randc to rand

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.randomize with {}
Specify inline constraints that are added to constraint set to solve

trans.randomize() with { x < 100;

z > buzz; };

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Distribution Constraints
Operators: := :/ dist Example: constraint twsConstraint { tws dist { [0:2] :/ 10, [3:9] :/ 1, [10:50] :/ 9 }; } constraint distConstraint { cmd dist { mem_write := 10, mem_read := 5, lrw := 1, lrrww := 1, io_read := 1, io_write := 1, idle := 1 }; }

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Putting it all together

module test_rand; typedef enum {SM, MED, LRG} trans_len; class transaction { rand bit [19:0] addr; rand trans_len len; rand bit [3:0] byte_len; rand bit wr_or_rd_b; constraint c1 { wr_or_rd_b -> len != LRG; } constraint c2 { (len == SM) -> (byte_len <= 4); } constraint c3 { (len == MED) -> (byte_len > 4 && byte_len <= 8);} constraint c4 { (len == LRG) -> (byte_len > 8); } // Mem above 16-bit is write-only IO devices constraint c5 { (!wr_or_rd_b) -> (addr[19:16] != 0); } virtual function string toString() return sformat(%5H: %s %d bytes, addr, (wr_or_rd_b ? WR : RD), byte_len); endfunction : toString endclass : transaction <CONTINUED>
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Putting it all together (cont)

transaction trans = new(); intial begin : test_body int counter = 0; repeat (20) begin : rand_gen if (trans.randomize() == 0) begin $display(ERROR: Random constraints conflict); $finish; end $display(%d: %s, counter++, trans.toString()); end : rand_gen end : test_body endmodule : test_rand

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Lab 12: Random Constraints

Modify the Xaction class created in lab11 and make all properties rand. 1. Add a rand property named size, with the following enumerated values: SMALL, MEDIUM, LARGE. 2. Add a distribution constraint that make the size: SMALL 70%, MEDIUM 20%, LARGE 10%. 3. Add a constraint that sets the length based on the size property: SMALL : (length <= 10) MEDIUM : (length >10) && (length <=20) LARGE : (length > 20) && (length < 100) (Note: Add a constraint saying the length must be > 0) 4. Write a loop that calls randomize() 40 times, printing the Xaction after each randomize() call.

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Packages
A mechanism for sharing parameters, data, types, tasks, functions, classes, sequences, and properties among modules, interfaces and programs

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Package Search Order Rules

package p; typedef enum {FALSE, TRUE} BOOL; BOOL c = TRUE; endpackage u = p::c, y = p::TRUE A qualified package identifier is visible in any scope All declarations inside package p become potentially directly visible in the importing scope: - c, BOOL, FALSE, TRUE The importing identifiers become directly visible in the importing scope: -c
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import p::*; y = FALSE;

import p::c if ( ! c )

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Package Example
keyword
package endpackage

Example: package p; class Data; int a; int b; endclass typedef enum {FALSE, TRUE} BOOL; endpackage : p

module top; import p::*; BOOL b = TRUE; endmodule OR module top; p::BOOL b = p::TRUE; endmodule

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Lab 13: Packages

Create two packages which contains an int C and C is initialized with two different values. Write a top level module that print out both C value

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System Tasks

Display
$display printf-ish, with \n implied
$display (format_string, arguments);

$write printf-ish ($display w/out newline) $sformat print formatted string (ala sprintf) $monitor Implicit task to call $display any time arguments change, only one $monitor active

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Time
$time Returns 64-bit time normalized to unit timescale, most common for error messages $realtime floating point scaled to timescale $stime least significant 32-bits of time

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Simulation Control
$finish end simulation (quit simulator), final blocks $stop halt simulation $exit quit execution of program block (SV-only)

Example
initial #10000 $finish(); initial @(posedge all_bfms_done) $finish();

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File I/O
integer char int integer integer integer fd c code code code code = = = = = = $fopen(string filename, string mode) $fgetc(int fd); $ungetc(char c, int fd); $fgets(string str, int fd); $fscanf(int fd, FORMAT, args); $sscanf(string str, FORMAT, args);

Example

string buf_s; in_fd = $fopen(input_file, r); out_fd = $fopen(output_file, w); chars_read = $fgets(buf_s, in_fd); if (chars_read == 0) begin $display(End of file); $finish(); end if (2==$sscanf(buf_s, "%x %x", hexStartAddr, hexEndAddr) ) begin $display(Address Range: %8x -> %8x, hexStartAddr, hexEndAddr); end

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File I/O
$fclose $fdisplay $fdisplayb $fdisplayh $fdisplayo $fgetc $fflush $fgets $fmonitor $fmonitorb $fmonitorh $fmonitoro $readmemb $swrite $swriteo $sformat $fscanf $fread $fseek $fopen $fstrobe $fstrobeb $fstrobeh $fstrobeo $ungetc $ferror $rewind $fwrite $fwriteb $fwriteh $fwriteo $readmemh $swriteb $swriteh $sdf_annotate $sscanf $ftell

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Random functions
$random $dist_chi_square $dist_exponential $dist_poisson $dist_uniform $dist_erlang $dist_normal $dist_t

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Named blocks
Blocks can be provided names. By providing blocks with names provides the following advantages:
Declaration of local variables. Named blocks are part of the design hierarchy. Local variables declared can be accessed through hierarchical referencing. Example
always @(CK or D) begin : latch_counter int count; if (CK) count = count + 1; begin O = D ; end end : latch_counter

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Threads

Sequential Blocks
There is the difference between a sequential and a concurrent block:
Simulator executes statements in a sequential block in sequence It finishes the current statement, then begins the next You always know the order in which it actually executes the statements The simulator exits the block after finishing the last statement
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Example
begin #5 a = 1; #5 a = 2; #5 a = 3; end

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Concurrent Blocks
The simulator executes statements in a concurrent block in parallel
It starts executing all statements simultaneously You can not know the order in which it actually executes statements scheduled for the same simulation time The simulator exits the block after finishing the latest statement. A return statement in the context of fork..join is illegal.

Example
fork begin $display( "First Block\n" ); # 20ns; end begin $display( "Second Block\n" ); @eventA; end join

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Dynamic Processes
Inspired by the need for software verification environments to dynamically start and stop threads, SystemVerilog defines 2 new special cases of forkjoin with associated keywords join_any & join_none
join_any join_none

fork other blocks continue as dynamic threads join_any // any block finished

begin fork join_none // no waiting at all @(sig1); end

NOTE Child processes spawned by a forkjoin_none do not start to execute until the parent process hits a blocking statement
Copyright 2005 Mentor Graphics Corporation

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Process Control Wait Fork

With Dynamic processes SystemVerilog needed to provide more global detection that spawned processes have completed.

Q 6.1

The wait fork statement is used to ensure that all child processes (spawned by the process where it is called) have completed execution.
begin fork task1(); task2(); join_any fork task3(); task4(); join_none wait fork; end

// continue when either task completes

// continue regardless // block until tasks 1-4 complete

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Copyright 2005 Mentor Graphics Corporation

Process Control Disable Fork

Q 6.1

The disable fork statement terminates all active child processes of the process where it is called. Termination is recursive, in other words it terminates child processes, grandchild processes, etc.

task run_tests; fork simul_test1; simul_test2; join endtask task test_with_timeout; fork run_tests(); timeout( 1000 ); join_any disable fork; endtask

// 2 child tasks spawned in parallel, first to finish triggers join_any // Kills the slower task (including any grandchild processes and so on)

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Copyright 2005 Mentor Graphics Corporation

Events Trigger Types [1]

Triggering an event
Named events are triggered using -> operator. Triggering an event unblocks all processes currently waiting on the event. These events are such that trigger state cannot be observed but only their effect. Event can be visualized in wave window.
module event_testing (); event a, b; bit clk; always @(posedge clk) -> a; always @(negedge clk) -> b; initial begin clk = 1'b0; forever #10 clk = !clk ; end endmodule

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Events Trigger Types [2]

Nonblocking event trigger
They are triggered using ->> operator. The statement executes without blocking and it creates a nonblocking assign update event in the time in which the event occurs. The effect of this event is felt during the nonblocking assignment region of a simulation cycle. Example
always @(posedge clk) begin if (counter == 2) ->> a; counter++; end initial begin forever @(a) $display("event a triggered @ %0t, $time); end

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Waiting for an event

@ is used to wait for an event. The @ operator blocks the calling process until the given event is triggered.
Example
module event_testing (); event a, b, c; bit clk; always @(posedge clk) -> a; always @(negedge clk) -> b; always @(a or b) -> c; initial begin clk = 1'b0; forever #10 clk = !clk ; end endmodule
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Event Sequencing: wait_order()

wait_order construct suspends the calling process until all specified events are triggered in the given order [left to right]. If any events are triggered out of order then it causes a fail of the operation.
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Example
bit success; wait_order (a, b, c) success = 1; else success = 0; // event must occur in the // following order // ->a ->b ->c if not it fails.

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Event Variables [1]

Merging Events
When one event variable is assigned to another, both merge into one event variable. Executing -> on either one of the events affects processes waiting on either event variable.
Example event a, b; a = b; -> a; // also triggers b -> b; // also triggers a

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Event Variables [2]

Reclaiming Events
When an event variable is assigned the special null value, the association between the event variable and the underlying synchronization queue is broken.
Example
event E1 = null;

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Event Variables [3]

Event Comparison
Event variables can be compared against other event variables or the special value null. Equality (==) with another event or with null. Inequality (!=) with another event or with null.
Example
event E1, E2; if ( E1 ) // same as if ( E1 != null ) E1 = E2; if ( E1 == E2 ) $display( "E1 and E2 are the same event" );

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Semaphores
Can be described as counters used to control access to shared resources by multiple processes [threads].
Printer1 Printer1 [1] [0] Printer2 [1] 3 keys 2 keys Printer3 [1] Print manager

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Semaphore Methods
Semaphore provides following built-in methods:
Method
new() put() get() try_get()

Use
Create a semaphore with specified number of keys. Return one or more keys back. Obtain one or more keys. Try to get one or more keys without blocking.

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Semaphore example
module semaphore_test (); semaphore spr = new(2); initial begin:init1 #1 spr.get(1); $display("initial1 takes 1 key at %0t", $time); #6 spr.put(1); $display("initial1 returns 1 key at %0t",$time); #1 spr.get(1); $display("initial1 takes 1 key at %0t", $time); end Output:
# initial1 takes 1 key at 1 # initial1 returns 1 key at 7 # inital2 takes 2 keys at 7 # inital2 returns 1 key at 12 # initial1 takes 1 key at 12 # q -f
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initial begin:init2 #5 spr.get(2); $display(" inital2 takes 2 keys at %0t",$time); #5 spr.put(1); $display(" inital2 returns 1 key at %0t",$time); end endmodule: semaphore_test

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Mailboxes
Mailbox is a communication mechanism that allows messages to be exchanged between different processes.

Process 1

Process 2

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Mailbox Types
Mailboxes can be classified as:
Unbounded mailboxes
No restrictions placed on size of mailbox. put() will never block. Ex: mailbox m = new ();

Bounded mailboxes
Number of entries is determined when the mailbox is created. Bound value should be positive. put() will be blocked if the mailbox is full. Ex: mailbox m = new (5); // mailbox of depth = 5

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Mailbox Methods
Messages are placed in strict FIFO order. This does not guarantee order of arrival but that the arrival order shall be preserved. Mailboxes provides following built-in methods:
Method
new() put() get() try_get()/ try_peek() try_put() Create a new mailbox. Place a message in a mailbox. Retrieve a message from mailbox. Try to retrieve a message from the mailbox without blocking. Try to place a message in mailbox without blocking. Useful only for bounded mailboxes. Copies a message from mailbox without actually removing it.
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Use

peek()

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Mailbox example
module mailbox_ex (); class Xaction; rand bit [2:0] addr; endclass typedef mailbox #(Xaction) mbx; mbx mb = new (); initial begin: t Xaction xaction; int mb_size; for (int i=0; i<5; i++) begin xaction = new; xaction.addr = 3b111; $display("BEFORE:: Addr = %h", xaction.addr); mb.put(xaction); end 163 mb_size = mb.num(); for (int i=0; i<mb_size; i++) begin: dis_l Xaction d_x; mb.get(d_x); $display("Addr = %h", d_x.addr); end: dis_l end: t endmodule: mailbox_ex

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BACKUP

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foreach (Not in ModelSim 6.1) {BACKUP}

Implicit loop variable(s), multiple dimensions, any array type
int arr_x[]; typedef int arr_joe[7:0][3:8] arr_joe arr_y[$]; int arr_z[0:3*width][8*num-1:0]; initial begin arr_x = foreach foreach foreach end

new[10]; (arr_x[i]) statement (arr_y[m,n,p]) statement (arr_z[i,j]) statement

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unique and priority modifiers {BACKUP}

Modifiers on if and case/casex/casez selection expressions unique - no more than one branch may be true for each evaluation, simulator errors if this happens priority - order of evaluation is important Both modifiers require that if no fall-through else/default statement is available, and no branch is true, an error is generated
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Lab 5: CRC}

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Lab 5: CRC (cont) {BACKUP}

Implement the CRC algorithm shown in the previous foil. The operators << (left shift) and ^ (xor) will be needed. Process the bitstream given in the lab file and report the CRC.

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Constraint Guards {BACKUP}

Guards prevent the application of constraints, similar to implication, but remove the constraint from consideration of the constraint solver Use the same implication operator, just using state variables
(!global_reset_state && cmd) -> (cmd_type != IDLE)

Can even test obj pointers for null

(a != null && a.x > 10) -> (y < 100 && y > a.x)

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std::randomize() {BACKUP}
Procedural invocation of constraint solver Any variables can be the random variables with block for constraints Normal .randomize() cannot include variables outside scope of class

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Disabling rand/constraints {BACKUP}

rand_mode method to toggle the rand attribute off on a class variable constraint_mode method to toggle the application of a named constraint

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Random Stability {BACKUP}

SV has thread random stability

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