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Design of a Semi-Custom IC
Dr Zhou Xing
SESSION 1995/96
EEE / NTU
X. ZHOU / 1995
Objectives
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
Goal 1 to study the various approaches to the design of a semicustom IC To identify the characteristics used to categorize the different types of VLSI methodologies into full custom, semi-custom and standard design To classify a given IC into one of the above groups To evaluate and decide on the most optimal design method to implement the IC for a given case study To describe the different stages of the design cycle To identify an ASIC family To summarize the main features of an FPGA architecture To describe the FPGA development cycle Goal 2 to deal with the design issues of a particular FPGA design for a 4-bit microprocessor To design the simple 4-bit microprocessor circuit using the basic building blocks available in the FPGA design tool environment To generate a test plan to test the circuit To demonstrate familiarity with the various CAD packages used in the three main stages of design entry, design verification and design implementation
EEE / NTU
X. ZHOU / 1995
How do I implement (on hardware) a 4-bit microprocessor using FPGA semi-custom IC design approach? How do I choose an appropriate design methodology if given a particular system specification?
EEE / NTU X. ZHOU / 1995
Project
Lecture
Notes
Q/A
Reading
Group discussion
Assignment
Design exercise
Thinking
Quiz
Examination
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Session 1 Lecture (50') Microelectronic IC and ASIC design Break (10') Group discussion (50') Break (10') Group presentation (50') Summary (10')
Session 2 Lecture (50') Semi-custom design and FPGA Break (10') Group discussion (50') Break (10') Group presentation (50') Summary (10')
Session 3 Design exercise and discussion (50') 4-bit microprocessor Break (10') Class discussion, Q/A (60') Break (10') Quiz (50')
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Assessment
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
Continuous assessment Attendance Group discussion/presentation Assignments Quiz (45 minutes, close book) Design exercise (1 week) Final examination 2 hour, open book (two choose one)
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Assignments
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
Assignment 1 List important terminologies, key concepts, methods of analysis, figures of merit and number ranges, etc., or anything else which you learned from this course or other references Due: End of last session Assignment 2 Ask a hypothetical question relevant to the subject of this course, and give your brief answer Due: Two days before the last session
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Outline
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
Microelectronic IC Design
ASIC Design Semi-Custom IC Design Field-Programmable Gate Array 4-Bit Microprocessor Implementation
EEE / NTU
X. ZHOU / 1995
Engineering
System Behavioral
Structural
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Motivation
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
Electronic System:
A black box which performs a certain function based on the laws of physics of the electrons
Input electron
Output
Answer:
Art
Design
Science Perspective Art Innovation Decision making Science Transformation Machine Human Tools ? KBES CAD Creativity Productivity Productivity
Decision-making perspective: a creative process involving individual talent, intuition, experience, etc. Transformation perspective: a process of successive transformations of specifications from one domain (abstraction level) to another
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Top-down
Synthesis
Bottom-up
Analysis
Behavior
Vo Vi
Structure
Vo
Behavior
Vo
Vi
Vi
Analysis Application of well-known principles to predict the behavior of a system Synthesis Selection of a solution from a number of alternatives based on a set of criteria An ensemble of answers waiting for the right question
EEE / NTU X. ZHOU / 1995
Design Decisions
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
q What design decisions are to be made? q How are they made? Software/hardware trade-offs Affect the flexibility of the product (need to modify the design in the future) Processing technology Figure of merit: gate delay, power consumption, noise immunity, logic capacity Implementation style Standard cells, gate arrays, programmable logic devices, etc. Choice of hardware algorithms Functional module designs in ROMs, RAMs, PLAs, etc., where regularity in the structure can be captured and exploited in a procedural fashion
Note The first three decisions are largely influenced by marketing considerations such as design standards, compatibility requirements, expendability, product lifetime, and other economic factors, which can be determined before the actual design starts. In contrast, It may be necessary to delay the fourth decision due to uncertainties in meeting physical constraints such as chip area, power consumption, I/O bandwidth, or system partitioning.
EEE / NTU X. ZHOU / 1995
To combat complexity divide-and-conquer Hierarchical approach Partition various aspects of VLSI circuits into abstraction levels Define the order among these levels Methodology A particular ordered sequence of steps linking these abstraction levels Implementation A set of CAE design tools Efficient implementation depends on: How well its underlying principles reflect the nature of VLSI circuitry How well its external expressions supports the implementation efforts
EEE / NTU
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Digital Behavioral
VHDL
Analog Behavioral
Laplace/Z transfer functions, Data-flow diagrams,
Level
High
Cost
Low
Accuracy
Low
RTL/Gate
Event-driven
Ideal Functional
Op-amps, switches, integrators, comparators,
Switch/Timing
Equivalent RC
Nonideal Functional
Finite bandwidth, gain, input/output resistances,
Electrical
Matrix solution
Electrical
Electrical circuits
Low High High
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High
Hierarchy System
Abstraction
Space-time behavior as instruction, timing and pin assignment specifications Global organization of functional entities Binding of data flow functional modules, microinstructions Primitive operation and control methods Boolean function of gate circuits Electrical properties of transistor circuits
Supporting Tools
Flow charts, diagrams high-level languages
HDLs, floor-planning, block diagrams, area and clock cycle estimators Systhesis, simulation, verification, and test analysis programs, resource utilization evaluators Libraries, module generators, schematic entry, test generators Schematic entry, synthesis programs, simulation and verification programs, PLA tools RC extraction programs, timing verification and electrical analysis Layout editor/compactor, netlist extractor, design rule checker, floor-planning, placement and routing programs
Geometric constraints
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Microelectronic Technologies
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
Microelectronic technologies
Printed circuit
Film
Monolithic
Solid board
Flexible board
Plastic molded
Thick
Thin
Silicon
Gallium arsenide
MOS
Bipolar MOS
Bipolar
GaAs on silicon
Hybrid
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Outline
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
EEE / NTU
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Standard components
Fixed application
Applications by programming
Full custom
Semicustom
Silicon compilation
Logic families
Hardware programming
Software programming
Gate array
Analog array
Master Programmable Standard slice logic devices cell PLA PAL PGA FPGA
TTL CMOS
PLA ROM
PROM
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Attribute Goal/Direction Cost constraint Performance limitation Major design alternatives Coupling between design steps Testability requirement Verification Prototyping Last-minute changes Design guidance Tools
Major components (processors) Design styles (GA, SC, FC) Loose Tight
Nodes accessible at board level Must be incorporated early Breadboarding Usually in-house Less costly Informal Less CAE dependent Simulation In cooperation with vendor Costly Strong methodology CAE intensive
EEE / NTU
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Costs
Lower non-recurring cost Tighter security Faster Turn-around time
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A process of integrating systems into chips ASIC A mixture of aspects of design approach, implementation technology, market orientation, and subsequent product requirements Central to meeting this challenge A better understanding of the algorithm characteristics, major architecture concepts, implementing technology, and, most important, their interactions
Algorithm
Technology
Interaction
Architecture
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Before VLSI
Algorithm data structure parallelism concurrency synchronization Technology fabrication device physics circuit techniques
Algorithm
Technology
Algorithm
Technology
instruction set
digial logic ASIC design Architecture Architecture functional unit memory interconnect network operating systems systolic array RISC hierarchical design methodology CAE systems Architecture
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System designer
Application engineer
q Gap: the disparity between our capability to fabricate and our capability to design
High-level abstraction
IC
Process technology
ASIC vendor
Silicon foundries
Circuit techniques
Device characteristics
q Interfaces: difficult to define due to the evolving nature of ASIC technology and the diversity in application areas
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Idea
ASIC product
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Schematic entry
Cell library
Select technology
Geometric rules
Re-simulation
Technology files
Manufacture
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Full custom
bottom-up
Semi-custom
application-specific
Silicon compilation
top-down
Full custom A chip is designed from scratch to meet a particular need The emphasis is on achieving best electrical performance and minimum area It is appropriate for chips having large production runs Silicon compilation Given a description of the system, mask and test information are produced The output is either a simple combinational circuit or a finite state machine Most silicon compilers are not silicon-area efficient It is appropriate for small volume runs It may be used to generate simple cells to build up standard cell libraries
EEE / NTU
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Time-to-market the time taken for prototypes to be available and, later, the time for production quantities to start arriving
Typical turn-around times for samples to be delivered by foundries
Year
Gate array
Standard cell
Full custom
The time for production models to arrive is usually longer, often 1020 weeks.
EEE / NTU
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design freedom/effort unconstrained full custom design semi-custom design mask layout
Microprocessor
interconnect
Gate array
PLA
programming
PAL
Performance (FTR) design turn-around time production volume
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Production volume
?
Security
EEE / NTU
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Group Discussion 1
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
VLSI Design Methods Topic 1 Identify characteristics used to categorize the different design methodologies Describe the VLSI design hierarchy and the hierarchical design approach Topic 2 Identify the main components of a typical design flow Define and explain front-end and back-end design activities
ASIC Design Topic 3 Describe the characteristics and benefits of ASIC design as opposed to the standard IC design Identify and define different ASIC families Topic 4 What design decisions are made in choosing a particular ASIC design style How they are made
EEE / NTU
X. ZHOU / 1995
Outline
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
EEE / NTU
X. ZHOU / 1995
Gate array A chip containing a prediffused but unconnected pattern of gates. Inter connection of the gates is made by one or more customized masks Analog array A partially prefabricated chip containing either analog basic circuit elements or discrete analog devices, which are interconnected into an analog circuit by a customized mask Master slice A prefabricated chip consisting of a mix of gate and analog arrays, allowing systems containing both analog and digital functions to be customized Standard cell Software defined logic or analog circuit functions as building blocks to form the required system. There is no prefabrication. Similar in concept to PCB Programmable logic devices (not strictly ASIC) A range of logic gates and latch functions which can be programmed
EEE / NTU X. ZHOU / 1995
Gate Arrays
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
Concept: Array of gates + pads General concerns What logic/gate configuration to use? How many pads are required? What is the best floor plan (layout) to provide adequate signal routing and power distribution?
EEE / NTU
X. ZHOU / 1995
Analog Arrays
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
amplifiers
filters
oscillators
No library of layouts Manual trial-and-error process Two classes With complete function cells op-amps, unity-gain buffer amplifiers, capacitors, switches With subcells diff-amp + output buffer = op-amp
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Master Slice
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
Concept: Gate array + Analog array = Master slice General concerns Ratio between the amount of digital to analog circuitry Type of analog circuitry Size of the gate array
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Service offered speed, quality, size of the library, range and sophistication of the software, time for prototyping and production Technical specifications of the array array size, functions, pad numbers, speed of operation, package range Cost non-recurring engineering (NRE) costs Second sourcing product lifetime (if long), product cost (if high)
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Advantages Lower cost (sharing of processing cost) Faster prototyping Disadvantages Large chip area for routing (~75%) Low gate utilization (~50%) Circuit utilization (due to standard size)
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Company AMD/MMI AMCC Cherry Fujitsu Gain Electronic Corp. GE/RCA Gigabit Logic Gould/AMI Harris Hitachi LSI Logic Linear Technology Micro Circuit Engineering Micro Linear Corp. Motorola
GA (GaAs) (GaAs)
AA/MS
Company National/Fairchild NCR NEC Philips/Signetics Plessey/Ferranti Raytheon Semi Process Inc. Siemens Taxas Instruments SGS/Thomson Toshiba TriQuint Univeral Semiconductors Vitesse Semiconductor VLSI Technology
GA (GaAs) (GaAs)
AA/MS
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Standard Cells
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
Design concept
Lib (mapping) Si
Standard cell
System
interconnect
Basic approaches Channelled cells alternate rows of cells and channels Channel-less type whole chip area covered by cells, the routing occurring above them in the top two layers of interconnect metal Cell library Size: Standard (small logic), macro cell, mega modules, megacells, supercells Type: Fixed: 8-bit synchronous counter Parameterized: n-bit counters, shift registers, PLAs, RAMs, ROMs, microprocessors (bit slice machine) Pads
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Advantages More flexible to include digital as well as analog functions More compact design (less routing area, improved speed) More sophisticated systems can be built (using parameterized cells, microprocessors) Disadvantages Up-front cost no inherent sharing of processing cost (some sharing in software library and processing in a multi-project wafer) Costs in additional mask-making, software, and workstation resources
EEE / NTU
X. ZHOU / 1995
AMCC Fujitsu GE/RCA/AWA Could/AMI Harris Hitachi International Micro Products Intel LSI Logic Micro Circuit Engineering Motorola National/Fairchild
NCR NEC Plessey/Ferranti Philips/Signetics Siemens Silicon Systems Texas Instruments SGS/Thomson Toshiba VLSI Technology Zymos
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Arrays
Hardware System (vendor)
PLDs
Standard products (can be programmed in-house)
Std Cells
Software System (vendor)
Risks in changing to ASIC (for small manufacturers) Investment in NRE costs Lack of last-minute design changes Advantages of turning to PLDs (even for large organizations for prototyping) Fast programming of devices No NRE charges Disadvantages Limited size (< 10,000 equivalent gates) Not as flexible as gate arrays, standard cells, or full custom Large devices can be expensive (several hundred dollars per chip)
EEE / NTU X. ZHOU / 1995
Technologies Metal fusible link technology Polysilicon fuse technology Antifuse technology Ultraviolet erasable and electrically erasable methods employed in ROMs Dynamic matrix switching methods (LCA)
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Concept: Array element Simple PLDs (macrocells) Routing Internal bus structure Examples Altera: Macrocells interconnected by internal bus Xilinx: Logic cell arrays (LCAs) routed by switching matrix Switching matrix Configurable logic circuits (PLA)
EEE / NTU
X. ZHOU / 1995
Class 1
AND (fixed) AND (variable) AND (variable) AND AND AND AND AND AND OR OR OR OR OR OR
Class 2
Inverter/NOT inverter Inverter/NOT inverter with feedback Register Register with feedback Other logic (e.g., XOR) register Other logic register with feedback
Class 3
Class 4
Other names (programmable logic devices ASICs) EPLD (erasable PLD) PLC (programmable logic sequencer) MAX (multiple array matrix) FPAD (field programmable address decoder)
EEE / NTU
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Actel Semiconductors Advanced Micro Devices Altera Corp. Atmel Corp. Cypress Semiconductor Exel Microelectronics Gazelle Microcircuits Gould Semiconductors Harris Semiconductors Intel Lattice Semiconductor Corp. Monolithic Memories National/Fairchild
Panatech Semiconductors Philips/Signetics PLX Technology Samsung Semiconductor Seeq Technology Inc. Seiko Semiconductor SGS/Thompson Sprague Solid State Texas Instruments VLSI Technology Wafer Scale Integration Xilinx Inc.
EEE / NTU
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Outline
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
EEE / NTU
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FPGA A device in which the final logic structure can be directly configured by the end user without the use of an IC fabrication facility Two major aspects Interconnection resources: wire segments and programmable switches Architecture design: structure and content of logic blocks Two distinct features Instant manufacturing turn-round (minutes) Negligible prototyping costs (~$100)
A Conceptual FPGA
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MPGA: Mask programmable by the manufacturer (hard-wired) FPGA: Field programmable by the end user (switch)
Attributes Prototype cost Production time Operation speed Logic density Area requirement Yield MPGA high long fast high small high FPGA low short slow low large low
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General architecture Programming technology Logic optimization Technology mapping Logic block architecture Interconnection resources Placement and routing
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Approach / Goal
Logic Optimization
--------------------------
----------------------------
Optimize area and/or speed of the final circuit Area optimization minimize total number of blocks Delay optimization minimize the number of stages of logic blocks Minimize the total length of interconnect
Technology Mapping
Placement
Routing
---------------------------Programming Unit
Configured FPGA
EEE / NTU
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Programming Technologies
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
Programming element (switch) Entities that allow programmable connections between wire segments Configurable in one of two states: ON or OFF Programming technologies Static RAM cells Anti-fuses EPROM and EEPROM transistors Desired properties of the programming element Consume as little area as possible Have a low ON resistance and a very high OFF resistance Contribute low parasitic capacitance to the wiring resources Can be reliably fabricated in large quantities on a single chip Other features: Non-volatile and re-programmable
EEE / NTU X. ZHOU / 1995
original network
Logic optimization
----------------------------
----------------------------
---------------------------Logic Synthesis
Technology independent Redundancy removal Common subexpression elimination Dont-care exploitation Technology mapping Technology and architecture dependent Optimized circuit considering both area and delay Library-based Lookup table Multiplexer-based
Logic Optimization
optimized network
Technology Mapping
---------------------------optimized circuit
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Area
Architecture
Delay
LOGIC BLOCK
Functionality Routing Total area (logic block + routing)
Area
10~30%
70~90%
Functionality
Interconnection Resources
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
General purpose interconnect Direct interconnect Horizontal/vertical routing channel Wiring segment Feed-through Routing switch (matrix)
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Placement
optimized circuit
-----------------------
----------------------------
Well developed techniques Similar to other technologies Routing Achieve interconnections among the Logic Cells by selecting wire segments and routing switches Routing architectures Row-based FPGA: only horizontal routing channels Symmetrical FPGA: both vertical and horizontal routing channels
Placement
Routing
---------------------------Programming Unit
EEE / NTU
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Requirement/planning
Design Entry
Computer-aided structual design Behavioural method of design description Hierarchical mixed-mode design entry
Design Verification
Functional simulation Timing simulation (after implementation) Hardware testing
Design Implementation
Design merge Partition (technology mapping) Placement and routing FPGA configuration
Manufacturing/Delicery/Maintenance
EEE / NTU
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FlipFlop
Switch Matrix
IOB
Pad
CLB
High-speed direct Flexible generalpurpose Low-skew long lines Internal 3-state buffer
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VIEWDRAW abc.1
Design Entry
Design Verification
Functional Simulation Timing Simulation
LCA2XNF abc.XNF
Filewrite abc.WIR
XCHECKER Download
VIEWSIM WIR2XNF abc.XNF XNFMAP Partitioned file abc.MAP MAP2LCA abc.AKA abc.BIT Bitstream file abc.WFM VIEWSIM waveform file
BAX abcth.XNF
MAKEBITS VIEWWAVE abc.LCA (routed) APR abc.LCA with hierarchical net connect info VSMUPD abcth.VSM VIEWSIM VSM Savefile abc.SEE abcth.VSM
VIEWWAVE abcth.WFM
{
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Design Implementation
X. ZHOU / 1995
Actel Semiconductors Advanced Micro Devices Algotronix Altera Corp. Concurrent Logic Crosspoint
Cypress Semiconductor Plessey Plus Logic Quicklogic Corp. Texas Instruments Xilinx Inc.
EEE / NTU
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Group Discussion 2
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
Semi-Custom Design Topic 1 Define and describe different semicustom design styles Discuss the major advantages and disadvantages of each of the design style Topic 2 Compare different types of programmable logic devices Describe the concept of programmable gate arrays
FPGA Development Topic 3 Summarize the main components of the FPGA architecture Describe the activities in each major step of the FPGA development cycle Topic 4 Describe the general architecture and major steps in the Xilinx FPGA design environment Relate the major design steps in the Project (M3) to those of the generic development cycle
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Outline
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
Microelectronic IC Design ASIC Design Semi-Custom IC Design Field-Programmable Gate Array 4-Bit Microprocessor Implementation
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Relate a specific example to what you have learned System specification What is required? Choice of methodology What are the alternatives? Why choosing FPGA? Design flow How to design? What are the major concerns at each stage of the design?
EEE / NTU
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From state diagram determine the connections of the flip-flops Each flip-flop represents one state Input is determined from the previous state AND the input function switches (FC3 FC2 FC1 FC0) May use a hierarchical approach each instruction is a sub-block From timing diagram determine the output signals Outputs of the CNTRL logic block are a combination (OR) of the different states of all the instructions Decode each output of the CNTRL logic block from the timing diagram Features Simple in design, but waste of flip-flops Difficult to modify the design hard-wired (i.e., laid down permanently in the processors electrical circuitry)
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RST
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Hardware
Hard-wired circuitry
Firware
Microprogram
Software
High-level program
Microprogram a set of control instructions written in microcode The idea was conceived more than 30 years ago, soon after the advent of the first computers In principle, any computer (mainframe to PC) can be designed with a microprogrammed control system Microprogramming a computer (firmware) is not the same as programming a microcomputer Microprogramming In most modern computers the routing of information is controlled at the lowest level by a microprogram: a set of stored instructions that functions in place of a completely hard-wired control system David A. Patterson
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RST: Reset the 3-bit counter as well as enable chip-select pin (CS) of the PLA CLK: Clock a divide-by-seven counter (outputs C2 C1 C0: 000 to 110)
PLA or ROM
PLA/ROM input: FC3 FC2 FC1 FC0 and C2 C1 C0 Every instruction cycle is made up of seven clock periods For single-operand instruction (NOT), Enable Output Register can be repeaed to avoid complicated decoding Boolean expression for the PLA/ROM can be decoded from the timing diagram for each instruction PLA is prefered to a ROM if the number of instructions to be implemented is fewer than 16
C RST
CLK
3-Bit Counter
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Table 1: Types of Cycles and the Corresponding Output Signals Cycle Enable Output Register Enable Input Buffer Load A Register Load B Register Enable ALU Load Output Buffer OE2 OE1 OE0 LO2 LO1 LO0 M F1 F0 Cin Ro Ren
T0 T1 T2 T3 T4 T5
Table 2: Truth Table for an Instruction FC3 FC2 FC1 FC0 C2 C1 C0 T x OE2 OE1 OE0 LO2 LO1 LO0 M F1 F0 Cin Ro Ren
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Assuming the design is implemented using Xilinx XC3000 FPGA Design methodology What design approach is chosen to implement the 4-bit microprocessor? and why? What design stages will be going through? Design implementation How to reduce (optimize) the number of states? How many configurable logic blocks (CLB) would be needed to implement your design? Design verification How to simulate your design using, e.g., the VIEWSIM simulator? What is the expected output waveform given a particular input pattern?
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Design Exercise
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
With reference to the 4-bit microprocessor specification in the Project Manual (M3), design the control circuitry of the CNTRL logic block for the following instructions [you may choose at least one from each of the groups (a) and (b)]: (a) NOT , AND , OR , XOR ; (b) ADD , SUB , RRC , R L C using the following two approaches: I. One flip-flop per state: (1) Draw the state and timing diagrams (2) Write the next-state and output equations (3) Draw schematic diagrams using D flip-flops to implement each state and output signals
II. PLA and 3-bit divide-by-seven counter: (1) Define the types of cycles by filling in Table 1 (2) Decode the output signals for each instruction by filling in Table 2 (3) Based on Table 2, draw stick diagram of the PLA to implement the CNTRL logic General questions: (1) Show how a new instruction (e.g., INCA) can be added for each of the two design methods (2) Draw conclusions on the advantages and disadvantages of the two design styles
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Summary
ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC
Design Approaches, methodologies, decisions, hierarchy, process Classification Manufacturing technologies, design methodologies Comparison Major figures of merit to consider Cost: development, manufacturing, non-recurring engineering, Performance: speed, power, density, reliability, Schedule: prototyping, turn-around time, CAD tools, second sourcing, service quality and speed, Others: production quantity, design freedom, last-minute change, security, FPGA (Xilinx) concept, features, design cycle, implementation, Design example relate to all of the above
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Thinking
Understanding
Expanding
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At present, we are using very-large-scale integration (VLSI). ULSI and wafer-scale integration (WSI) are being
considered to replace VLSI. Do you think that WSI can replace VLSI despite of its disadvantages? and when do you think WSI will replace VLSI technology?
What skill/knowledge an engineer must possess when designing circuit using different design methodologies? What are the front-end and back-end design activities in the design cycle? What are the most important factors/criteria affecting the selection of a particular methodology for use in a
company?
What are the advantages and disadvantages of various ASIC test approaches? ASIC designs are getting more and more complex. How should we go about doing it? An IC is to be designed. Highlight the design steps that will be applied to obtain the final design. Give examples of the different types of ASIC families and describe briefly the advantages and architecture of one
of the types.
With todays technologies, to buy a sophisticated standard off-the-shelf IC is very easy or to fabricate a full-custom
IC is already simplified. Why is there a need to have a semi-custom solution and why it is so popular?
What is the disadvantages of using full-custom ICs and what is the solution to it? What are the definitions of gate array, analog array, master slice, standard cell, programmable logic devices?
List the pros and cons.
What are the advantages and disadvantages of using master slice analog semi-custom ICs?
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What are the advantages and disadvantages of MPGA and FPGA? Which is a wiser choice to use? The time frame from first to second to third generation of FPGAs is approximately six years. Explain why and
what might happen in the next 6 years.
The details of the FPGA development cycle, given in the document of Design Module, was insufficient to show the
software and hardware that a new designer has no idea of utilizing its various tools. The question is how the visualization of FPGA development system like? What is the function of its system, in terms of hardware and software?
List some debugging hardware tools of a FPGA-based system. Can a field programmable electrical system be implemented on one chip? Why do we need FPGA and how we can use it? What are the software tools needed for the future development of FPGA? What are the future trends of the Field Programmable Gate Array (FPGA)? Compare FPGAs and PLDs. If you are a designer, what are the criteria to choose among different types of semi-custom ASIC? and how are
you going to choose an appropriate type for your design?
Since there are many kinds of user-programmable logic devices (e.g., FPGA, PLD & PAL), their characteristics
and architectures vary widely as well. So is there any proposal/solutions to integrate the programming of all these devices with just one package/software?
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