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An Optimum Digital SMPS Controller Architecture

Introduction
Silicon Laboratories Inc., Power Products Application Engineer: Ravi Murugeshappa Marketing Manager: Brett Etter Digital control promises significant system performance gains resulting from complex control algorithms that are difficult to implement in analog. This enables improved performance in traditional power architectures, and new innovation within the power stages that were previously impractical due to the lack of a sophisticated control mechanism. System reliability is improved with the elimination of external analog components, which are prone to value changes with age and temperature. The addition of in-system programmability enables the manufacturer to revise system design and generate custom product versions primarily through software modifications and shorter design cycles. Digital power control is not new to power system designers. In the last two decades, digital control methods implemented in general-purpose processors and digital signal processors (DSPs) have become commonplace in applications, such as motor drives and three phase power converters. In these applications, the power semiconductors are operated at relatively slow switching frequencies, enabling low-bandwidth processors to perform complex control and monitoring tasks. For quite some time, digital control of switch mode power supplies (SMPS) has eluded power system designers due to the stringent requirements of fast processing times and low-cost system solutions. However, recent digital control technology advancements are generating interest in digital SMPS control methods, architectures and circuit implementation techniques.

DIGITAL CONTROLLER ARCHITECTURAL CONSIDERATIONS


In order to be commercially successful, the digital SMPS controller must be low cost and easy-to-use, and must offer a means of achieving features and performance not easily attainable in analog implementations. Three common architectural approaches are considered here: DSP, custom hardware and application-specific processor.

Figure 1: Digital control architectures The DSP approach (Fig. 1A) involves analog-to-digital conversion of all pertinent system parameters and control/management algorithm execution in real time by a single processor. While this approach is very flexible, it has practical cost, size and performance limitations compared to analog approaches. For example, applications operating at higher PWM frequencies may not perform as well as their analog counterparts due to DSP bandwidth limitations. Unlike the DSP architecture, the hardware-based approach (Fig. 1B) uses fixedarchitecture hardware state machines to execute the control algorithm. While this architecture offers higher bandwidth and lower cost than the DSP approach, it is not flexible and, therefore, must be designed to suit a specific end application.

The application-specific processor (Fig. 1C) combines the programmability attributes of the DSP solution with the performance and economy of the hardware solution. Dedicated, configurable processing hardware performs bandwidth-intensive operations, such as cycle-by-cycle control variable calculation and current limiting. The hardware processors are managed by a lower-bandwidth, programmable system processor that continuously modifies parameters in the hardware processors to optimize system performance at every point of line and load. The system processor also performs system protection and management functions. This architecture offers both flexibility and performance and results in a smaller, low-cost controller solution.

Digital Control Overview


Comparisons between traditional analog and digital control will be made in this section; so, a brief review of analog voltage and current mode control is presented here. An analog voltage mode control circuit is shown in Figure 1. The pulse width modulation (PWM) cycle is initiated by the leading edge of a free-running PWM clock. The clock edge sets the PWM latch (causing current to flow in the inductor or transformer) and, at the same time, starts a linear voltage ramp, which is applied to one side of the PWM comparator. The error amplifier generates a compensated error signal (VERROR) by subtracting the output voltage from a reference and applying the appropriate frequency compensation. The PWM comparator compares the voltage ramp to the compensated error signal and resets the PWM latch when the difference between the two terms is zero.

Figure 2: Analog Voltage Mode Control

Current mode control (Figure 3) regulates output current, providing faster output transient response compared to voltage mode control. As shown, the PWM cycle again begins with the PWM clock setting the latch. However, the controller resets the latch only when enough current has been delivered to the load to drive the error term to zero.

Figure 3 : Analog Current Mode Control While neither of these control methods is ideal, each has its own range of applications where it is more effective than the other. A summary of the strengths and weaknesses of voltage mode and current mode control is summarized in Table 1.
Consideration Design Difficulty Transient response Compensation Current sharing XFMR flux balancing Noise immunity Operation at duty cycle >50% Pulse-by-pulse current limiting Loop gain change with VIN Multiple output voltages Voltage Mode Single loop- easy to design/analyze Slower than current mode More complex: 3 Poles, 2 Zeros Requires extra circuitry Requires extra circuitry Good Operates normally Requires current limiting circuitry Requires VIN feed-forward circuit Good cross-regulation - does not need coupled inductors Current Mode Two loops more difficult to design and analyze Faster than voltage mode Less complex: One pole Inherent in operation Inherent in operation Poor, especially at low loads Requires slope compensation beyond 50% duty cycle Inherent in operation No gain change Requires coupled inductors

Table 1: Voltage Mode vs. Current Mode Control

An Optimum Digital Controller Architecture A prime example of the architecture shown in Figure 1C is the Silicon Laboratories Si825x family. This controller contains dedicated signal processing hardware that performs high-bandwidth operations, such as the filter and modulation functions, and a FLASH-programmable management processor to perform low-bandwidth loop optimization, system management and exception handling functions. The management processor is not in the high-bandwidth signal path allowing it to be simpler, lower cost and easier to program. This approach is not quite as flexible as the DSP implementation, but it can be made flexible enough to service a wide range of switch mode power supply applications. Using the processing capability of the Si825x, it is possible to create more sophisticated control algorithms that deliver the benefits of both voltage mode and current mode control while minimizing the liabilities of both. This "digital voltage mode control" is effectively a main voltage mode control loop combined with a series of smaller performance-enhancing loops. The Si825x is a single-chip, mixed-signal IC implemented in a low-cost CMOS technology useful in a wide range of DC/DC and AC/DC converter applications. Figure 4 shows the controller block diagram.

Fig.4. Digital Power Supply Controller Block Diagram

The Si825x is partitioned into a power-supply-specific hardware block DSP to provide a high-bandwidth, fully-independent digital control loop function and a softwareprogrammable system management processor section for system functionality. The hardware block control path includes a high-speed differential analog-to-digital controller (ADC), a voltage-reference digital-to-analog controller (DAC), a programmable infiniteimpulse response compensator and a six-phase DPWM finite-state machine. The reference DAC, ADC and compensator together generate a duty cycle control signal to modulate 6 independently controlled phase outputs of the DPWM. Protection circuits providing cycle-by-cycle current limiting and fault detection are integral parts of the hardware digital control loop. The system management processor section provides an instruction-based engine, including an 8-channel self-sequencing ADC, a 50 MIPS 8051based MCU, four 16-bit timers and other system peripheral I/O. Together they provide system initialization, control loop optimization, fault recovery, housekeeping, communication interface, soft start/stop and other user-defined functions. Other system functions include a high-precision (2.0%) oscillator, PLL clock multiplier for providing all necessary clocks to DSP and MCU, program storage non-volatile memory for userdefined programming, software-coded serial interface (for easy upgrade), UART and GPIO ports. To facilitate interfacing between two processors, monitor registers and configuration registers are provided. This controller has an architecture similar to analog voltage mode control. As shown, the control processor architecture of the Si825x maps directly to the analog voltage mode controller of Figure 2. Like its analog counterpart, the output voltage is subtracted from a reference voltage by a digital error amp consisting of a differential input analog-todigital converter (ADC) and digital filter. Digital error term u(n) is analogous to the analog error term, VERROR, in Figure A. The digital PWM (DPWM) is analogous to an analog PWM in that the output duty cycle is a function of the compensated error variable u(n). Like many analog controllers, there is a dedicated pulse-by-pulse current limiter that terminates the on-going portion of the PWM waveform when current reaches the maximum allowable value. While the control processor provides system closed-loop control, the system processor provides the programmable intelligence that leads to performance gains. The system processor contains a high-speed CPU and a 12-bit ADC to digitize key system parameters, such as input voltage and current. The CPU can be used as a multi-loop controller, utilizing information provided by the 12-bit ADC to optimize Control Processor behavior. That is, the CPU can manipulate control handles, such as switch control timing, voltage reference setting, protection thresholds and loop bandwidth, to improve system performance at every point of line and load. With this concept in mind, and again referring to Table 1, the areas where current mode has an advantage over voltage mode are as follows: Faster transient response Less complex compensation

Inherently-supported current sharing Inherently-supported transformer flux balancing Inherent pulse-by-pulse current limiting No loop gain change with changes in input voltage

The Si825x digital voltage mode control addresses each of these points as follows: Faster transient response: Nonlinear control can be applied to quickly resolve the transient. Here, the CPU increases compensator bandwidth at the onset of the transient and continuously regulates loop bandwidth until the transient is resolved (after which the default loop bandwidth settings are restored). Less complex compensation: Digital controller loop compensation is implemented in software. As such, compensation complexity has no impact on component count, board area or cost. Current sharing: The CPU can execute a current sharing feedback algorithm using output current as the control variable and the compensated duty cycle variable u(n) as the controlled variable. Transformer flux balancing: The CPU can execute a feedback algorithm using the effective voltage across the transformer as the control variable and timing phase symmetry as the controlled variable. Pulse-by-pulse current limiting: A digital controller like the Silicon Laboratories Si825x has dedicated onboard circuitry to provide cycle-by-cycle current limiting and overcurrent fault protection. Loop gain changes with input voltage: The CPU can execute a VIN feed-forward algorithm where VIN is the control variable and loop gain is the controlled variable. The algorithms outlined above supplement the basic voltage mode control methodology and help realize the advantages of current mode control. Of perhaps greater importance is the lack of drawbacks associated with current mode control, specifically noise susceptibility at low loads where the current ramp is shallow, the need for slope compensation at duty cycles above 50% and the need for coupled inductors in multioutput supplies. Other software control loops can be added beyond those listed above. For example, the CPU can adjust dead time to minimize input current, thereby maximizing efficiency.

Summary
Si825x digital power controller takes a dual-processor approach that separates all of the communication and housekeeping activities from the primary task of loop control. The dual-processor controller fits into QFN-28 and LQFP-32 packages. The Si825x operates with an internal 25 MHz system clock. An internal PLL based clock multiplier derives 50, 100 and 200 MHz clocks for the loop-control ADC, DPWM, and some peripherals. Programmable options include operation with an external clock with an on-chip, 3-bit programmable pre-scaler and an integrated 80 kHz, low-frequency clock useful for certain low-power, non-operational modes. Silicon Laboratories provides a dedicated 10 MHz, 6-bit loop-control ADC1 and a separate 12-bit ADC with an eight-channel multiplexer for current, temperature and other housekeeping measurements. This digital power controller provides both digital power control and power management functions for most isolated and non-isolated switch-mode power supply topologies.

References:
1. 2. 3. Don Alfano, A versatile Monolithic Digital PWM Controller, APEC 2005. Ka Leung, Optimizing System Operation Using a Flexible Digital PWM Controller, Digital Power Forum 2005. Dragan Maksimovic, et.al., Impact of Digital Control in Power Electronics, Proceedings of International Symposium on Power Semiconductor Devices & ICs, 2004.