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5.1 DRAM
(1) Principle of DRAM
MOSFET Gate
Source Drain
Fixed Voltage
Capacitor
Bit Line
119
120 Chapter 5
SiO 2
n+ n+
Capacitor MOSFET
Poly Si
fixed voltage p-type Si
The electron-hole pair generation around the FET by the IC package or natural
radiation changes the amount of charge on the capacitor, and sometimes destroys
the memory (soft error). In order to retain memory, the capacitance of the memory
capacitor must be higher than 30 fF (remember f = 10-15).
Explain the generation process of the depletion and inversion layers in a MOS
structure (p-type Si) using a simple energy band model as pictured in Fig. 5.3, when
a positive voltage is applied on the metal. Describe the Fermi level in the metal
region and the hole and electron concentrations using + and - symbols in the energy
band model. For simplicity, you can use the assumption that the flat band voltage is
close to zero.
Conduction band
Valence band
Metal M
Semiconductor (p-type)
Oxide O
Solution
Figure 5.4 shows the energy band change of a MOS structure (with a p-type
semiconductor) under an applied voltage.
(a) When the gate is forward-biased, holes will accumulate in the semiconductor
region near the oxide.
(b) When the gate is reverse-biased, a depletion layer (that is, a region depleted in
holes) is generated.
(c) When the applied voltage exceeds a certain threshold voltage (VT), an
inversion layer (an electron-rich region) is generated. This condition is given by:
semiconductor surface voltage ψs > ψB, where ψ B is the difference between the
intrinsic Fermi level (Ei) and the Fermi level (EF ) (ψ B = (kT/q) ln (Na/n i)).
electron
E1 < 0
EF hole
M O S
(a) Forward Bias
Metallic electrode
E2
SiO 2
E2 > 0 EF
Depletion layer
E3 > E2
EF
E3> 0
Inversion layer
Fig. 5.4 Energy band change of a MOS structure (with a p-type semiconductor)
under an applied voltage.
___________________________________________________________________
122 Chapter 5
Gate
SiO 2 film
Source n + Drain n +
p-type semiconductor
Solution
A positive gate voltage induces the electron inversion layer, which then connects
the n-type source and drain regions. The source terminal is the source of carriers
that flow through the channel to the drain terminal. In such an n-channel device,
electrons travel from the source to the drain so that the conventional current flows
from the drain to the source.
Remember that the depletion layer has low conductivity, which is analogous to a
shielded cable, a lead wire (the inversion layer) covered by an insulating coat (the
depletion layer). This is analogous to water flowing in a tube, where the water (the
electron) flows in a tube (the inversion layer) surrounded by rubber material (the
depletion layer). When the tube is pinched off, the water flow is restricted.
Making the assumption that the flat band voltage is close to zero, the application of
the gate voltage EG easily creates the inversion layer [Fig. 5.6(a)]. When a small
drain voltage (EDS < EG) is applied, the electrons in the inversion layers will flow
from the source to the positive drain terminal. Since for small EDS , the channel
region has the characteristics of a conducting lead, we expect
ID = g d EDS. (P.5.2.1)
When EDS is increased to the point where the potential drop across the oxide at the
drain terminal is equal to zero (precisely speaking, equal to the threshold voltage
VT), the induced inversion charge density is zero at the drain terminal. This effect
is schematically shown in Fig. 5.6(b). At this point (EDS = EG), the incremental
Ferroelectric Memory Devices 123
conductance at the drain becomes zero. The slope of the ID versus EDS curve
becomes zero.
When EDS becomes larger than the above value (EG), the point in the channel at
which the inversion charge is just zero shifts toward the source terminal [Fig.
5.6(c)]. In this case, electrons enter the channel at the source, travel through the
channel toward the drain, and then, at the pinch-off point the electrons are injected
into the space charge region (depletion layer) where they are swept by the E-field to
the drain contact. If we assume that the change in channel length is small compared
to the original length, the drain current becomes constant for EDS > EG. This
region is referred to as the saturation region. Figure 5.7 shows the ID versus EDS
curves.
EG EDS
Gate
Source n + Drain n +
Inversion layer
Electron flow (n channel) Depletion layer
(a) Drain voltage E DS < Gate voltage E G
Gate
Source n + Drain n +
Inversion layer
Electron flow Depletion layer
(b) Drain voltage E DS = Gate voltage E G
Gate
Source n + Drain n +
Depletion layer
Inversion layer
Electron flow
(c) Drain voltage E DS > Gate voltage E G
Fig. 5.6 Change in the n-channel with the drain/source voltage for an n-channel
enhancement mode MOSFET.
124 Chapter 5
EDS(Sat)=E G-VT
EG3 > EG2
EG1 > VT
Drain/Source Voltage E DS
Since the conventional SiO2 film plane structure cannot maintain a sufficient
capacitance with decreasing element area, a multilayer type and a trench type
(normal hole structure on a Si substrate) have been proposed. But these complexed
three-dimensional structures have their own limitations. Ferroelectric materials are
attractive for DRAM devices because of their high permittivities.2)
Because the dielectric constant of ferroelectrics is typically more than 1000, much
larger than the dielectric constant of 3.9 for SiO2 , when we use a ferroelectric thin
film with the same thickness as the SiO2 film, the capacitor size to obtain 30 fF is
significantly decreased, by 1/250 in terms of the area, or by 1/16 in linear scale.
Hence, much higher memory integration is possible for a ferroelectric DRAM
device. Of course, the situation will not be so simple because the thickness of the
ferroelectric film required to exhibit a sufficiently large permittivity sometimes
needs to be thicker than the SiO2 film typically used in the conventional MOS
structure.
The material first studied for this purpose was strontium titanate (SrTiO3 ), which
does not exhibit hysteres is in its polarization versus electric field curve or at the
permittivity peak in its temperature characteristics, and has a dielectric constant of
around 300 at room temperature. Note that for DRAM application, a high dielectric
constant is essential, but the typical ferroelectric dielectric hysteresis must be
avoided; this is accomplished by utilizing the paraelectric phase by operating just
above the Curie temperature.
The solid solution Ba xSr 1-xTiO3 [BST], between SrTiO3 and BaTiO3, has been
investigated also because of its larger dielectric constants at room temperature,
which can further improve the capacitor integration. The SiO2 equivalent thickness
of 0.47nm was reported using BST films.4)
The DRAM capacitor film must have high resistivity so as not to leak the
accumulated charge during the refreshing cycle. A leakage current less than 10-7
A/cm2 has been obtained for SrTiO 3 and Ba xSr 1-xTiO 3 films, which satisfies the
capacitance requirement for 256 Mbit level devices. General requirements for
DRAM capacitor thin films are:
The dry etching technique has been successfully applied for micro-machining of
ferroelectric films, and diffusion and contamination problems have been solved by
decreasing the film fabrication temperature and by carrying out the ferrolectric
fabrication as late as possible in all the processes. Thus, compatibility with the
semiconductor process has been established, and prototype 256 Mbit level DRAMs
have been fabricated and their function verified.
126 Chapter 5
Let us assume a P-E hysteresis loop of the ferroelectric film as illustrated in Fig.
5.9, and that the polarization state is on A. When a step voltage is applied and the
state shifts to B, the current flows according to the polarization difference between
A and B. On the contrary, when the polarization state is on C first, the current
increases dramatically because the spontaneous polarization reversal is associated.
Figure 5.10 shows the current responses to a series of pulses (two positive pulses
followed by two negative pulses) on a PZT film with 20 x 20 µm2 electrodes.5)
When a positive pulse is applied just after the negative pulses, a large current Iposi
is observed, which includes the polarization reversal. However, the second positive
pulse generates only a small current Iup . Thus, the observed current amount for a
positive pulse can indicate the initial polarization state; that is, an on or off state, or
1 or 0 state. In this memory device, after reading the initial state by applying the
positive voltage, the minimum polarization state becomes A for all the times; that is,
the reading process is destructive. Hence, in order to retain the memory state, a
writing process similar to the case of DRAM is required every time.
B
A
Electric field E
Fig. 5.9 Polarization versus electric field curve for a ferroelectric film.
Ferroelectric Memory Devices 127
Fig. 5.10 Current responses to a series of pulses (two positive pulses followed by
two negative pulses) on a PZT film with 20 x 20 µm2 electrodes.
The possible origins for the fatigue are related to the generation of oxygen
vacancies and the diffusion of ions. Much effort has been made to remedy this
problem. The proposed ideas can be categorized as follows:
Recent new thin film materials include layer-structure ferroelectrics. The so-called
Y1 material patented by Symmetrix, which has a basic composition of BiSr 2Ta 2O 9,
shows superior anti-fatigue properties. Figure 5.11 shows the fatigue characteristics
for rewriting the remanent polarization in Y1 and PZT films.6) The magnitude of
the remanent polarization does not change significantly in Y1 even after testing for
10 12 cycles, an improvement as is compared to the lifetime of 107 cycles for PZT.
New electrode materials RuO2 and Ir have been found to exhibit improvement in
fatigue in comparison with the conventional Pt electrode. Furthermore, new drive
modes such as a combination of the DRAM operation during the switch-on stage
and the memory mode during the switch-off stage have been proposed.
128 Chapter 5
Fig. 5.11 Fatigue characteristics for rewriting the remanent polarization in Y1 and
PZT films.
(2) MFSFET
Gate
SiO 2
Ferroelectric film
Source p + Drain p +
n-type Silicon
Fig. 5.13 Drain current versus gate voltage relation in an MFSFET with a PbTiO3
film fabricated on a SiO2/Si substrate.
Though the present devices have problems in fatigue and bistability characteristics,
this MFSFET structure is one of the ideal types, because no large electric field is
applied on the ferroelectric film during the reading process, nor is a rewriting
process required after reading, in contrast to the FRAM. In addition, the
polarization density required to control the Si surface potential is relatively small.
Thus, in general, the requirements for the ferroelectric film is greatly reduced in this
design.
The development of ferroelectric memory started with DRAMs, then moved into
FRAMs, and is now focused on MFSFETs. 256 Mbit level prototype DRAMs have
been manufactured already by several companies. Regarding the non-volatile
memory, 64 kbit level devices have been used on a trial basis for commuter train
tickets.
CHAPTER ESSENTIALS_________________________________
CHAPTER PROBLEM S
5.1 Surveying the recent literature, discuss and summarize the studies on
ferroelectric thin films from the following viewpoints.
(1) List the papers (minimum 5) which report on epitaxially grown PZT
films.
(2) Tabulate the experimentally obtained physical parameters of the PZT
films and compare with the data for bulk ceramics.
(3) Discuss the above deviation briefly with reference to the papers' results
and conclusions.
(4) Discuss the crystal orientation dependence of the physical parameters
of the PZT films by referring to the paper (Du, X. H., U. Belegundu and K.
Uchino, “Crystal Orientation Dependence of Piezoelectric Properties in
Lead Zirconate Titanate: Theoretical Expectation for Thin Films,” Jpn. J.
Appl. Phys., Vol.36 [9A], 5580-5587, 1997).
REFERENCES
1) D. A. Neamen: Semiconductor Physics and Devices, 2nd Edit., Irwin, Boston
(1997).
2) M. Okuyama: Ferroelectric Memory, Bull. Ceram. Soc. Jpn., 30 (No.6), 504
(1995).
3) S. Yamamichi, T. Sakuma, K. Takemura and Y. Miyasaka: Jpn. J. Appl. Phys., 30,
2193 (1991).
4) T. Sakaemori, Y. Ohno, H. Ito, T. Nishimura, T. Horikawa, T. Shibano, K. Sato
and T. Namba: Nikkei Micro Devices, No.2, 99 (1994).
5) T. Mihara, H. Watanabe, C. A. Pas de Araujo, J. Cuchiaro, M. Scott and L. D.
McMillan: Proc. 4th Int. Symp. on Integrated Ferroelectrics, Monterey, US, p.137,
March (1992).
6) H. Fujii, T. Ohtsuki, Y. Uemoto and K. Shimada: Jpn. Appl. Phys., Mtg. Appl.
Phys. Electronics, No.456, AP 942235, p.32 (1994).
7) Y. Matsui, H. Nakano, M. Okuyama, T. Nakagawa and Y. Yamakawa: Proc. 2nd
Mtg. Ferroelectric Mater. and Appl., Kyoto, p.239 (1979).