3rd International Conference on Computers and Devices for Communication (CODEC-06) CIS

Institute of Radio Physics and Electronics, University of Calcutta, December 18-20, 2006.

Incremental Encoder Reader Circuit with Error Detection and

Correction using FPGA
1
Arindam Sanyal, 2Snehasish Das, 3Sonai Ray, 4P.Venkateswaran, 5S.K.Sanyal and 6R.Nandi
1,2,4,5,6
Department of Electronics & Tele-Communication Engineering
Jadavpur University, Kolkata – 700 032.
3
Department of Computer Science & Engineering
Indian Institute of Technology Kharagpur
Kharagpur – 721 302.
( email ids : arindam_3110@yahoo.co.in, snehasishetce@yahoo.co.in, pvwn@yahoo.co.in, s_sanyal@ieee.org,
robnon@ieee.org )

Abstract- Design of incremental encoder interface

involves designing a circuit to decode the positional and
directional data embedded in the output signals of the
encoder , as well as designing a counter circuit to count
the number of pulses. This can be done either by using a channel A
custom IC or 5-10 discrete ICs. Four monostable
circuits would be needed to implement the direction
sensing unit. However, with the increase in number of
components, system reliability is reduced. Also, systems
are easily susceptible for interference by noise. This
paper presents a way of implementing the above channel B
functions using software only. In addition, the paper
provides a mechanism for efficient error correction, thus
making it suitable for servomotor control designs, even
under noisy conditions.

Keywords : Biphase , Control system , Encoder reader Fig. (1) Typical encoder waveform showing channel
circuit , Error correction , Forward pulse train , FPGA . B being 900 offset from channel A

I. INTRODUCTION
Whenever mechanical rotary motions have to
be monitored, an encoder is the most important
interface between the mechanical and the control
unit. Encoders transform rotary movement into a
sequence of electrical pulses. As only increments of
rotation are detected by a single channel, a second
signal, phase shifted by 90 degrees is also generated.
This second signal, along with the first signal,
enables the direction of rotation to be determined.
The two signals from channel A and B are shown in
Fig. (1) .
An incremental biphase encoder is the most
commonly used device in computer-controlled
feedback system. The microcomputer actuates
several final control elements based on the
information obtained from the encoder. In addition
to providing positional and directional information,
the encoder interface circuit must also perform some
special functions to maintain proper operations, such
as missing pulse correction, error correction, reseting
the position counter based on control signal from the
microcomputer, etc. It requires 5-10 discrete ICs to
implement all the above functions. Also certain
types of combinational logic are error prone due to
gate delays or threshold offsets and multivibrator
imprecisions. This paper tries to do away with these
errors as well as reducing drastically the amount of
hardware needed. The scheme is explained in
section II and the implementation details are given in
section III.

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3rd International Conference on Computers and Devices for Communication (CODEC-06)
Institute of Radio Physics and Electronics, University of Calcutta, December 18-20, 2006.
II. PROPOSED SCHEME
A. Edge Detection algorithm
The change of states of signals A and B as
Fig. (1) can be represented in the form of the
following state diagram:
00
10 01
11
Fig. (2a) State transition diagram of a biphase
incremental encoder dashed lines indicate erroneous
transition.
The above state diagram has been formed taking
the value of channel A as the msb ( most significant
bit ) and the value of channel B as the lsb ( least
significant bit ). The state transition from
00→01→
11 →10 is denoted by FPT( forward pulse train ) and
the state transition from 00→10→11→01 is denoted
by RPT( reverse pulse train ). The erroneous state
transitions are shown by dotted lines. The above
state diagram has been used to obtain the following
state model : A counter is incremented at every
forward transition and decremented at every reverse
transition of the signals A and B. Thus the value of
the counter at any instant gives the total number of
edges detected.
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CIS
00
S1
00
01
10
00
10 S4 S2 01
01
11
11
10
S3
11
Fig. (2b) State diagram of the encoder reader circuit
B. Error Handling algorithm
There may be errors introduced into the
signals A and B due to noise. The effect of the noise
is to change the input voltage level so that a 1 may
appear as a 0 or vice versa. Any erroneous state
transition can be found as shown in Fig. (2a).
Depending on the direction of the previous state
transitions, the program then takes the input signals
to their correct states, for example in fig. 2b), if the
current state is S1 and the input is 11 then the
program will sense an error and send the next state to
either S4 or S2 depending on the direction of the
previous transitions. Also, the effect of the noise
may be such that it does not trigger any invalid
transition. This can happen if there are spikes
between two cycles of signals A and B. The effect
of a spike is to trigger an fpt and an rpt in succession,
thus resulting in no change in the counter. Thus the
algorithm can effectively correct any error due to
noise.
III. IMPLEMENTATION
The program was simulated using ModelSim
XE III 6.a. We give below two snapshots of our
simulations in Fig.s (3a) and (3b). For the first
waveform Fig. (3a), error free signals phase-shifted
by 90 degrees applied to the inputs of the encoder
reader circuit, and the count value is taken after 8
cycles. The counter rightly indicates the value as 32.
For the second waveform Fig. (3b) a test bench was
3rd International Conference on Computers and Devices for Communication (CODEC-06) CIS
Institute of Radio Physics and Electronics, University of Calcutta, December 18-20, 2006.

designed to simulate the effect of noise. The signals 32 after 8 cycles, thus indicating that the algorithm
distorted by noise are applied to the inputs of the works even if the inputs are corrupted by noise.
encoder reader circuit, and again the count value is
taken after 8 cycles. Once again, the counter reads

Fig. (3a) Snapshot of the simulated waveform in the absence of noise

Fig. (3b) Snapshot of the simulated waveform in the presence of noise

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3rd International Conference on Computers and Devices for Communication (CODEC-06) CIS
Institute of Radio Physics and Electronics, University of Calcutta, December 18-20, 2006.

IV. CONCLUSION [1] E. S. Tez, “Interfacing bi-phase incremental encoders”, IEEE

An efficient error correcting mechanism for
biphase encoder interface has been described. The
implementation details and the simulation results
have been given above. Using this implementation
the system reliability can be increased thus making it
a favourable tool for automatic control system.
REFERENCES
Trans. Ind. Electron, Vol. IE – 33, No. 3, Aug. 1986, pp. 337-
339
[2] Bernard Hebert, Michel Brule and Louis- A. Dessaint, “A
high efficiency interface for a biphase incremental encoder
with error detection” , IEEE Trans. Ind. Electron, Vol. 40,
No. 1, Feb.1998, pp. 155
[3] J Bhasker A VHDL Synthesis Primer, Star Galaxy Publishing,
Revised 2nd Edition
[4] Xilinx Spartan 3 FPGA Trainer User Manual, Vi
Microsystems Pvt Ltd, Chennai-600096

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