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Zuber Basha Shaik1, Akurathi.Srinivasarao2 Electronics and Communication Engineering Nimra College of Engineering and Technology Krishna (D.T), Andhra Pradesh, India. e-mail: 1Shaik.zuberbasha@gmail.com, 2Akurathi.srinivasarao@gmail.com

International Journal of Systems , Algorithms & Applications

Design of DDR3 SDRAM Controller for Achieving High Speed Read Operation

Abstract In computing, DDR3 SDRAM or double-datarate three synchronous dynamic random access memories is a random access memory interface technology used for high bandwidth storage of the working data of a computer or other digital electronic devices. DDR3 SDRAM is the 3rd generation of DDR memories, featuring higher performance and lower power consumption. In comparison with earlier generations, DDR1/2 SDRAM, DDR3 SDRAM is a higher density device and achieves higher bandwidth due to the further increase of the clock rate and reduction in power consumption. In this work, the DDR3 SDRAM controller is designed and it can interface with Look up table based Hash CAM circuit. Content-addressable memory (CAM) is a special type of computer memory used in certain very high speed searching applications. Because a CAM is designed to search its entire memory in a single operation, it is much faster than RAM in virtually all search applications. The architecture of DDR3SDRAM controller consists of Initialization FSM, Command FSM, data path, bank control, clock counter, refresh counter, Address FIFO, command FIFO, Wdata FIFO and Rdata reg . Now here an advanced DDR3 SDRAM controller architecture was designed and which can interface with a high performance Hash-CAM based lookup circuit. Basically the DDR3 SDRAM controller can perform normal write, normal read and fast write operations, in this paper a ddr3 controller is designed to achieve fast read operation to achieve high performance throughput in many network systems and these results are verified by simulation and DDR3 SDRAM controller is synthesized.

mance, higher memory density and lower cost. Here the efficient bandwidth usage is major part for lookup functions. However, a DDR3 SDRAM controller must be designed to achieve good read efficiency and for high bandwidth. 2. DESIGN METHODOLOGY DDR3 SDRAM devices are the next generation devices in the DDR SDRAM family. DDR3 SDRAM is third generation of DDR memories, providing higher performance and lower power consumption. The primary benefit of DDR3 is the ability to transfer I/O data at eight times the data rate of the memory cells it contains, thus enabling higher bus rates and higher peak rates than earlier memory technologies. However, there is no corresponding reduction in latency, which is therefore proportionally higher. In addition, the DDR3 standard allows for chip capacities of 512 megabits to 8 gigabits, effectively enabling a maximum memory module size of 16 gigabytes.

1.INTRODUCTION In the recent advanced developed network systems, the processing techniques of data, i.e. in packets form which deal with massive content to achieve high throughput packet of the internet. Now a days according to the advances in memory architecture we must need to meet the bandwidth requirements. Content based techniques are widely used for achieving fast table lookup. Unlike standard computer memory (random access memory or RAM) in which the user supplies a memory address and the RAM returns the data word stored at that address, a CAM is designed such that the user supplies a data word and the CAM searches its entire memory to see if that data word is stored anywhere in it. If the data word is found, the CAM returns a list of one or more storage addresses where the word was found (and in some architecture, it also returns the data word, or other associated pieces of data). Recently a Hash-CAM circuit, which combines the advantages of hash algorithm and CAM functionality was used in the place of pure CAM based lookup circuits with some comparable parameters like perfor-

Fig 1 : DDR3 SDRAM data rate.

The frequencies of DDR3 memory could be raised beyond those of DDR2 due to doubling of the data prefetch that was moved from the information storage device to the input/output buffer. While DDR2 SDRAM uses 4-bit samples, DDR3 SDRAM uses 8-bit prefetch also known as 8n-prefetch, as shown in fig 1. In other words, DDR3 SDRAM technology implies doubling of the internal bus width between the actual DRAM core and the input/output buffer. The proposed Hash-CAM based look up circuit is shown in Figure 2.

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Design of DDR3 SDRAM Controller for Achieving High Speed Read Operation

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International Journal of Systems , Algorithms & Applications

Rdata reg gets the data from the data path module normal and fast read operation. In this paper the designed DDR3 controller provides interface to the Hash-CAM circuit and the DDR Memory Banks. If the data word is found, the CAM returns a list of one or more storage addresses where the word was found (and in some architecture, it also returns the data word, or other associated pieces of data). Because a CAM is designed to search its entire memory in a single operation, it is much faster than RAM in virtually all search applications. 2.1 Timing and Bank Acess Control of DDR3 sdram The most important parameters to consider in ddr3 technology are column address strobe latency (tCAS), RAS to CAS latency (tRCD), RAS precharge time (tRP), row active time (tRAS). The ddr3 commands are given below table 1. Depending on these commands only we can perform operations like auto refresh, write, read, precharge etc. Table 1: DDR3 SDRAM commands

Fig 2 : Hash-CAM lookup circuit for DDR3 SDRAM.

The original data and reference address information are stored in the DDR3 SDRAM lookup request (data input) for a given content is pipelined and processed by the Hash circuit to generate an address. This address value is forwarded to DDR3 SDRAM Interface where it is translated into instructions and addresses that are recognized by the DDR3 memory as an access. The stored data & addresses in the memory are read back to the Hash-CAM circuit in order to validate the match. In the case of corresponding reference address is reference address is returned.

Fig 3: Functional block diagram of DDR3 SDRAM controller.

The functional block diagram of the DDR3 controller is shown in Fig 3. The architecture of DDR3SDRAM controller consists of Initialization FSM Command FSM, data path, bank control, clock counter, refresh counter, Address FIFO, command FIFO, Wdata FIFO and Rdata reg . Initialization FSM generates proper i_State to initialize the modules in the design. Command FSM generates c_State to perform the normal write, read and fast write, read operations. The data path module performs the data latching and dispatching of the data between Hash-CAM unit and DDR3SDRAM banks. The Address FIFO gives the address to the Command FSM so the bank control unit can open particular bank and address location in that bank. The Wdata FIFO provides the data to the data path module in normal and fast write operation. The
Volume 2, Issue 1, January 2012, ISSN Online: 2277-2677

The controller has the ability to keep four banks open at a time. The banks are opened in the order of the commands that are presented to the controller. In the event four banks are already opened and an access arrives to the fifth bank, the least recently activated bank will be closed and the new bank will be opened. All the banks are closed during auto refresh and will be opened as commands are presented to the controller. The controller opens a row in a bank if that bank and row are not already opened. In the case of an access to a different row in an already opened bank, the controller closes the row in that bank and opens the new row. The controller moves to the Read/Write states after opening the banks if the banks are already opened. 2.2 Initialization FSM Diagram Before normal memory accesses can be performed, DDR3 needs to be initialized by a sequence of commands. The initialization FSM states are shown in fig 4, which are i_IDLE, i_NOP, i_PRE, i_ERMS, i_MRS, i_tRP, i_tMRD, i_AR1,i_tRFC1,i_AR2,i_tRFC2, i_ready.
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Design of DDR3 SDRAM Controller for Achieving High Speed Read Operation

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International Journal of Systems , Algorithms & Applications

After the initialization has done the command FSM can decide depending on the input signals, in this it first activates, after the activation it decides the operation to be performed, i.e. c_READA, C_WRITEA inputs came from Command FIFO, and Address of the particular location or locations provided by address FIFO, which are shown in fig 5.

Fig 4 : Initialization of FSM (Finite State machine).

First one is the idle state, next is the no operation state ,after that precharge state to precharge capacitors, i.e. rows in memory, after the completion of precharge next state is extended register mode set, in this the register is programmed as per the requirements some are Bank selection, Write, CAS latency , Burst length etc. After this two autorefresh must be applied after that the mode register is set which implies now the initialization of FSM is done is indicated by setting the bit in load mode register. Now the overall initialization is done by these commands and they can give as inputs to the command FSM to continue the next module in the process, for this command FSM the clocking signals and refresh signals can be provided by Clock Counter and Refresh Counter. 2.3 Command FSM State Diagram

Fig 6 : Command FSM with Fast read with auto precharge.

Fast read can be achieved by switching banks. Bank control logic is used to issue desired bank addresses at each cycle when a bank active command or read command is issued. The state machine for this method is given in Fig 6. The proposed controller provides the control interface for switching between normal write/read mode and fast read mode. Unlike other data processing techniques, the distinct characteristic of the random data lookup is the uncertainty of the incoming data. In this work, address FIFOs are applied to buffer the row/column addresses separately for each read request. The empty flag of the row address FIFO (addr_fifo_empty) is checked in order to evaluate whether the next command is active (ACT) or read (RDA).in this we are achieving the fast read operation by reducing the latencies occurred during processing of controller. 3. TIMING DIAGRAMS The figures 7 and 8 are the read cycle and write cycle timing diagrams of the reference design with the two CAS latency cycles and the burst length of four. The timing diagrams may be different due to the values of the timing delays tMRD/tRP/tRFC/tRCD/tRCD/tWR, the clock period tCK, the CAS latency and the burst length. The total number of clocks for read and writes cycles are decided by these factors. In the example shown in the figures, the read cycle takes 10 clocks and the write cycle takes 9 clocks.

Fig 5 : Command FSM with Normal read and write.

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Design of DDR3 SDRAM Controller for Achieving High Speed Read Operation

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International Journal of Systems , Algorithms & Applications

The state variable c_State of CMD_FSM is also shown in these figures. Note that the ACTIVE, READ, WRITE commands are asserted one clock after the c_ACTIVE, c_READA, c_WRITEA states respectively. The values of the region filed with slashes in the system interface input signals of these figures are dont care. For example, signal sys_R_Wn needs to be valid only at the clock before CMD_FSM switches to the c_READA or c_WRITEA states. Depending on the values of tRCD and tCK, this means the signal sys_R_Wn needs to be valid at state c_ACTIVE or the last clock of state c_tRCD.

Hash-CAM sub block is designed to work at quad rate at 100mhz.

Fig 9 : Normal read operation (a)

Fig 7 : Write cycle timing diagram.

Fig 10 : Normal read operation (b)

Fig 11 : Fast read operation (a)

Fig 8 : Read cycle timing diagram.

4. EXPERIMENTAL RESULTS In the implementation of DDR3 SDRAM controller for normal read and fast read operations can be seen in below figs 9-12,the diference between the normal and fast read can be decided by conidering the diffferent latencies, in the below figures the latencies can be seen as reducing but we need to consider the main signals sdr_RASn, sdr_CASn, sdr_WEn. This prototype is designed to work at half rate frequency 200mz and the
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Fig 12 : Fast read operation (b)

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Design of DDR3 SDRAM Controller for Achieving High Speed Read Operation

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International Journal of Systems , Algorithms & Applications

5. CONCLUTIONS In this paper we have designed a High speed DDR3 SDRAM Controller with 64-bit data transfer which synchronizes the transfer of data between DDR RAM and External peripheral devices like host computer, laptops and so on. The advantages of this controller compared to SDR SDRAM , DDR1 SDRAM and DDR2 SDRAM is that it synchronizes the data transfer, and the data transfer is twice as fast as previous, the production cost is also very low, the Higher frequencies enable higher rates of data transfer,DDR3 SDRAM standards are still being developed and improved in future trends. REFERENCES
1. A. J. McCauley, et al, Fast Routing Table Lookup Using CAMs, Proceedings on 12th Annual Joint Conference of the IEEE Computer and Communications Societies (INFOCOM), Vol.3, March 1993, pp.1382 1391. 2. X. Yang, et al, High Performance IP Lookup Circuit Using DDR SDRAM, IEEE International SOC Conference (SOCC), Sept. 2008, pp. 371-374. 3. G. Allan, The Love/Hate Relationship with DDR SDRAM Controllers, MOSAID Technologies Whitepaper, 2006. 4. H. Kim, et al, High-Performance and Low-Power Memory- Interface Architecture for Video Processing Application, IEEE Transac-

tions on Circuit and Systems for Video Technology, Vol. 11, Nov. 2001, pp. 1160-1170. 5. E. G. T. Jaspers, et al, Bandwidth Reduction for Video Processing in Consumer Systems, IEEE Transactions on Consumer Electronics, Vol. 47, No. 4, Nov. 2001, pp. 885- 894. 6. N. Zhang, et al, High Performance and High Efficiency Memory Management System for H.264/AVC Application in the Dual-Core Platform, ICASE, Oct. 2006, pp. 5719-5722. 7. J. Zhu, et al, High Performance Synchronous DRAMs Controller in H. 264 HDTV Decoder, Proceedings of International Conference on Solid-State and Integrated Circuits Technology, Vol. 3, Oct. 2004, pp. 1621-1624. 8. High-Performance DDR3 SDRAM Interface in Virtex-5 Devices, Xilinx, XAPP867 (v1.0), Sept 24, 2007. 9. T. Mladenov, Bandwidth, Area Efficient and Target Device Independent DDR SDRAM Controller, Proceedings of World Academy of Science, Engineering and Technology, Vol. 18, De. 2006, pp. 102106. 10. DDR3 SDRAM Specification (JESD79-3A), JEDEC Standard, JEDEC Solid State Technology Association, Sept. 2007. 11.www.altera.com/literature/ug/ug_altmemphy.pdf, External DDR Memory PHY Interface Megafunction User Guide (ALTMEMPHY) accessed on 23 Feb. 2009.

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