STE70NM50

N-CHANNEL 500V - 0.045 - 70A ISOTOP Zener-Protected MDmeshPower MOSFET

TYPE STE70NM50
n n n n n n n

VDSS 500V

RDS(on) < 0.05

ID 70 A

TYPICAL RDS(on) = 0.045 HIGH dv/dt AND AVALANCHE CAPABILITIES IMPROVED ESD CAPABILITY LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL INDUSTRYS LOWEST ON-RESISTANCE

ISOTOP

DESCRIPTION The MDmesh is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Companys PowerMESH horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Companys proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competitions products. APPLICATIONS The MDmesh family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies.

INTERNAL SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol VDS VDGR VGS ID ID IDM (l) PTOT VESD(G-S) dv/dt (1) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Gate source ESD(HBM-C=100pF, R=15K) Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature Value 500 500 30 70 44 280 600 6 5 15 65 to 150 150
(1)ISD 60A, di/dt 400A/s, V DD V(BR)DSS, Tj T JMAX

Unit V V V A A A W KV W/C V/ns C C 1/8

()Pulse width limited by safe operating area

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STE70NM50
THERMAL DATA
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max Max 0.2 30 300 C/W C/W C

Maximum Lead Temperature For Soldering Purpose

AVALANCHE CHARACTERISTICS
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 35 V) Max Value 30 1.4 Unit A J

ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF

Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20V Min. 500 10 100 10 Typ. Max. Unit V A A A

ON (1)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250A VGS = 10V, ID = 30A Min. 3 Typ. 4 0.045 Max. 5 0.05 Unit V

DYNAMIC
Symbol gfs (1) Ciss Coss Crss RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain Test Conditions VDS > ID(on) x RDS(on)max, ID = 30A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 35 7500 980 200 1.5 Max. Unit S pF pF pF

Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.

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ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 250V, ID = 30A RG = 4.7 VGS = 10V (see test circuit, Figure 3) VDD = 400V, ID = 60A, VGS = 10V Min. Typ. 51 58 190 53 97 266 Max. Unit ns ns nC nC nC

SWITCHING OFF
Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 400V, ID = 60A, RG = 4.7, VGS = 10V (see test circuit, Figure 5) Min. Typ. 51 46 108 Max. Unit ns ns ns

SOURCE DRAIN DIODE

Symbol ISD ISDM (2) VSD (1) trr Qrr Irrm trr Qrr Irrm Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 60A, VGS = 0 ISD = 60A, di/dt = 100A/s, VDD = 100 V, Tj = 25C (see test circuit, Figure 5) ISD = 60A, di/dt = 100A/s, VDD = 100 V, Tj = 150C (see test circuit, Figure 5) 532 9.9 37 636 13.4 42 Test Conditions Min. Typ. Max. 60 240 1.5 Unit A A V ns C A ns C A

Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area.

GATE-SOURCE ZENER DIODE

Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs= 1mA (Open Drain) Min. 30 Typ. Max. Unit V

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the devices ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the 25V Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the devices integrity. These integrated Zener diodes thus avoid the usage of external components.

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Safe Operating Area Thermal Impedance

Output Characteristics

Transfer Characteristics

Transconductance

Static Drain-source On Resistance

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Gate Charge vs Gate-source Voltage Capacitance Variations

Normalized Gate Threshold Voltage vs Temp.

Normalized On Resistance vs Temperature

Source-drain Diode Forward Characteristics

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STE70NM50
Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform

Fig. 3: Switching Times Test Circuit For Resistive Load

Fig. 4: Gate Charge test Circuit

Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times

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ISOTOP MECHANICAL DATA

DIM. MIN. A B C D E F G H J K L M N O 11.8 8.9 1.95 0.75 12.6 25.15 31.5 4 4.1 14.9 30.1 37.8 4 7.8 8.2 4.3 15.1 30.3 38.2 mm TYP. MAX. 12.2 9.1 2.05 0.85 12.8 25.5 31.7 MIN. 0.466 0.350 0.076 0.029 0.496 0.990 1.240 0.157 0.161 0.586 1.185 1.488 0.157 0.307 0.322 0.169 0.594 1.193 1.503 inch TYP. MAX. 0.480 0.358 0.080 0.033 0.503 1.003 1.248

G O B

J K L M

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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com

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