nRF905

Single chip 433/868/915MHz Transceiver

Product Specification
Key Features
True single chip GFSK transceiver in a small 32 pin package (32L QFN 5x5mm) ShockBurst mode for low power operation Power supply range 1.9 to 3.6 V Multi channel operation ETSI/FCC Compatible Channel switching time <650s Extremely low cost Bill of Material (BOM) No external SAW filter Adjustable output power up to 10dBm Carrier detect for "listen before transmit" protocols Data Ready signal when a valid data packet is received or transmitted Address Match for detection of incoming packet Automatic retransmission of data packet Automatic CRC and preamble generation Low supply current (TX), typical 9mA @ -10dBm output power Low supply current (RX), typical 12.5mA

Applications
Wireless data communication Alarm and security system Home automation Remote control Surveillance Automotive Telemetry Keyless entry Toys

All rights reserved. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. April 2008

nRF905 Product Specification Liability disclaimer

Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out of the application or use of any product or circuits described herein. All application information is advisory and does not form part of the specification.

Limiting values
Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the specifications are not implied. Exposure to limiting values for extended periods may affect device reliability.

Life support applications

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic Semiconductor ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such improper use or sale. Data sheet status Objective product specification

This product specification contains target specifications for product development. Preliminary product specification This product specification contains preliminary data; supplementary data may be published from Nordic Semiconductor ASA later. Product specification This product specification contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

Contact details
Visit www.nordicsemi.no for Nordic Semiconductor sales offices and distributors worldwide Main office:

Otto Nielsens vei 12 7004 Trondheim Phone: +47 72 89 89 00 Fax: +47 72 89 89 89 www.nordicsemi.no

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nRF905 Product Specification Writing conventions

This product specification follows a set of typographic rules that makes the document consistent and easy to read. The following writing conventions are used: Commands, bit state conditions, and register names are written in Courier. Pin names and pin signal conditions are written in Courier bold. Cross references are underlined and highlighted in blue.

Revision history
Date June 2006 April 2008 Version 1.4 1.5 Description Restructured layout in the new template Updated package information Added moisture sensitivity level to the absolute maximum ratings

Attention! Observe precaution for handling Electrostatic Sensitive Device.

Datasheet order code: 051005nRF905

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nRF905 Product Specification Contents

1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 9.1 9.2 9.3 9.4 9.5 10 10.1 10.2 10.3 10.4 10.5 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 12 12.1 12.2 12.3 12.4 12.5 13 Introduction ............................................................................................... Quick reference data................................................................................. Block Diagram ........................................................................................... Absolute maximum ratings ...................................................................... Electrical Specifications........................................................................... Current Consumption ............................................................................... Pin information.......................................................................................... Pin Assignment ................................................................................... Pin Functions ....................................................................................... Modes of Operation ................................................................................. Active Modes ....................................................................................... Power Saving Modes .......................................................................... nRF ShockBurst Mode ..................................................................... Typical ShockBurst TX .................................................................... Typical ShockBurst RX ..................................................................... Power Down Mode ............................................................................... Standby Mode ...................................................................................... Device Configuration ............................................................................... SPI Register Configuration................................................................... SPI Instruction Set .............................................................................. SPI Timing............................................................................................ RF Configuration Register Description.............................................. Register Contents ................................................................................ Important Timing Data .............................................................................. Device Switching Times ....................................................................... ShockBurst TX timing ....................................................................... ShockBurst RX timing....................................................................... Preamble .............................................................................................. Time On Air .......................................................................................... Peripheral RF Information ........................................................................ Crystal Specification............................................................................. External Clock Reference ................................................................... Microprocessor Output Clock ............................................................... Antenna Output .................................................................................... Output Power Adjustment .................................................................... Modulation ........................................................................................ Output Frequency ................................................................................ PCB Layout and Decoupling Guidelines .............................................. nRF905 features ....................................................................................... Carrier Detect ....................................................................................... Address Match ..................................................................................... Data Ready .......................................................................................... Auto Retransmit ................................................................................... RX Reduced Power Mode.................................................................... Mechanical specifications........................................................................ 6 7 8 9 10 13 14 14 15 16 16 16 16 16 18 19 19 20 20 21 21 23 24 26 26 26 27 27 27 28 28 28 28 29 29 29 29 30 31 31 31 31 31 32 33

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nRF905 Product Specification

14 Ordering information................................................................................. 34 14.1 Package marking.................................................................................. 34 14.1.1 Abbreviations ................................................................................... 34 14.2 Product options..................................................................................... 34 14.2.1 RF silicon ......................................................................................... 34 14.2.2 Development tools ........................................................................... 34 15 Application Examples ............................................................................... 35 15.1 Differential Connection to a Loop Antenna........................................... 35 15.2 PCB Layout Example; Differential Connection to a Loop Antenna....... 36 15.3 Single ended connection to 50W antenna............................................ 37 15.4 PCB Layout Example; Single Ended Connection to 50W Antenna ...... 40 16 Glossary of terms ..................................................................................... 41

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nRF905 Product Specification 1 Introduction

nRF905 is a single chip radio transceiver for the 433/868/915MHz ISM band. The transceiver consists of a fully integrated frequency synthesizer, receiver chain with demodulator, a power amplifier, a crystal oscillator and, a modulator. The ShockBurst feature automatically handles preamble and CRC. You can easily configure the nRF905 through the SPI. Current consumption is very low, in transmit only 9mA at an output power of -10dBm, and in receive mode 12.5mA. Built-in power down modes makes power saving easily realizable.

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nRF905 Product Specification 2 Quick reference data

Parameter Minimum supply voltage Maximum transmit output power Data rate Supply current in transmit @ -10dBm output power Supply current in receive mode Temperature range Typical sensitivity Supply current in power down mode Value 1.9 10 50 9 12.5 -40 to +85 -100 2.5 Unit V dBm kbps mA mA C dBm A

Table 1. nRF905 quick reference data.

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nRF905 Product Specification 3 Block Diagram

DVDD_1V2 (31)

VDD (17)

VDD (25)

VSS (16)

VSS (18)

VSS (22)

VSS (24)

VSS (26)

VSS (27)

VSS (28)

VSS (29)

VSS (30)

VDD (4)

VSS (5)

VSS (9)

MISO (10) MOSI (11) SCK (12) CSN (13)

XC1 (14)

IF BBF

TRX_CE (1) PWR_UP (2) TX_EN (32)

SPI interface TX - addr. TX - reg. RX - reg. Config-reg. ShockBurst Demod Dataslicer CRC code/ decode Address decode GFSK filter Manchester encoder/ decoder

Voltage regulators

Crystal oscillator

XC2 (15)

LNA

Frequency Synthesiser

VDD_PA (19)

CD (6) AM (7) DR (8)

ANT1 (20)

PA

uPCLK (3)

ANT2 (21)

IREF (23)

Figure 1. nRF905 with external components.

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nRF905 Product Specification 4 Absolute maximum ratings

Operating conditions Supply voltages VDD VSS Input voltage VI Output voltage VO Total power dissipation PD (TA=85C) Temperatures Operating temperature Storage temperature Moisture sensitivity level Minimum -0.3 -0.3 -0.3 Maximum +3.6 0 VDD +0.3 VDD +0.3 200 -40 -40 +85 +125 260 Units V V V V mW

C C C

Note: Stress exceeding one or more of the limiting values may cause permanent damage to the device. Table 2. Absolute maximum ratings

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nRF905 Product Specification 5 Electrical Specifications

Conditions: VDD = +3V VSS = 0V, TEMP = -40C to +85C (typical +27C) Symbol VDD TEMP Parameter (condition) Supply voltage Operating temperature Notes Min. 1.9 -40 Typ. Max. 3.6 85 Units V C

Table 3. Operating conditions Symbol VIH VIL Ci

IiL

VOH VOL

Parameter (condition) HIGH level input voltage LOW level input voltage Pin capacitance Pin leakage current HIGH level output voltage (IOH=-0.5mA) LOW level output voltage (IOL=0.5mA)

Notes

Min. 0.7VDD VSS

Typ.

VDD-0.3 VSS

Max. VDD 0.3VDD 5 10 VDD 0.3

Units V V pF nA V V

a. Max value determined by design and characterization testing.

Table 4. Digital input/output Symbol Istby_eclk Istby_dclk IPD ISPI

a. b. c. d.

Parameter (condition) Supply current in standby, uCLK enabled Supply current in standby, uCLK disabled Supply current in power down mode Supply current in SPI programming

Notes
a b c d

Min.

Typ. 100 12.5 2.5 20

Max.

Units A A A A

Output frequency is 4MHz load of external clock pin is 5pF, Crystal is 4MHz. Crystal is 4MHz. Pin voltages are VSS or VDD. Chip in power down, SPI_SCK frequency is 1MHz.

Table 5. Electrical specifications

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nRF905 Product Specification

Symbol fOP fXTAL f BR fCH433 fCH868/915

Parameter (condition) Operating frequency Crystal frequency Frequency deviation Data rate Channel spacing for 433MHz band Channel spacing for 868/ 915MHz band

Notes
a b c

Min. 430 4 42

Typ.

50 50 100 200

Max. 928 20 58

Units MHz MHz kHz kbps kHz kHz

a. Operates in the 433, 868 and 915MHz ISM band. b. The crystal frequency may be chosen from 5 different values (4, 8, 12, 16, and 20MHz). c. Data is Manchester encoded before GFSK modulation.

Table 6. General RF conditions Symbol PRF10 PRF6 PRF-2 PRF-10 PBW_-16 PBW_-24 PBW_-32 PBW_-36 PRF1 PRF2 ITX10dBm ITX-10dBm Parameter (condition) Notes a Output power 10dBm setting a Output power 6dBm setting a Output power 2dBm setting a Output power -10dBm setting b -16dBc bandwidth for modulated carrier b -24dBc bandwidth for modulated carrier b -32dBc bandwidth for modulated carrier b -36dBc bandwidth for modulated carrier 1st adjacent channel transmit power 2nd adjacent channel transmit power Supply current @ 10dBm output power Supply current @ -10dBm output power
c c

Min. 7 3 -6 -14

Typ. 10 6 -2 -10 173 222 238 313 -27 -54 30 9

Max. 11 9 2 -6

Units dBm dBm dBm dBm kHz kHz kHz kHz dBc dBc mA mA

a. Optimum load impedance, please see peripheral RF information. b. Data is Manchester encoded before GFSK modulation. c. Channel width and channel spacing is 200kHz.

Table 7. Transmitter operation Symbol IRX RXSENS RXMAX C/ICO C/I1ST C/I2ND C/I+1M C/I-1M C/I-2M Parameter (condition) Supply current in receive mode Sensitivity at 0.1%BER Maximum received signal C/I Co-channel 1 adjacent channel selectivity C/I 200kHz 2nd adjacent channel selectivity C/I 400kHz Blocking at +1MHz Blocking at -1MHz Blocking at -2MHz
st

Notes

Min.

Typ. 12.5 -100 13 -7 -16 -40 -50 -63

Max.

0
a a a a a a

Units mA dBm dBm dB dB dB dB dB dB

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nRF905 Product Specification

Symbol C/I+5M C/I-5M C/I+10M C/I-10M C/IIM Parameter (condition) Blocking at +5MHz Blocking at -5MHz Blocking at +10MHz Blocking at -10MHz Image rejection Notes
a a a a a

Min.

Typ. -70 -65 -69 -67 -36

Max.

Units dB dB dB dB dB

a. Channel Level +3dB over sensitivity, interfering signal a standard CW, image lies 2MHz above wanted.

Table 8. Receiver operation

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nRF905 Product Specification 6 Current Consumption

Crystal freq. Output clock Typical current (MHz) Freq. (MHz) Power Down 16 OFF 2.5uA Standby 4 OFF 12uA Standby 8 OFF 25uA Standby 12 OFF 27uA Standby 16 OFF 32uA Standby 20 OFF 46uA Standby 4 0.5 110uA Standby 8 0.5 125uA Standby 12 0.5 130uA Standby 16 0.5 135uA Standby 20 0.5 150uA Standby 4 1 130uA Standby 8 1 145uA Standby 12 1 150uA Standby 16 1 155uA Standby 20 1 170uA Standby 4 2 170uA Standby 8 2 185uA Standby 12 2 190uA Standby 16 2 195uA Standby 20 2 210uA Standby 4 4 260uA Standby 8 4 275uA Standby 12 4 280uA Standby 16 4 285uA Standby 20 4 300uA Rx @ 433 16 OFF 12.2mA Rx @ 868/915 16 OFF 12.8mA Reduced Rx 16 OFF 10.5mA Tx @ 10dBm 16 OFF 30mA Tx @ 6dBm 16 OFF 20mA Tx @ -2dBm 16 OFF 14mA Tx @ -10dBm 16 OFF 9mA Conditions: VDD = 3.0V, VSS = 0V, TA = 27C, Load capacitance of external clock = 13pF, Crystal load capacitance = 12pF Mode Table 9. nRF905 current consumption

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nRF905 Product Specification 7 7.1 Pin information Pin Assignment

TX_EN DVDD_1V2 VSS VSS VSS VSS VSS VDD

32
TRX_CE

31

30

29

28

27

26

25 24
VSS

1 2 3 4 5 6 7 8 9
VSS

PWR_UP

nRF905
32L QFN 5x5

23 22 21 20 19 18 17

IREF

uPCLK

VSS

VDD

ANT2

VSS

ANT1

CD

VDD_PA

AM

VSS

DR

VDD

10
MISO

11
MOSI

12
SCK

13
CSN

14
XC1

15
XC2

16
VSS

Figure 2. nRF905 pin assignment (top view) for a 32L QFN 5x5 package

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nRF905 Product Specification 7.2

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Pin Functions
Name TRX_CE PWR_UP uPCLK VDD VSS CD AM DR VSS MISO MOSI SCK CSN XC1 XC2 VSS VDD VSS VDD_PA ANT1 ANT2 VSS IREF VSS VDD VSS VSS VSS VSS VSS DVDD_1V2 TX_EN Pin function Digital input Digital input Clock output Power Power Digital output Digital output Digital output Power SPI - interface SPI - interface SPI - Clock SPI - enable Analog Input Analog Output Power Power Power Power output RF RF Power Analog Input Power Power Power Power Power Power Power Power Digital input Description Enables chip for receive and transmit Power up chip Output clock, divided crystal oscillator full swing clock Power supply (+3V DC) Ground (0V) Carrier Detect Address Match Receive and transmit Data Ready Ground (0V) SPI output SPI input SPI clock SPI enable, active low Crystal pin 1/ External clock reference pin Crystal pin 2 Ground (0V) Power supply (+3V DC) Ground Positive supply (1.8V) to nRF905 power amplifier Antenna interface 1 Antenna interface 2 Ground (0V) Reference current Ground (0V) Power supply (+3V DC) Ground (0V) Ground (0V) Ground (0V) Ground (0V) Ground (0V) Low voltage positive digital supply output for decoupling TX_EN=1TX mode, TX_EN=0RX mode

Table 10. nRF905 pin function.

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nRF905 Product Specification 8 Modes of Operation

The nRF905 has two active (RX/TX) modes and two power saving modes:

8.1

Active Modes
ShockBurst RX ShockBurst TX

8.2

Power Saving Modes

Power down and SPI programming Standby and SPI programming

The nRF905 mode is decided by the settings of TRX_CE, TX_EN and PWR_UP. PWR_UP 0 1 1 1 1 TRX_CE X 0 X 1 1 TX_EN X X 0 0 1 Operating Mode Power down and SPI programming Standby and SPI programming Read data from RX register Radio Enabled - ShockBurst RX Radio Enabled - ShockBurst TX

Table 11. nRF905 operational modes.

8.3

nRF ShockBurst Mode

The nRF905 uses the ShockBurst feature. ShockBurst makes it possible to use the high data rate offered by the nRF905 without the need of a costly, high-speed microcontroller (MCU) for data processing/ clock recovery. By placing all high speed signal processing related to RF protocol on-chip, the nRF905 offers the application microcontroller a simple SPI, the data rate is decided by the interface speed the microcontroller sets up. By allowing the digital part of the application to run at low speed, while maximizing the data rate on the RF link, the nRF905 ShockBurst mode reduces the average current consumption in applications. In ShockBurst RX, Address Match (AM) and Data Ready (DR) notifies the MCU when a valid address and payload is received respectively. In ShockBurst TX, the nRF905 automatically generates preamble and CRC. Data Ready (DR) notifies the MCU that the transmission is completed. This means reduced memory demand in the MCU resulting in a low cost MCU, as well as reduced software development time.

8.4
1. 2. 3.

Typical ShockBurst TX
When the application MCU has data for a remote node, the address of the receiving node (TXaddress) and payload data (TX-payload) are clocked into nRF905 through the SPI. The application protocol or MCU sets the speed of the interface. MCU sets TRX_CE and TX_EN high, this activates a nRF905 ShockBurst transmission. nRF905 ShockBurst does the following: Radio is automatically powered up. Data packet is completed (preamble added, CRC calculated). Data packet is transmitted (50kbps). Data Ready is set high when transmission is completed.

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nRF905 Product Specification

4. 5. If AUTO_RETRAN is set high, the nRF905 continuously retransmits the packet until TRX_CE is set low. When TRX_CE is set low, the nRF905 finishes transmitting the outgoing packet and then sets itself into standby mode.

If TX_EN is set low while TRX_CE is kept high, the nRF905 finishes transmitting the outgoing packet and enters RX mode in the channel already programmed in the RF-CONFIG register. The ShockBurst mode ensures that a transmitted packet that has started always finishes regardless of what TRX_EN and TX_EN are set to during transmission. The new mode is activated when the transmission is completed. For test purposes such as antenna tuning and measuring output power it is possible to set the transmitter so that a constant carrier is produced. To do this, TRX_CE must be maintained high instead of being pulsed and Auto Retransmit should be switched off. After the burst of data is sent the device continues to send the unmodulated carrier.

Radio in Standby TX_EN = HI PWR_UP = HI TRX_CE = LO

Data Packet

SPI - programming uController loading ADDR and PAYLOAD data (Configuration register if changes since last TX/RX) ADDR PAYLOAD

TRX_CE = HI ?

NO

YES Transmitter is powered up

nRF ShockBurst TX Generate CRC and preamble Sending packet DR is set high when completed

DR is set low after preamble

Preamble

ADDR

PAYLOAD

CRC

NO TRX_CE = HI ? AUTO_ RETRAN = HI ? YES Bit in configuration register

NO

YES

Figure 3. Flowchart ShockBurst transmit of nRF905. Note: When DR is set high it can be set low again under the following conditions: If TX_EN is set low If PWR_UP is set low

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nRF905 Product Specification 8.5

1. 2. 3. 4. 5. 6. 7. 8. 9.

Typical ShockBurst RX
ShockBurst RX is selected by setting TRX_CE high and TX_EN low. After 650s nRF905 is monitoring the air for incoming communication. When the nRF905 senses a carrier at the receiving frequency, Carrier Detect (CD) pin is set high. When a valid address is received, Address Match (AM) pin is set high. When a valid packet has been received (correct CRC found), nRF905 removes the preamble, address and CRC bits, and the Data Ready (DR) pin is set high. MCU sets the TRX_CE low to enter standby mode (low current mode). MCU can clock out the payload data at a suitable rate through the SPI. When all payload data is retrieved, nRF905 sets Data Ready (DR) and Address Match (AM) low again. The chip is now ready for entering ShockBurst RX, ShockBurst TX or, power down mode.

If TX_EN is set high while TRX_CE is kept high, the nRF905 would enter ShockBurst TX and start a transmission according to the present contents in the SPI registers. If TRX_CE or TX_EN is changed during an incoming packet, the nRF905 changes mode immediately and the packet is lost. However, if the MCU is sensing the Address Match (AM) pin, it knows when the chip is receiving an incoming packet and can therefore decide whether to wait for the Data Ready (DR) signal or enter a different mode. To avoid spurious address matches it is recommended that the address length be 24 bits or higher in length. Small addresses such as 8 or 16 bits can often lead to statistical failures due to the address being repeated as part of the data packet. This can be avoided by using a longer address. Each byte within the address should be unique. Repeating bytes within the address reduces the effectiveness of the address and increases its susceptibility to noise which increases the packet error rate. The address should also have several level shifts (that is, 10101100) reducing the statistical effect of noise and the packet error rate.

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nRF905 Product Specification

Radio in Standby TX_EN = LO PWR_UP = HI

TRX_CE = HI ? YES Receiver is powered up

NO

Receiver Sensing for incomming data CD is set high if carrier

Data Packet
NO Correct ADDR? YES AM is set high Preamble

ADDR

PAYLOAD

CRC

Receiving data

AM is set low

NO

Correct CRC? YES DR high is set high DR and AM are set low DR and AM are set low

MCU clocks out payload via the SPI interface

MCU clocks out payload via the SPI interface

PAYLOAD

TRX_CE = HI ?

NO

Radio enters STBY

RX Remains On

YES

Figure 4. Flowchart ShockBurst receive of nRF905.

8.6

Power Down Mode

In power down the nRF905 is disabled with minimal current consumption, typically less than 2.5A. When the device enters this mode it is not active which minimizes average current consumption and maximizes battery lifetime. The configuration word content is maintained during power down.

8.7

Standby Mode

Standby mode is used to minimize average current consumption while maintaining short start up times to ShockBurst RX and ShockBurst TX. In this mode part of the crystal oscillator is active. Current consumption is dependent on crystal frequency, Ex: IDD= 12A @4MHz and IDD =46A @20MHz. If the uPclock (pin 3) of nRF905 is enabled, current consumption increases and is dependent on the load capacitance and frequency. The configuration word content is maintained during standby.

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nRF905 Product Specification 9 Device Configuration

All configuration of the nRF905 is through the SPI. The interface consists of five registers. A SPI instruction set is used to decide which operation shall be performed. The SPI can be activated in any mode however, we recommend that the chip is in standby or power down mode.

9.1

SPI Register Configuration

The SPI consists of five internal registers. A register readback mode is implemented to allow verification of the register contents.

MISO MOSI SCK CSN I/O-reg EN DTA CLK STATUS-REGISTER

EN DTA CLK

RF - CONFIGURATION REGISTER

EN DTA CLK TX-ADDRESS

EN DTA CLK TX-PAYLOAD

EN DTA CLK RX-PAYLOAD

Figure 5. SPI interface and the five internal registers. Internal registers Description Status Register Register contains status of Data Ready (DR), Address Match (AM). RF Configuration Register Register contains transceiver setup information such as frequency and output power ext. TX Address Register contains address of target device. How many bytes used is set in the configuration register. TX Payload Register containing the payload information to be sent in a ShockBurst packet. How many bytes used is set in the configuration register. RX Payload Register containing the payload information derived from a received valid ShockBurst packet. How many bytes used is set in the configuration register. Valid data in the RX-Payload register is indicated with a high Date Ready (DR) signal. Table 12. Internal registers description

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nRF905 Product Specification 9.2 SPI Instruction Set

The available commands used on the SPI are shown below. Whenever CSN is set low the interface expects an instruction. Every new instruction must be started by a high to low transition on CSN. Instruction set for the nRF905 SPI Instruction Operation Format 0000 AAAA Write Configuration register. AAAA indicates which byte the write operation is to be started from. Number of bytes depends on start address AAAA. 0001 AAAA Read Configuration register. AAAA indicates which byte the read operation is to be started from. Number of bytes depends on start address AAAA. 0010 0000 Write TX-payload: 1 32 bytes. A write operation always starts at byte 0. 0010 0001 Read TX-payload: 1 32 bytes. A read operation always starts at byte 0. Write TX-address: 1 4 bytes. A write operation always starts at byte 0. Read TX-address: 1 4 bytes. A read operation always starst at byte 0 Read RX-payload: 1 32 bytes. A read operation always starts at byte 0. Special command for fast setting of CH_NO, HFREQ_PLL and PA_PWR in the CONFIGURATION REGISTER. CH_NO= ccccccccc, HFREQ_PLL = h PA_PWR = pp The content of the status register (S[7:0]) is always read to MISO after a high to low transition on CSN as shown in Figure 6. and Figure 7.

Instruction Name W_CONFIG (WC) R_CONFIG (RC) W_TX_PAYLO AD (WTP) R_TX_PAYLO AD (RTP) W_TX_ADDRE SS (WTA) R_TX_ADDRE SS (RTA) R_RX_PAYLO AD (RRP) CHANNEL_CO NFIG (CC) STATUS REGISTER

0010 0010

0010 0011

0010 0100

1000 pphc cccc cccc N.A.

Table 13. Instruction set for the nRF905 SPI. A read or a write operation may operate on a single byte or on a set of succeeding bytes from a given start address defined by the instruction. When accessing succeeding bytes, you read or write the MSB of the byte with the smallest byte number first.

9.3

SPI Timing

The interface supports SPI mode 0. SPI operation and timing is given in Figure 6. to Figure 8. and in Table 14.. The device must be in one of the power saving modes for you to read or write to the configuration registers.

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nRF905 Product Specification

CSN SCK MOSI MISO

C7 C6 C5 C4 C3 C2 C1 C0

S7

S6

S5

S4

S3

S2

S1

S0

D7

D6

D5

D4

D3

D2

D1

D0

D1 5

D1 4

D1 3

D1 2

D1 1

D1 0

D9

D8

Figure 6. SPI read operation.

CSN SCK MOSI MISO
C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8

S7

S6

S5

S4

S3

S2

S1

S0

Figure 7. SPI write operation.

Tcwh
CSN

Tcc
SCK

Tch Tdh

Tcl

Tcch

Tdc
MOSI
C7 C6 C0

Tcsd
MISO
S7

Tcd
S0

Tcdz

Figure 8. SPI NOP timing diagram. PARAMETER Data to SCK Setup SCK to Data Hold CSN to Data Valid SCK to Data Valid SCK Low Time SCK High Time SCK Frequency SCK Rise and Fall CSN to SCK Setup SCK to CSN Hold CSN Inactive time CSN to Output High Z SYMBOL Tdc Tdh Tcsd Tcd Tcl Tch Tsck Tr,Tf Tcc Tcch Tcwh Tcdz MIN 5 5 40 40 DC 5 5 500 45 MAX UNITS ns ns ns ns ns ns MHz ns ns ns ns ns

45 45 10 100

Table 14. SPI timing parameters (Cload = 10pF)

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nRF905 Product Specification 9.4 RF Configuration Register Description

Parameter CH_NO Bitwidth 9 Description Sets center frequency together with HFREQ_PLL (default = 001101100b = 108d). fRF = ( 422.4 + CH_NOd /10)*(1+HFREQ_PLLd) MHz Sets PLL in 433 or 868/915MHz mode (default = 0). '0' Chip operating in 433MHz band '1' Chip operating in 868 or 915 MHz band Output power (default = 00). '00' -10dBm '01' -2dBm '10' +6dBm '11' +10dBm Reduces current in RX mode by 1.6mA. Sensitivity is reduced (default = 0). '0' Normal operation '1' Reduced power Retransmit contents in TX register if TRX_CE and TXEN are high (default = 0). '0' No retransmission '1' Retransmission of data packet RX-address width (default = 100). '001' 1 byte RX address field width '100' 4 byte RX address field width TX-address width (default = 100). '001' 1 byte TX address field width '100' 4 byte TX address field width RX-payload width (default = 100000). '000001' 1 byte RX payload field width '000010' 2 byte RX payload field width . '100000' 32 byte RX payload field width TX-payload width (default = 100000). '000001' 1 byte TX payload field width '000010' 2 byte TX payload field width . '100000' 32 byte TX payload field width RX address identity. Used bytes depend on RX_AFW (default = E7E7E7E7h). Output clock frequency (default = 11). '00' 4MHz '01' 2MHz '10' 1MHz '11' 500kHz Output clock enable (default = 1). '0' No external clock signal available '1' External clock signal enabled

HFREQ_ PLL PA_PWR

RX_RED_ PWR

AUTO_ RETRAN

RX_AFW

TX_AFW

RX_PW

TX_PW

RX_ ADDRESS UP_CLK_ FREQ

32 2

UP_CLK_ EN

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nRF905 Product Specification

Parameter XOF Bitwidth 3 Description Crystal oscillator frequency. Must be set according to external crystal resonant frequency (default = 100). '000' 4MHz '001' 8MHz '010' 12MHz '011' 16MHz '100' 20MHz CRC check enable (default = 1). '0' Disable '1' Enable CRC mode (default = 1). '0' 8 CRC check bit '1' 16 CRC check bit Table 15. Configuration register description

CRC_EN

CRC_ MODE

9.5

Register Contents

Byte # 0 1 2 3 4 5 6 7 8 9

RF-CONFIG_REGISTER (R/W) Content bit[7:0], MSB = bit[7] CH_NO[7:0] bit[7:6] not used, AUTO_RETRAN, RX_RED_PWR, PA_PWR[1:0], HFREQ_PLL, CH_NO[8] bit[7] not used, TX_AFW[2:0] , bit[3] not used, RX_AFW[2:0] bit[7:6] not used, RX_PW[5:0] bit[7:6] not used, TX_PW[5:0] RX_ADDRESS (device identity) byte 0 RX_ADDRESS (device identity) byte 1 RX_ADDRESS (device identity) byte 2 RX_ADDRESS (device identity) byte 3 CRC_MODE,CRC_EN, XOF[2:0], UP_CLK_EN, UP_CLK_FREQ[1:0] Table 16. RF config register TX_PAYLOAD (R/W) Content bit[7:0], MSB = bit[7] TX_PAYLOAD[7:0] TX_PAYLOAD[15:8] TX_PAYLOAD[247:240] TX_PAYLOAD[255:248] Table 17. TX payload register

Init value 0110_1100 0000_0000 0100_0100 0010_0000 0010_0000 E7 E7 E7 E7 1110_0111

Byte # 0 1 30 31

Init value X X X X X X

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nRF905 Product Specification

Byte # 0 1 2 3

TX_ADDRESS (R/W) Content bit[7:0], MSB = bit[7] TX_ADDRESS[7:0] TX_ADDRESS[15:8] TX_ADDRESS[23:16] TX_ADDRESS[31:24] Table 18.TX address register RX_PAYLOAD (R) Content bit[7:0], MSB = bit[7] RX_PAYLOAD[7:0] RX_PAYLOAD[15:8] RX_PAYLOAD[247:240] RX_PAYLOAD[255:248] Table 19. RX payload register STATUS_REGISTER (R) Content bit[7:0], MSB = bit[7] AM, bit [6] not used, DR, bit [0:4] not used Table 20. Status register

Init value E7 E7 E7 E7

Byte # 0 1 30 31

Init value X X X X X X

Byte # 0

Init value X

The length of all registers is fixed. However, the bytes in TX_PAYLOAD, RX_PAYLOAD, TX_ADDRESS and RX_ADDRESS used in ShockBurst RX/TX are set in the configuration register. Register content is not lost when the device enters one of the power saving modes.

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nRF905 Product Specification 10 Important Timing Data

The following timing must be obeyed during nRF905 operation.

10.1

Device Switching Times

nRF905 timing PWR_DWN ST_BY mode STBY TX ShockBurst STBY RX ShockBurst RX ShockBurst TX ShockBurst TX ShockBurst RX ShockBurst Max. 3 ms 650 s 650 s 550 sa 550 s

a. RX to TX or TX to RX switching is available without re-programming the RF configuration register. The same frequency channel is maintained.

Table 21. Switching times for nRF905.

10.2
MOSI

ShockBurst TX timing

CSN

PWR_UP

TX_EN

TRX_CE TX DATA

TIME Programming of Configuration Register and TX Data Register T0 T1 T2 Transmitted Data 100kbps Manchester Encoded T3

T0 T1 T2 T3

= = = =

Radio Enabled T0+10uS Minimum TRX_CE pulse T0 + 650uS.Start of TX Data transmission End of Data Packet, enter Standby mode

Figure 9. Timing diagram for standby to transmit After a data packet has finished transmitting, the device automatically enters Standby mode and waits for the next pulse of TRX_CE. If the auto retransmit function is enabled the data packet continues resending the same data packet until TRX_CE is set low.

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nRF905 Product Specification 10.3 ShockBurst RX timing

PWR_UP

TX_EN

TRX_CE

RX DATA

CD

AM

DR

TIME

650uS 650uS to enter RX mode from TRX_CE being set high. T0 T0 T1 T2 T3 = = = = T1 T2 T3

Receiver Enabled -Listening for Data Carrier Detect finds a carrier AM - Correct Address Found DR - Data packet with correct Address/CRC

Figure 10. Timing diagram for standby to receiving After the Data Ready (DR) has been set high a valid data packet is available in the RX data register. This may be clocked out in RX mode or standby mode. After the data has been clocked out through the SPI the Data Ready (DR) and Address Match (AM) pins are reset to low. The RX register is reset if the PWR_UP pin is taken low or if the device is switched into TX mode, that is, TXEN is taken high. This also results in the Data Ready (DR) and Address Match (AM) pins being reset to low.

10.4

Preamble

In each data packet transmitted by the nRF905 a preamble is added automatically. The preamble is a predefined bit sequence used to adjust the receiver for optimal performance. A ten bit sequence is used as preamble in nRF905. The length of the preamble, tpreamble, is then 200s.

10.5

Time On Air

The time on air is the sum of the radio start up time and the data packet length. The length of the preamble, address field, payload and CRC checksum give the data packet length while the radio start up time is given in Table 11. While preamble length and start up time are fixed the user sets the other parameters in the RF configuration register. The below equation shows how to calculate TOA:

TOA = t startup + t preamble +

N address + N payload + N CRC BR

tstartup and tpreamble are RF start up time and preamble time respectively. Naddress, Npayload and NCRC are numbers of bits in the address, payload and CRC checksum while BR is the bitrate, which is equal to 50kbps.

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nRF905 Product Specification 11 11.1 Peripheral RF Information Crystal Specification

Tolerance includes initial accuracy and tolerance over temperature and aging. Frequency 4MHz 8MHz 12MHz 16MHz 20MHz CL 8pF 16pF 8pF 16pF 8pF 16pF 8pF 16pF 8pF 16pF ESR 150 100 100 100 100 C0max 7.0pF 7.0pF 7.0pF 7.0pF 7.0pF Tolerance @ 868/915 MHz 30ppm 30ppm 30ppm 30ppm 30ppm Tolerance @ 433 MHz 60ppm 60ppm 60ppm 60ppm 60ppm

Table 22. Crystal specification of nRF905 To achieve a crystal oscillator solution with low power consumption and fast start up time, it is recommended to specify the crystal with a low value of crystal load capacitance. Specifying a lower value of crystal parallel equivalent capacitance, Co=1.5pF is also good, but this can increase the price of the crystal itself. Typically Co=1.5pF at a crystal specified for Co_max=7.0pF. The crystal load capacitance, CL, is given by:

CL =

C1 'C 2 ' , C1 '+C 2 '

where C1 ' = C1 + C PCB1 + C I 1 and C 2 ' = C 2 + C PCB 2 + C I 2

C1 and C2 are 0603 SMD capacitors as shown in the application schematics. CPCB1 and CPCB2 are the layout parasitic on the circuit board. CI1 and CI2 are the capacitance seen into the XC1 and XC2 pin respectively; the value is typical 1pF.

11.2

External Clock Reference

An external reference clock, such as an MCU clock, may be used instead of a crystal. The clock signal should be applied directly to the XC1 pin, the XC2 pin can be left high impedance. When operating with an external clock instead of a crystal the clock must be applied in standby mode to achieve low current consumption. If the device is set into standby mode with no external clock or crystal then the current consumption increases up to a maximum of 1mA.

11.3

Microprocessor Output Clock

By default a microprocessor clock output is provided. Providing an output clock increases the current consumption in standby mode. The current consumption in standby depends on frequency and load of external crystal, frequency of output clock and capacitive load of the provided output clock. Typical current consumption values are found in Table 9. on page 13.

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nRF905 Product Specification 11.4 Antenna Output

The ANT1 and ANT2 output pins provide a balanced RF output to the antenna. The pins must have a DC path to VDD_PA, either through a RF choke or through the center point in a dipole antenna. The load impedance seen between the ANT1/ANT2 outputs should be in the range 200-700W. The optimum differential load impedance at the antenna ports is given as: 900MHz225+j210 430MHz300+j100 A low load impedance (for instance 50) can be obtained by fitting a simple matching network or a RF transformer (balun). Further information regarding balun structures and matching networks may be found in chapter 15 on page 35.

11.5

Output Power Adjustment

The power amplifier in nRF905 can be programmed to four different output power settings by the configuration register. By reducing output power, the total TX current is reduced. DC current consumption 00 -10 dBm 9.0 mA 01 -2 dBm 14.0 mA 10 6 dBm 20.0 mA 11 10 dBm 30.0 mA Conditions: VDD = 3.0V, VSS = 0V, TA = 27C, Load impedance = 400 . Power setting RF output power Table 23. RF output power setting for the nRF905

11.6

Modulation

The modulation of nRF905 is Gaussian Frequency Shift Keying (GFSK) with a data rate of 100kbps. Deviation is 50kHz. GFSK modulation results in a more bandwidth effective transmission link compared with ordinary FSK modulation. The data is internally Manchester encoded (TX) and Manchester decoded (RX). That is, the effective symbol rate of the link is 50kbps. By using internally Manchester encoding, no scrambling in the microcontroller is needed.

11.7

Output Frequency

The operating RF frequency of nRF905 is set in the configuration register by CH_NO and HFREQ_PLL. The operating frequency is given by:

f OP = (422.4 + (CH _ NO / 10)) (1 + HFREQ _ PLL) MHz

When HFREQ_PLL is 0 the frequency resolution is 100kHz and when it is 1 the resolution is 200kHz.

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nRF905 Product Specification

The application operating frequency must be chosen to apply with the Short Range Device regulation in the area of operation. Operating frequency 430.0 MHz 433.1 MHz 433.2 MHz 434.7 MHz 862.0 MHz 868.2 MHz 868.4 MHz 869.8 MHz 902.2 MHz 902.4 MHz 927.8 MHz HFREQ_PLL [0] [0] [0] [0] [1] [1] [1] [1] [1] [1] [1] CH_NO [001001100] [001101011] [001101100] [001111011] [001010110] [001110101] [001110110] [001111101] [100011111] [100100000] [110011111]

Table 24. Examples of real operating frequencies

11.8

PCB Layout and Decoupling Guidelines

nRF905 is an extremely robust RF device due to internal voltage regulators and requires the minimum of RF layout protocols. However, the following design rules should still be incorporated into the layout design. A PCB with a minimum of two layers including a ground plane is recommended for optimum performance. The DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF capacitors. It is preferable to mount a large surface mount capacitor (for example, 4.7F tantalum) in parallel with the smaller value capacitors. The supply voltage should be filtered and routed separately from the supply voltages of any digital circuitry. Long power supply lines on the PCB should be avoided. All device grounds, VDD connections and VDD bypass capacitors must be connected as close as possible to the IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to place via holes as close as possible to the VSS pins. A minimum of one via hole should be used for each VSS pin. Full swing digital data or control signals should not be routed close to the crystal or the power supply lines. A fully qualified RF layout for the nRF905 and its surrounding components, including antennas and matching networks, can be downloaded from www.nordicsemi.no.

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nRF905 Product Specification 12 12.1 nRF905 features Carrier Detect

When the nRF905 is in ShockBurst RX, the Carrier Detect (CD) pin is set high if a RF carrier is present at the channel the device is programmed to. This feature is very effective to avoid collision of packets from different transmitters operating at the same frequency. Whenever a device is ready to transmit it could first be set into receive mode and sense whether or not the wanted channel is available for outgoing data. This forms a very simple listen before transmit protocol. Operating Carrier Detect (CD) with Reduced RX Power mode is an extremely power efficient RF system. Typical Carrier Detect level (CD) is typically 5dB lower than sensitivity, that is, if sensitivity is 100dBm then the Carrier Detect function senses a carrier wave as low as 105dBm. Below 105dBm the Carrier Detect signal is low, that is, 0V. Above 95dBm the Carrier Detect signal is high, that is, Vdd. Between approximately -95 to -105 the Carrier Detect Signal toggles.

12.2

Address Match

When the nRF905 is in ShockBurst RX mode, the Address Match (AM) pin is set high as soon as an incoming packet with an address that is identical with the devices own identity is received. With the Address Match pin the controller is alerted that the nRF905 is receiving data actually before the Data Ready (DR) signal is set high. If the Data Ready (DR) pin is not set high, that is, the CRC is incorrect then the Address Match (AM) pin is reset to low at the end of the received data packet. This function can be very useful for an MCU. If Address Match (AM) is high then the MCU can make a decision to wait and see if Data Ready (DR) is set high indicating a valid data packet has been received or ignore that a possible packet is being received and switch modes.

12.3

Data Ready

The Data Ready (DR) signal makes it possible to largely reduce the complexity of the MCU software program. In ShockBurst TX, the Data Ready (DR) signal is set high when a complete packet is transmitted, telling the MCU that the nRF905 is ready for new actions. It is reset to low at the start of a new packet transmission or when switched to a different mode, that is, receive mode or standby mode. In ShockBurst TX Auto Retransmit the Data Ready (DR) signal is set high at the beginning of the preamble and is set low at the end of the preamble. The Data Ready (DR) signal therefore pulses at the beginning of each transmitted data packet. In ShockBurst RX, the signal is set high when nRF905 has received a valid packet, that is, a valid address, packet length and correct CRC. The MCU can then retrieve the payload through the SPI. The Data Ready (DR) pin is reset to low once the data has been clocked out of the data buffer or the device is switched to transmit mode.

12.4

Auto Retransmit

One way to increase system reliability in a noisy environment or in a system without collision control is to transmit a packet several times. This is easily accomplished with the Auto Retransmit feature in nRF905. By setting the AUTO_RETRAN bit to 1 in the configuration register, the circuit keeps sending the same data packet as long as TRX_CE and TX_EN is high. As soon as TRX_CE is set low the device finishes sending the packet it is currently transmitting and then returns to standby mode.

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nRF905 Product Specification 12.5 RX Reduced Power Mode

To maximize battery lifetime in application where the nRF905 high sensitivity is not necessary; nRF905 offers a built in reduced power mode. In this mode, the receive current consumption reduces from 12.5mA to only 10.5mA. The sensitivity is reduced to typical 85dBm, 10dB. Some degradation of the nRF905 blocking performance should be expected in this mode. The reduced power mode is an excellent option when using Carrier Detect to sense if the wanted channel is available for outgoing data.

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nRF905 Product Specification 13 Mechanical specifications

nRF905 uses the QFN 32L 5x5 green package with a mat tin finish. Dimensions are in mm. Recommended soldering reflow profile can be found in application note nAN400-08, QFN soldering reflow guidelines, www.nordicsemi.no.

Package

A1

A3

N ND NE 8 8

0 12

QFN32 Min. 0.8 0.0 0.18 3.2 0.2 0.35 (5x5 mm) Typ. 0.85 0.02 0.2 0.23 5 BSC 5 BSC 0.5 BSC 3.3 0.4 32 Max. 0.9 0.05 0.3 3.4 0.45 Figure 11. nRF905 package outline

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nRF905 Product Specification 14 14.1 Ordering information Package marking

n 9 Y R F B 0 5 Y W W L X L

14.1.1

Abbreviations
Definition Product number Build Code, that is, unique code for production sites, package type and, test platform. "X" grade, that is, Engineering Samples (optional). Two digit Year number Two digit week number Two letter wafer lot number code Table 25. Abbreviations

Abbreviation 905 B X YY WW LL

14.2
14.2.1
nRF905

Product options
RF silicon
Ordering code Package 5x5mm 32-pin QFN, lead free (green) 5x5mm 32-pin QFN, lead free (green) Container Tray 13 reel MOQa 490 2500

nRF905-REEL
a. Minimum Order Quantity

Table 26. nRF905 RF silicon options

14.2.2

Development tools
Description nRF905 Development kit 433MHz nRF905 Development kit 868/915MHz Table 27. nRF905 solution options Version 1.0 1.0

Type Number nRF905-EVKIT 433 nRF905-EVKIT 868/915

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nRF905 Product Specification 15 15.1 Application Examples Differential Connection to a Loop Antenna
aaaaaaaa VDD C5 33pF 0603 C6 4.7nF 0603 C7 10nF 0603

32 31 30 29 28 27 26 25

TXEN DVDD_1V2 VSS VSS VSS VSS VSS VDD

TXEN TRX_C E PWR_UP uPCLK aaaaaaaa CD AM DR SPI_MISO SPI_MOSI SPI_SC K SPI_C SN

R2 22K C12 0603 27pF 24 23 22 21 20 19 18 17

J1 Loop Antenna, 433MHz 35x20mm C9 3.9pF aaaaaaaa

VDD

1 2 3 4 5 6 7 8

TRX_C E PWR_UP uPCLK VDD VSS CD AM DR

nRF 905

VSS IR EF VSS ANT2 ANT1 VDD_PA VSS VDD

C10 6.8pF VDD C13 27pF C3 180pF C11 4.7pF

C8 33pF 0603 C4 3.3nF 0603

9 10 11 12 13 14 15 16 X1 16 MHz R1 1M C1 22pF 0603 aaaaaaaa C2 22pF 0603

U1 nRF905

Figure 12. nRF905 Application schematic, differential connection to a loop antenna (433MHz) Component C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 R1 R2 U1 X1 Description Size Value Tol. Units NP0 ceramic chip capacitor, (Crystal oscillator) 0603 22 5% pF NP0 ceramic chip capacitor, (Crystal oscillator) 0603 22 5% pF NP0 ceramic chip capacitor, (PA supply decoupling) 0603 180 5% pF X7R ceramic chip capacitor, (PA supply decoupling) 0603 3.3 10% nF NP0 ceramic chip capacitor, (Supply decoupling) 0603 33 5% pF X7R ceramic chip capacitor, (Supply decoupling) 0603 4.7 10% nF X7R ceramic chip capacitor, (Supply decoupling) 0603 10 10% nF NP0 ceramic chip capacitor, (Supply decoupling) 0603 33 5% pF NP0 ceramic chip capacitor, (Antenna tuning) 0603 3.9 0.1 pF NP0 ceramic chip capacitor, (Antenna tuning) 0603 6.8 0.1 pF 0603 4.7 0.1 pF NP0 ceramic chip capacitor, (Antenna tuning) NP0 ceramic chip capacitor, (Antenna tuning) 0603 27 5% pF NP0 ceramic chip capacitor, (Antenna tuning) 0603 27 5% pF 0.1W chip resistor, (Crystal oscillator bias) 0603 1 5% M 0.1W chip resistor, (Reference bias) 0603 22 1% k nRF905 Transceiver QFN32L/5x5 Crystal, CL = 12pF LxWxH = 16 60ppm MHz 4.0x2.5x0.8

Table 28. Recommended external components, differential connection to a loop antenna (433MHz)

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VSS MISO MOSI SCK CSN XC1 XC2 VSS

nRF905 Product Specification 15.2 PCB Layout Example; Differential Connection to a Loop Antenna

Figure 13. shows a PCB layout example for the application schematic in Figure 12. A double sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. A large number of via holes connect the top layer ground areas to the bottom layer ground plane. There is no ground plane beneath the antenna.

No components in bottom layer

a) Top silk screen b) Bottom silk screen

c) Top view

d) Bottom view

Figure 13. PCB layout example for nRF905, differential connection to a loop antenna A fully qualified RF layout for the nRF905 and its surrounding components, including antennas and matching networks, can be downloaded from www.nordicsemi.no.

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nRF905 Product Specification 15.3 Single ended connection to 50 antenna

C12 33pF, 5%
VDD C7 10nF C5 33pF C6 4.7nF

6.8pF, 5% Optional 12nH, 5% 39nH, 5% 39nH, 5%

C13 Optional L1 L2 L3 12nH, 5% 12nH, 5% 12nH, 5%

32 31 30 29 28 27 26 25

TXEN DVDD_1V2 VSS VSS VSS VSS VSS VDD

R2 22K 24 23 22 21 20 19 18 17

C9 L2 C12

C13 Optional aaaaaaaa 50 ohm RF I/O

TXEN TRX_CE PWR_UP uPCLK CD AM DR SPI_MISO SPI_MOSI SPI_SCK SPI_C SN VDD aaaaaaaa

1 2 3 4 5 6 7 8

TRX_C E PWR_UP uPCLK VDD VSS CD AM DR

nRF 905

VSS IREF VSS ANT2 ANT1 VDD_PA VSS VDD

C11 Optional VDD

L1

L3

C3

VSS MISO MOSI SCK CSN XC1 XC2 VSS

C10

C8 33pF

9 10 11 12 13 14 15 16

U1 nRF905

C4 3.3nF X1

R1

16 MHz

1M C1 22pF aaaaaaaa C2 22pF

Figure 14. 433 MHz operating nRF905 application schematic, single ended connection to 50 antenna by using a differential to single ended matching network

Figure 15. 868-915 MHz operating nRF905 application schematic, single ended connection to 50 antenna by using a differntial to single ended matching network

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nRF905 Product Specification

Component Description C1 NP0 ceramic chip capacitor, (Crystal oscillator) C2 NP0 ceramic chip capacitor, (Crystal oscillator) C3 NP0 ceramic chip capacitor, (PA supply decoupling) @ 433MHz @ 868MHz @ 915MHz C4 X7R ceramic chip capacitor, (PA supply decoupling) C5 NP0 ceramic chip capacitor, (Supply decoupling) C6 X7R ceramic chip capacitor, (Supply decoupling) C7 X7R ceramic chip capacitor, (Supply decoupling) C8 NP0 ceramic chip capacitor, (Supply decoupling) C9 NP0 ceramic chip capacitor, (Impedance matching) @ 433MHz @ 868MHz @ 915MHz C10 NP0 ceramic chip capacitor, (Impedance matching) @ 433MHz @ 868MHz @ 915MHz NP0 ceramic chip capacitor, (Impedance matching) NP0 ceramic chip capacitor, (Impedance matching) @ 433MHz @ 868MHz @ 915MHz NP0 ceramic chip capacitor, (Impedance matching) @ 433MHz @ 868MHz @ 915MHz Chip inductor, (Impedance matching) @ 433MHz: SRF> 433MHz @ 868MHz: SRF> 868MHz @ 915MHz: SRF> 915MHz Chip inductor, (Impedance matching) @ 433MHz: SRF> 433MHz @ 868MHz: SRF> 868MHz @ 915MHz: SRF> 915MHz Size 0603 0603 0603 180 33 33 3.3 33 4.7 10 33 Value 22 22 Tol. 5% Units pF pF pF

5% 5%

0603 0603 0603 0603 0603 0603

10% 5% 10% 10% 5%

nF pF nF nF pF pF

18 5.6 5.6 0603

5% <0.25pF <0.25pF
pF

C11 C12

0603 0603

18 5.6 5.6 Not fitted

5% <0.25pF <0.25pF
pF pF

6.8 22 22 0603 Not fitted 4.7 4.7 0603 12 12 12 0603 39 10 10

5% 5% 5%

C13

pF

L1

5%

nH

L2

5% 5% 5%

nH

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nRF905 Product Specification

Component Description L3 Chip inductor, (Impedance matching) @ 433MHz: SRF> 433MHz @ 868MHz: SRF> 868MHz @ 915MHz: SRF> 915MHz R1 0.1W chip resistor, (Crystal oscillator bias) R2 0.1W chip resistor, (Reference bias) U1 nRF905 Transceiver X1 Crystal, CL = 12pF @ 433MHz @ 868MHz @ 915MHz Size 0603 Value 39 12 12 1 22 16 Tol. Units nH

0603 0603 QFN32L/5x5 LxWxH = 4.0x2.5x0.8

5% 5% 5% 5% 1%

M k MHz

60ppm 30ppm 30ppm

Table 29. Recommended external components, single ended connection to 50 antenna

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nRF905 Product Specification 15.4 PCB Layout Example; Single Ended Connection to 50 Antenna

Figure 16. shows a PCB layout example for the application schematic in Figure 14. and Figure 17. shows a PCB layout example for the application schematic in Figure 15. A double sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. A large number of via holes connect the top layer ground areas to the bottom layer ground plane.

No components in bottom layer

a) Top silk screen

b) Bottom silk screen

c) Top view

d) Bottom view

Figure 16. PCB layout example for 433 MHz operation on nRF905, single ended connection to 50 antenna by using a differential to single ended matching network

No components in bottom layer b) Bottom silk screen a) Top silk screen

c) Top view

d) Bottom view

Figure 17. PCB layout example for 868-915 MHz operation on nRF905, single ended connection to 50 antenna by using a differential to single ended matching network A fully qualified RF layout for the nRF905 and its surrounding components, including antennas and matching networks, can be downloaded from www.nordicsemi.no

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nRF905 Product Specification 16 Glossary of terms

Term ADC AM CD CLK CRC DR GFSK ISM kSPS MCU PWR_DWN PWR_UP RX SPI CSN MISO MOSI SCK SPS STBY TRX_EN TX TX_EN Description Analog to Digital Converter Address Match Carrier Detect Clock Cyclic Redundancy Check Data Ready Gaussian Frequency Shift Keying Industrial-Scientific-Medical kilo Samples per Second Micro Controller Unit Power Down Power Up Receive Serial Programmable Interface SPI Chip Select Not SPI Master In Slave Out SPI Master Out Slave In SPI Serial Clock Samples per Second Standby Transmit/Receive Enable Transmit Transmit Enable Table 30. Glossary of terms.

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