Вы находитесь на странице: 1из 3

INSERTION DELAY: Usually in a clock tree file we need to provide the values of insertion delay and skew values.

I have read, that its usually advisable to give 10% of clock period for minimum skew value if The chip is not much big in size and we can go below to 5% as chip size increases. Anyway the Skew value is dependent on the technology also. If i make the skew value to a low value it will Make my design consume high power, because of the clock buffers needed to attain the skew value. So someone please throw some ideas how the skew value and insertion delay values can be chosen for a design. I know the definitions of both and also I know the skew value can't be more than the clock period. So please give me a clear answer from your experience, How I can decide a safe skew value for the Clock which will meet the timing with minimum power consumption. This is going to be very design-dependent, so I think the best thing is to do several experiments Until you find something you're happy with. For insertion delay, you may also need to make sure Its not bigger than the clock period. Also, keep in mind that global skew isn't necessarily a Target in itself - it's the local skew that matters. You may be able to still make timing with a bigger global skew (which should reduce the insertion delay/buffers). Sorry if this isn't much Help - maybe some other users will chime in with some advice! The combination of clock skew scheduling and delay insertion may lead to further clock period reduction. Although some previous works can minimize the clock period, they only heuristically reduce the required Inserted delay. However, since the delay insertion is an ECO (engineering change order) process, minimizing The required inserted delay is very important for the design closure, hi this paper, we present a linear Program to formally formulate the simultaneous application of clock skew scheduling and delay insertion. Our objective is not only to achieve the lower bound of the clock period, but also to achieve the lower bound of required inserted delay. Compared with previous works, our paper has the following two significant

Contributions: (1) our approach is the first work that guarantees solving this problem optimally; and (2) Our paper is the first proof of showing that the time complexity of this problem is polynomial. In clock tree synthesis, how to decide whats the maximum allowable skew and maximum insertion delay for a given clock say k MHZ and also how to decide when we have multiple clocks in the design and whats the relation between these parameters Skew in general would be around 2 * (inverter delay). Maximum allowable skew is less than clock period. There is no relation b/w insertion delay and clock frequency, but for a subchip it is derived from the top level specification, ideally it is kept as small as possible considering the effects of jitter and dynamic power consumption. Is there any relation between clock skew and insertion delay? Can someone provide more info on these parameters or provide doc if any. How can i target these two parameters for my design/? Could you please give more explaining on this? Only one relation b/w these two is skew is always less than the insertion delay :) There is no relation b/w these two parameters, even though if you have 2-10ns of insertion delay you can close the design with less than 0 ps skew ideally. In general try to minimize the insertion delay as much as possible, even you can make lesser insertion delay than the target given by top level. You can just add in the top level in that case. But always try to minimize insertion delay in order to lessen the effects of jitter. You need to minimize the skew, not to run to setup/hold issue. If you do not meet timing either you can skew or deskew for some flops, so in that case your skew is more than your target skew for those flops. But based on my experience do not skew or deskew blindly in order to meet timing. Quality of CTS engine depends on how low skew & latency values it is providing while maintaining the level of clock tree structure and how many buffers its inserting so generally it is followed to give a 0ps target for both in first iteration and from this iteration reports, set the target for both parameters for next iterations,, but for sure it is not straight fwd tat,, this much of skew/latency target will give good quality CTS. These both depend on the design size even, so for the same tech node and speed, two designs may have diff values. I have done some experiments on some ARM cores using SOCE, and found that for those cores. it is better to start with skew target of 10% of clock period. But this number is not a concrete one to be used everywhere

What we give to the tool for CTS: Skew: global skew or local skew or a range like min to max skew? Latency: min latency or max latency or range like min to max latency? What is the purpose to give these constraints like this? What to think to reduce Clock Insertion Delay in the Design 1. Number of Clock sinks 2. Balancing two different clock frequencies 3. Placement of clock sinks. 4. Placement of Clock gating cells 5. Clock tree buffers/inverters drive strength's 6. Clock Transition 7. Placement of Clockgating cells and the clock sinks 8. Combinationals cells in the path of clocks (say clock dividers, muxes, clockgates) ...