A fully Synchronous Circuit design for embedded DRAM

A.Yamazaki, N.Okumura*, K.Dosaka, and M.Kumanoya ULSI Lab. / System LSI Lab*., Mitsubishi Electric Corp. 4-1, Mizuhara, Itami, Hyogo 664, Japan Abstract A fully synchronous circuit for embedded DRAMs is presented. It realizes accurate DRAM timing control, and easy timing adjustment. Using the circuit, software switching of the control timing is realized without difficulty. Providing handshake signals to on-chip memory-controller simplifies the memory-controller circuit in a CPU embedded DRAM. 1. Introduction Since the address multiplex scheme was adopted into the 4K-bit MOS DRAM, conventional DRAMs have kept their asynchronous design for over 20 years. Careful timing control is necessary to sense a small voltage signal of the 1Tr/1C memory cell. To fine-tune the timing, the internal DRAM control signals are generated as the delay signals of the Row Address Strobe signal(/RAS) or the Column Strobe signal(/CAS), with series of delay elements. The DRAM operation isn't synchronized with a system clock because enough internal clock edges could not be produced with the system clock. Recently, several high speed DRAMs have been introduced [1-3]. All of them operate synchronously with the system clock, but only I/O circuits and address paths are replaced with the synchronous circuits. Basically, most of their internal control circuits remain asynchronous. This is also true in the previous CPU embedded DRAM[4]. The demerits of the asynchronous control with the delay elements are follows: (1) Access time is considerably affected by the supply voltage and temperature. (2) The actual waveforms are usually different from the simulated results due to the large dependency of the process parameter. (3) Large area is occupied with the additional delay elements to fine-tune the timing. This paper proposes a fully synchronous control circuit for embedded DRAM. The merits of the fully synchronous circuit are as follows: (1) The control timing is accurate, because it is generated by counting the number of the external clocks. (2) Typical ASIC standard cells can be used for the DRAM control logic. (3) The circuit is suitable to employ logic synthesis and Place & Router tools. In addition to these merits, the following functions can be easily implemented in the CPU embedded DRAM. (1) Software switching of the DRAM control timing is realized with no difficulty. (2) Providing handshake signals to on-chip memory-controller simplifies the controller circuit in a CPU embedded DRAM. 2. Circuit Design 2-1. DRAM control signals & timing The typical address and data paths of the DRAM are shown in fig.1(a) and the control timing is indicated in fig.1(b). The meaning of control signals is explained in table 1. Because the DRAM read-operation is destructive, careful timing control of the row operation is necessary as described below: (1) The row address decoding can't be started until after the addresses are latched to prevent temporary and unexpected word-line selection. (2) The word line should not be activated until the equalization signal of the bit line is completely deactivated. (3) The bit line should be sensed after the memory cell data is sufficiently transferred to it. For the column control, careful control is necessary for the points listed below: (1) The CDE signal should not be activated until after the column addresses are latched to prevent the invalid data from being transferred to the I/O line. (2) The PAE signal should be asserted after the bit line data is sufficiently transferred to the I/O line. 2-2. Block diagram of the fully synchronous circuit The block diagram of the fully synchronous DRAM control circuit is shown in fig.2. The circuit consists of the row and column counters, and the control signals generator. Each counter operates synchronously with the positive edges of both clock P1 and clock P2, which are non-overlapped complementary clocks. The row counters are

controlled with the Row-Activation-Request(ACT) signal and the Row-Precharge-Request(PCG) signal. The column counter is controlled by the Read-Operation-Request(RREQ) signal and Write-Operation-Request(WREQ) signal. Each request signal is generated by the memory controller, synchronized with clock P2, and sampled at the edge of clock P1. The DRAM control signal generator uses the row and column outputs to create its outputs. 2-3. Fully synchronous circuit The row counter, which is based on the Johnson counter, is shown in fig.3(a). The counter counts up at the positive edge of both clock P1 and P2, to generate the DRAM control signals at a half clock interval. The merits of Johnson counter are: (1) All of the control signal generators can be built only with the 'OR' or 'AND' gates. (2) The Johnson counter creates a-half-clock-interval timing easier than with Binary counter. A state diagram is shown in fig.3(b). The counter starts with the assertion of the ACT signal, and it stops after the row-active time (tRAS). The tRAS period is adjustable with 'Row-Stop-Decoder' in fig.3(a). After the column operations, the PCG signal is asserted by the memory controller. In response to this signal, the row counter starts to count up again, and it is reset to the initial state after the row-precharge time (tRP). The tRP is adjusted by the 'RowReset-Decoder' in fig.3(a). The column counter and it's state diagram are shown in fig.4(a) and 4(b), respectively. The column counter is based on the Johnson-counter, too. The counter starts with the RREQ or WREQ signal, and stops after the columnactive time (tCAS). The tCAS period is adjustable with 'Column-Reset-Decoder' in fig.4(a). Two flip-flops should be used to indicate a column read operation or write. The reason for using two flip-flops is to prevent hazard on the column control signals during the successive column operations. For generating the DRAM row control signals, only a 2-input 'AND' gate or 'OR' gate is needed to decode the counter outputs. For easy modification, the complex gate shown in fig.5 is best, because it has both 'OR' and 'AND' functions by switching the level of the 'C' terminal. 2-4. Waveforms The waveforms which were generated with the fully synchronous circuits from fig.2 are shown in fig.6. The enable period of each control signal depends on the counter value. Because there are only a few logic gates between the flip-flops of the counters and the outputs of the DRAM control signals, the control timing shows a smaller voltage dependency, temperature and the process parameter variation compared to the conventional asynchronous circuits. 3.Application to CPU embedded DRAM The fully synchronous circuits are applied to a CPU embedded DRAM, as shown in fig.7. The timing of the DRAM control signals are adjustable with the software. During the reset sequence of the CPU, the timing information is set to the 'Timing-Select-Register' by the on-chip memory controller. The purpose of software switching is to cover a wide range of the clock frequencies. Using the proposed counter, it is easy to implement this function by adding some selectors to the portions listed below. (1) The row-stop-decoder and reset-decoder(in fig.3(a)) (2) The column-reset-decoder(in fig.4(a)) (3) The control signal generators(in fig.5) An example of the control signal generators is shown in fig.8. In ordinary, the memory controller has be designed to wait for some cycles after requesting the DRAM operation. These cycles are called latency cycles. In the DRAM operation, following latency cycles exist. Row Active latency(tRAS) ,Row Precharge latency(tRP), Row to Column Delay latency(tRCD) ,CAS to CAS Delay latency(tCCD) For each latency, the memory controller has to count the clock numbers to wait for requesting next DRAM operation. By counting the latency cycles on the DRAM side and providing the handshake signals to the controller listed below, the controller doesn't have to take care of the various latency cycles. What the memory controller does is only sampling these signals to detect completion of the latency cycles. (1) RINH signal:Inhibiting the row command input during tRAS and tRP. (2) CINH signal:Inhibiting column command input during the tRCD. (3) CEND signal:Inhibiting column command input during the tCCD. These signals are simply generated by decoding proposed counter outputs, and their operation waveforms are shown in fig.9. 4.Conclusion A fully synchronous circuit design, which is based on the Johnson counter, for embedded DRAM is proposed. It realizes the timing resolution of half clock intervals. So, fine timing resolution is obtained, even if the clock frequency is under 100MHz. The fully synchronous circuit makes the DRAM control timing accurate.

The proposed circuit easily realizes the software switching of the DRAM control timing. In addition, generating the handshake signals, which inform the latency passage to the memory controller, is easy for proposed circuit, and it simplifies the on-chip memory controller in CPU embedded DRAM. 5. Reference [1]. N.Kushiyama et al.,"500 Mbyte/sec data-rate 512Kbits x9 DRAM Using a novel I/O interface," in Symp. on VLSI Circuits Digest Technical Papers, p66-67,June. 1992. [2]. Y.Takai et al., "250Mbyte/sec synchronous DRAM using 3-state-Pipelined Architecture," in Symp. on VLSI Circuits Digest Technical Papers, pp. 59-60, May. 1993. [3]. K.Dosaka et al., "A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU", in Symp. on VLSI Circuits Digest Technical Papers, pp. [4]. T.Shimizu et al, "A Multimedia 32b RISC Microprocessor with 16Mb DRAM," in ISSCC Digest Technical Papers, pp. 216-217, Feb. 1996.

BLI0 SAP Memory Cell BL

BLEQ

SAN

Write WDE Driver

BLI1

RAS CAS RAL RADE

BL VBL WLE RADE Row Dec. Row Add. Buf. Add. RAL RAS CAS WE CDE CAL Col Dec. Col Add. Buf. PreAmp. PAE

BLI BLEQ WLE SAN SAP CAL CDE PAE

DRAM control signal generator

fig.1(a) Typical address and data paths of the 1Tr/1C DRAM fig.1(b) Control timing RAL : Row Address Latch RADE: Row Address Enable /BLI : Bit Line Isolate BLEQ : Bit Line Equalize WLE : Word Line Enable SAN : Sense-Amp. enable for N-ch /SAP : Sense-Amp. enable for P-ch CAL : Column Address Latch CDE : Column Decoder Enable PAE : Pre-Amp. Enable WDE : Write Driver Enable table 1 Control signals

P1 P2 ACT PCG

Row Counter DRAM control sig. generator Col Counter

RAL RADE BLI BLEQ WLE SAN SAP CAL CDE PAE WDE

RREQ WREQ

fig.2 Block diagram of fully synchoronous circuit

FF1<4> FF2<4> CO1<4> CO1<4> D P2 Q Q CO2<3> CO2<3>

Row Reset Decoder

CO1<4> CO1<3> CO1<2> CO1<1> CO1<0>

D P1 R

Q Q

Reset

CO1<3>

Row Stop Decoder

CO1<4> CO1<3> CO1<2> CO1<1> CO1<0> FF1<1> D Q R Q CO1<1> CO1<1> FF2<1> D P2 Q Q CO2<1> CO2<1>

ACT
00000

ACT

00001

00011

00111

PCG ACT

Wait

P1

10000
FF1<0> D P1 R Q Q CO1<0> CO1<0> FF2<0> D P2 Q Q CO2<0> CO2<0>

01111

PCG
11000 11100

PCG

11110

11111

fig.3(a) Row counter circuit

fig.3(b) State diagram of P1 row counter

Col Reset Decoder

FF1<1> D P1 Q R Q CO1<1> CO1<1>

FF2<1> D P2 Q Q CO2<1>

RREQWREQ RREQ|WREQ
CO2<1>

CO1<1> CO1<0>

Reset
D

00

01

RREQ WREQ

FF1<0> Q CO1<0> CO1<0> FF2_R D P2 FF2_W D P2 Q Q

FF2<0> D P2

Q
Q

CO2<0> CO2<0>

P1 R Q FF1_R D P1 R FF1_W D P1 R Q Q

10

11

READ_FLAG

fig.4(b) State diagram of P1 column counter

Write_FLAG

A B C

Example A:CO1<2> Y B:CO2<1> C:'L' Y:SAN

fig.4(a) Column counter circuit

P1 P2 ACT PCG RREQ
Row Count(P1)00000 00001 Row Count(P2) Col Count(P1) Col Count(P2) 00011 00111 01111 11111 11110 11110 11100 11000 00000 00000 00001 00011 00111 01111 11111 11110 11110 11100 11000 00000

fig.5 Control signal generator

00000 00001

00011 00000 00011 00000

00000 00001

RAL RADE BLI BLEQ WLE SAN SAP CAL CDE PAE
SANfunc CO2<1> CO1<1> CO2<2> SANset<0> SANset<1> CO1<3> CO2<3> CO1<4> SANrst<0> SANrst<1>
3to1 Selector 3to1 Selector

SAN

fig.6 Waveforms of fully synchronous ciruit

fig.8 Flexible control generator

Inst. Que

P1 P2 ACT

CPU
Data Buffer SRAM Cache

Fully sync. DRAM

PCG RREQ
Row Count(P1)00000 00001 Row Count(P2) Col Count(P1) Col Count(P2) 00011 00111 01111 11111 11110 11110 11100 11000 00000 11000 00000 00000 00001 00011 00111 01111 11111 11110 11110 11100

Memory Cont.

DRAM Control Bus DRAM Address Bus RINH,CINH,CEND

00000 00001

00011 00000

00000 00001 00011 00000

RINH

tRAS tRCD tCCD

tRP

TAG Memory

Timing Select registers

CINH CEND

fig.7 CPU embeded DRAM

fig.9 Waveforms of the handshake signals