NAME : OWORU THEOPHILUS MAYOWA DEPT: COMPUTER SCIENCE CLASS: HND 1

DISCUSSING INSTRUCTION SET ARCHITECTURE

An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine language), and the native commands implemented by a particular processor. Instruction set architecture is distinguished from the microarchitecture, which is the set of processor design techniques used to implement the instruction set. Computers with different microarchitectures can share a common instruction set. For example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the x86 instruction set, but have radically different internal designs. Some virtual machines that support bytecode for Smalltalk, the Java virtual machine, and Microsoft's Common Language Runtime virtual machine as their ISA implement it by translating the bytecode for commonly used code paths into native machine code, and executing lessfrequently-used code paths by interpretation; Transmeta implemented the x86 instruction set atop VLIW processors in the same fashion.

INSTRUCTION SET ARCHITECTURE

1. The instruction set architecture (ISA) is the interface between the software and hardware. 2. Computers do not understand high level languages. For a processor to understand instructions, they must be encoded as binary numbers. 3. Besides instructions, the ISA also defines the items in the computer that are available to a program. For example, it defines data types, registers, addressing modes, memory organization and etc. 4. Register indexes (or names) and memory addressing modes are the ways in which the instructions locate their operands. 5. Software tools, special computer programs such as compilers, translate high level languages into instructions for a particular instruction set architecture. 6. The ISA of a computer is usually described in a small book or pamphlet that describes the binary numbers that encode the instructions. Most often, the short three-letter human names for the instructions can be recognized by a software development tool called an assembler. An assembler is a computer program to translate a human-readable form of the ISA into a computer-readable form. Disassemblers are also widely available,
1

VARIOUS INSTRUCTION SET ARCHITECHTURE

Computer architectures are often described as n-bit architectures. Today n is often 8, 16, 32, or 64, but other sizes have been used. This is actually a strong simplification. A computer architecture often has a few more or less "natural" datasizes in the instruction set, but the hardware implementation of these may be very different. Many architectures have instructions operating on half and/or twice the size of respective processors major internal datapaths. Examples of this are the 8080, Z80, MC68000 as well as many others. On this type of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The external databus width is often not useful to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses. The NS32764 had a 64-bit bus, but used 32bit registers. The width of addresses may or may not be different than the width of data. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors.

Operands
The number of operands is one of the factors that may give an indication about the performance of the instruction set. A three-operand architecture will allow
A := B + C

to be computed in one instruction. A two-operand architecture will allow

A := A + B

to be computed in one instruction, so two instructions will need to be executed to simulate a single three-operand instruction
A := B A := A + C

Endianess
An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little endian processors order bytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big endian architectures instead order them with the most significant byte at the lowest-numbered address. The x86 and the ARM architectures as well as several 8-bit architectures are little endian. Most RISC architectures (SPARC, Power, PowerPC, MIPS) were originally big endian, but many (including ARM) are now configurable.

DISCUSSING THE BASIS OF INSTRUCTION SETS

ARCHITECHTURE
A complex instruction set computer CISC has many specialized instructions, which may only be rarely used in practical programs. A Reduced instruction set computer(RISC) simplifies the processor by only implementing instructions that are frequently used in programs; unusual operations are implemented as subroutines, where the extra processor execution time is offset by their rare use. Theoretically important types are the minimal instruction set computer and the one instruction set computer but these are not implemented in commercial processors. Another variation is the very long instruction word (VLIW) where the processor receives many instructions encoded and retrieved in one instruction word.

Instruction types
Some operations available in most instruction sets include:

Data handling and Memory operations o set a register (a temporary "scratchpad" location in the CPU itself) to a fixed constant value o move data from a memory location to a register, or vice versa. This is done to obtain the data to Complex instructions

Some computers include "complex" instructions in their instruction set. A single "complex" instruction does something that may take many instructions on other computers. Such instructions are typified by instructions that take multiple steps, control multiple functional units, or otherwise appear on a larger scale than the bulk of simple instructions implemented by the given processor. Some examples of "complex" instructions include:

saving many registers on the stack at once

3

moving large blocks of memory complex and/or floating-point arithmetic (sine, cosine, square root, etc.) performing an atomic test-and-set instruction instructions that combine ALU with an operand from memory rather than a register A complex instruction type that has become particularly popular recently is the SIMD or Single-Instruction Stream Multiple-Data Stream operation or vector instruction, an operation that performs the same arithmetic operation on multiple pieces of data at the same time. SIMD have the ability of manipulating large vectors and matrices in minimal time. SIMD instructions allow easy parallelization of algorithms commonly involved in sound, image, and video processing. Various SIMD implementations have been brought to market under trade names such as MMX, 3DNow! and AltiVec.

DISCUSSIONG CISC AND RISC TERMS

The terms CISC and RISC have become less meaningful with the continued evolution of both CISC and RISC designs and implementations. The first highly (or tightly) pipelined x86 implementations, the 486 designs from Intel, AMD, Cyrix, and IBM, supported every instruction that their predecessors did, but achieved maximum efficiency only on a fairly simple x86 subset that was only a little more than a typical RISC instruction set (i.e. without typical RISC loadstore limitations). The Intel P5 Pentium generation was a superscalar version of these principles. However, modern x86 processors also (typically) decode and split instructions into dynamic sequences of internally-buffered micro-operations, which not only helps execute a larger subset of instructions in a pipelined (overlapping) fashion, but also facilitates more advanced extraction of parallelism out of the code stream, for even higher performance. Contrary to popular simplifications (present also in some academic texts), not all CISCs are microcoded or have "complex" instructions. As CISC became a catch-all term meaning anything that's not a load-store (RISC) architecture, it's not the number of instructions, nor the complexity of the implementation or of the instructions themselves, that define CISC, but the fact that arithmetic instructions also perform memory accesses.[citation needed] Compared to a small 8-bit CISC processor, a RISC floating-point instruction is complex. CISC does not even need to have complex addressing modes; 32 or 64-bit RISC processors may well have more complex addressing modes than small 8-bit CISC processors.

Classification of instruction sets

A complex instruction set computer CISC has many specialized instructions, which may only be rarely used in practical programs. A Reduced instruction set computer(RISC) simplifies the
4

processor by only implementing instructions that are frequently used in programs; unusual operations are implemented as subroutines, where the extra processor execution time is offset by their rare use. Theoretically important types are the minimal instruction set computer and the one instruction set computer but these are not implemented in commercial processors. Another variation is the very long instruction word (VLIW) where the processor receives many instructions encoded and retrieved in one instruction word.

The design of instruction sets is a complex issue. There were two stages in history for the microprocessor. The first was the CISC (Complex Instruction Set Computer) which had many different instructions. In the 1970s, however, places like IBM did research and found that many instructions in the set could be eliminated. The result was the RISC (Reduced Instruction Set Computer), an architecture which uses a smaller set of instructions. A simpler instruction set may offer the potential for higher speeds, reduced processor size, and reduced power consumption. However, a more complex set may optimize common operations, improve memory/cache efficiency, or simplify programming. A complex instruction set computer (CISC, /ssk/) is a computer where single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) and/or are capable of multi-step operations or addressing modes within single instructions. The term was retroactively coined in contrast to reduced instruction set computer (RISC).[1] Examples of CISC instruction set architectures are System/360 through z/Architecture, PDP-11, VAX, Motorola 68k, and x86. The IBM System/360 (S/360) was a mainframe computer system family first announced by IBM on April 7, 1964, and sold between 1964 and 1978. It was the first family of computers designed to cover the complete range of applications, from small to large, both commercial and scientific. The design made a clear distinction between architecture and implementation, allowing IBM to release a suite of compatible designs at different prices. All but the most expensive systems used microcode to implement the instruction set, which featured 8-bit byte addressing and binary, decimal and floating-point calculations. The slowest System/360 models announced in 1964 ranged in speed from 0.0018 to 0.034 MIPS;[1] the fastest System/360 models were approximately 50 times as fast[2] with 8 kB and up to 8 MB of internal main memory,[2] though the latter was unusual, and up to 8 megabytes of slower Large Core Storage (LCS). A large system might have as little as 256 kB of main storage, but 512 kB, 768 kB or 1024 kB was more common. The 360s were extremely successful in the market, allowing customers to purchase a smaller system with the knowledge they would always be able to migrate upward if their needs grew, without reprogramming of application software. The design is considered by many to be one of the most successful computers in history, influencing computer design for years to come. The chief architect of the S/360 was Gene Amdahl, and the project was managed by Fred Brooks, responsible to Chairman Thomas J. Watson Jr.[2] The 360's commercial release was

piloted by another of Watson's lieutenants John R. Opel who managed the launch of IBMs System 360 mainframe family in 1964.[3] Application level compatibility (with some restrictions) for System/360 software is maintained until present day with the IBM zSeries computers.

System/360 history

An IBM System/360-20 (w/ front panels removed), with IBM 2560 MFCM (Multi-Function Card Machine)

IBM System/360 Model 30 at the Computer History Museum.

System/360 Model 65 operator's console, with register value lamps and toggle switches (middle of picture) and "emergency pull" switch (upper right).

A family of computers
Contrasting with at-the-time normal industry practice, IBM created an entire series of computers (or CPUs) from small to large, low to high performance, all using the same instruction set (with two exceptions for specific markets). This feat allowed customers to use a cheaper model and then upgrade to larger systems as their needs increased without the time and expense of rewriting software. IBM was the first manufacturer to exploit microcode technology to implement a compatible range of computers of widely differing performance, although the largest, fastest, models had hard-wired logic instead. This flexibility greatly lowered barriers to entry. With other vendors (with the notable exception of ICT), customers had to choose between machines they could outgrow and machines that were potentially overpowered (and thus too expensive). This meant that many companies simply did not buy computers.

Models
IBM initially announced a series of six computers and forty common peripherals. IBM eventually delivered fourteen models, including rare one-off models for NASA. The cheapest model was the S/360-20 with as little as 4 K of core memory, eight 16-bit registers instead of the sixteen 32-bit registers of real 360s, and an instruction set that was a subset of that used by the rest of the range. (The Model 20 was suited for smaller businesses yet it had the IBM name and salesforce.) The initial announcement in 1964 included Models 30, 40, 50, 60, 62, and 70. The first three were low- to middle-range systems aimed at the IBM 1400 series market. All three were sold first during mid-1965. The last three, intended to replace the 7000 series machines, were never sold and were replaced by the 65 and 75, which was first delivered during November 1965, and January 1966, respectively. Later additions to cheaper models included the 20 (1966, mentioned above), 22 (1971), and 25 (1968). The Model 22 was a recycled Model 30 with minor limitations: a smaller maximum memory configuration, and slower I/O channels which limited it to slower and lower-capacity disk and tape devices than on the 30. The Model 44 (1966) was a variant aimed at the mid-range scientific market with hardware floating point but an otherwise limited instruction set.

This image of the System/360 Model 91 was taken by NASA sometime in the late 60s. A succession of high-end machines included the 67 (1966, mentioned below, briefly anticipated as the 64 and 66[4]), 85 (1969), 91 (1967, anticipated as the 92), 95 (1968), and 195 (1971). The 85 design was intermediate between the System/360 line and the follow-on System/370 and was the basis for the 370/165. There was a System/370 version of the 195, but it did not include Dynamic Address Translation. The implementations differed substantially, using different native data path widths, presence or absence of microcode, yet were extremely compatible. Except where specifically documented, the models were architecturally compatible. The 91, for example, was designed for scientific computing and provided out-of-order instruction execution (and could yield "imprecise interrupts" if a program trap occurred while several instructions were being read), but lacked the decimal instruction set used in commercial applications. New features could be added without violating architectural definitions: the 65 had a dual-processor version (M65MP) with extensions for inter-CPU signalling; the 85 introduced cache memory. Models 44, 75, 91, 95, and 195 were implemented with hardwired logic, rather than microcoded as all other models. The S/360-67, announced in August 1965, was the first production IBM system to offer dynamic address translation hardware to support time-sharing. "DAT" is now more commonly referred to as an MMU. An experimental one-off unit was built based on a model 40. Before the 67, IBM had announced models 64 and 66, DAT versions of the 60 and 62, but they were almost immediately replaced by the 67 at the same time that the 60 and 62 were replaced by the 65. DAT hardware would reappear in the S/370 series in 1972, though it was initially absent from the series. Like the 65 to which it was closely related, the 67 also had a dual-CPU implementation. All System/360 models were withdrawn from marketing by the end of 1977.

Backward compatibility
IBM's existing customers had a large investment in software that executed on second generation machines. Many models offered the option of emulation of the customer's previous computer (e.g. the IBM 1400 series on a 360-30 or the IBM 7094 on a 360-65) using a combination of special hardware,[5] special microcode and an emulation program that used the emulation instructions to simulate the target system, so that old programs could run on the new machine. However, customers had to halt the computer and load the emulation program.[6] The 360/85 and

later System/370 retained the emulation options, but allowed them to be executed under operating system control alongside native programs.[7]

Successors and variants

The S/360 (excepting the 360/20) was replaced by the compatible System/370 range in 1970 and 360/20 users were targeted to move to the IBM System/3. (The idea of a major breakthrough with FS technology was dropped in the mid-1970s for cost-effectiveness and continuity reasons.) Later compatible IBM systems include the 3090, the ES/9000 family, 9672 (System/390 family), the zSeries, System z9, System z10 and IBM zEnterprise System. Computers that were mostly[NB 1] identical or compatible in terms of the machine code or architecture of the System/360 included Amdahl's 470 family (and its successors), Hitachi mainframes, the UNIVAC 9200/9300/9400 series, the English Electric System 4, and the RCA Spectra 70 series, which was sold to what was then UNIVAC to become the UNIVAC 90/60 and later releases. The Soviet Union produced an S/360 clone named the ES EVM. The IBM 5100 portable computer, introduced in 1975, offered an option to execute the System/360's APL.SV programming language through a hardware emulator. IBM used this approach in order to avoid the costs and delay in creating a version of APL specific to the 5100. Special radiation-hardened and otherwise somewhat modified S/360s, in the form of the System/4 Pi avionics computer, are used in several fighter and bomber jet aircraft. In the complete 32-bit AP-101 version, 4 Pi machines are used as the replicated computing nodes of the fault-tolerant Space Shuttle computer system (in five nodes). The U.S. Federal Aviation Administration operated the IBM 9020, a special cluster of modified System/360s for air traffic control, from 1970 until the 1990s. (Some 9020 software is apparently still used via emulation on newer hardware.

Comparison of CPU architectures

Computer architectures are often described as n-bit architectures. Today n is often 8, 16, 32, or 64, but other sizes have been used. This is actually a strong simplification. A computer architecture often has a few more or less "natural" datasizes in the instruction set, but the hardware implementation of these may be very different. Many architectures have instructions operating on half and/or twice the size of respective processors major internal datapaths. Examples of this are the 8080, Z80, MC68000 as well as many others. On this type of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The external databus width is often not useful to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses. The NS32764 had a 64-bit bus, but used 32-bit registers.

The width of addresses may or may not be different than the width of data. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors.

[edit] Operands
The number of operands is one of the factors that may give an indication about the performance of the instruction set. A three-operand architecture will allow
A := B + C

to be computed in one instruction. A two-operand architecture will allow

A := A + B

to be computed in one instruction, so two instructions will need to be executed to simulate a single three-operand instruction
A := B A := A + C

10