DEPARTMENT OF ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING

DIGITAL SYSTEMS ERS 220

PRACTICAL 3: Sequential logic circuit design

A game of Ping-Pong.

DATE: 24/10/2011

Name: Frederick Schalk Montgomery

Student no. 10030868

Name: Joshua Leigh Sendall

Student no. 10029924

Name: Sebastian Sylvo Volker

Student no. 10000543

Name: Danil Andr van der Walt

Student no. 10042088

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Contents
List of Figures ............................................................................................................................................... iii
AIM OF THE PRACTICAL ................................................................................................................................ 1
METHOD........................................................................................................................................................ 1
RESULTS ........................................................................................................................................................ 2
CONCLUSION............................................................................................................................................... 14
BIBLIOGRAPHY ............................................................................................................................................ 14

List of Figures

Figure 1, State diagram. ................................................................................................................................ 2

Figure 2, Logical OR gate truth table. ........................................................................................................... 3
Figure 3, Logical AND gate truth table. ......................................................................................................... 3
Figure 4, Logical XOR gate truth table. ......................................................................................................... 3
Figure 5, Logical INVERTER truth table. ........................................................................................................ 3
Figure 6, Excitation table. ............................................................................................................................. 5
Figure 7, S0* Excitation map. ........................................................................................................................ 6
Figure 8, S1* Excitation map. ........................................................................................................................ 7
Figure 9, Circuit 1. ......................................................................................................................................... 8
Figure 10, Circuit 2. ....................................................................................................................................... 9
Figure 11, Circuit 3. ..................................................................................................................................... 10
Figure 12, Circuit 4. ..................................................................................................................................... 11
Figure 13, Circuit 5. ..................................................................................................................................... 11
Figure 14, Circuit 6. ..................................................................................................................................... 12
Figure 15, Circuit 7. ..................................................................................................................................... 13
Figure 16, Circuit 8. ..................................................................................................................................... 13

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AIM OF THE PRACTICAL

The aim of this practical project was to successfully implement the aspect of memory in sequential logic
circuits to create a game of Ping-Pong. The game would be played by two players, each controlling a
paddle consisting of two parts, an upper half as well as a lower half. Therefore it can be seen as a
game of doubles.
The constraints for this project were detailed by the rules that had to be designed into the game. A
working implementation of a scoring system between the two players was attempted seeing as extra
marks would be awarded for extra effort.
An appropriate hypothesis for this project is that it will have to be a Mealy machine design, seeing as
inputs and current states will have to influence future states.

METHOD
Firstly, following the design principles stated in (Wakerley, 2007), the project was divided into three
parts, i.e. Next-State Logic, State Memory and Output Logic. A state diagram was then constructed
according to the word description of the problem given, to account for every possible situation in the
game. Secondly, the Excitation table and Excitation maps were constructed to relate inputs and current
states to next/future states.
It was chosen not to implement state registers, but rather only bit counters in conjunction with
decoders and a clock signal. The design of the court was expanded into a two-dimensional LED array
where the ball exhibited dynamic behaviour. The players would play the game by using the remote,
which allows for a comfortable and exciting gaming experience.
After the theoretical design of the project had been completed, the actual layout of the circuit had to be
designed and built. The circuit design was created using PSPICE and ORCAD software. After this step had
been completed, the actual circuit was realised using several logic gates, flip-flops, bit-counters, LEDs
and so forth.
Finally, the project also had to be coded in VHDL format. This was done only after the circuit had been
completely constructed.

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RESULTS
State diagram

Figure 1, State diagram.

LPB = Left Push Button

RPB = Right Push Button
LL = Left Lamp
RL = Right Lamp

In figure 1 it can be seen that scoring has not yet been implemented. After scoring has been taken into
account, it adds two more states to the above diagram i.e. one state being Player1 wins and the other
being Player2 wins.

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Truth and Excitation tables

Displayed below are the truth tables for the logic gates implemented in the design as well as the
Excitation table which relates Next-State logic and Current-State logic.

Figure 2, Logical OR gate truth table.

Figure 3, Logical AND gate truth table.

Figure 4, Logical XOR gate truth table.

Figure 5, Logical INVERTER truth table.

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S0

S1

LPB

RPB

L-LAMP

R-LAMP

S0*

S1*

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Figure 6, Excitation table.

Figure 6 above shows the relationship between the Next-State logic and Current-State logic. In each of
these states, the outputs of the circuit were clearly defined, the outputs being the LED array as well as
the scoring implementation. This is the Excitation table that was used to generate the Excitation maps in
order to obtain the simplified excitation equations.

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Excitation maps

Map for S0*

Figure 7, S0* Excitation map.

Using Product-of-Sums for the above Excitation map yields:

S0* = (S0 + S1 + LPB + RPB).(RPB + RL).(S0 + LPB + RPB).(S0 + LL)

This equation represents the next value of S0 as a function of the inputs and previous states. This
confirms the Mealy machine design hypothesis.

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Map for S1*

Figure 8, S1* Excitation map.

Using Sum-of-Products for the Excitation Map above yields:

S1* = LPB(RPB + RL) + RPB(LL + S0.RL + S0.LPB.RL) + (S0.LPB.RL) + (S0.LL + RL)

This equation represents the next value of S1 as a function of the inputs and previous states. This
confirms the Mealy machine design hypothesis.
The two excitation equations, given by S0* and S1*, were implemented by using normal combinational
logic design, i.e. logical AND, OR and NOT gates. Seeing as SO* and S1* are both functions of the inputs
and current states, the scoring implementation would also have to be dependent on these inputs and
states. The scoring implementation was formally described by the following equations:

Score_Player_1 = S1.S0.(RPB XOR RL)

Score_Player_2 = S1.S0.(LPB XOR LL)
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Circuit diagrams
Please refer to the diagrams below for the full representation of the logic circuit. Please also note that in
the logic diagrams, each logic gate is actually situated within its own specific IC (Integrated Circuit).
These ICs are all supplied with 5 Volts DC to enable proper functionality of the logic gates housed
within.

Circuit Diagram 1: LED implementation Part1

S0

CLK

S1

CLK
CLR

Bit
Counter

2
1
3

2
1
3

2
1
3

3-8 Decoder

Wires leading from the

3-8 decoder to the
LED's
Figure 9, Circuit 1.

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Circuit Diagram 2: LED implementation Part 2

Wires leading to
the 3-8 decoder

560

560

Wires leading
to the 4-2
decoder

560

560

Figure 10, Circuit 2.

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Circuit Diagram 3: LED implementation Part 3

(LL + RL)'

CLK

Wires leading
to the LEDs
3

CLK

CLK

1
2

4-2
Decoder

3
1
2

Bit
Counter

Figure 11, Circuit 3.

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Circuit Diagram 4: S0* Logic layout

1
2
8

S0

2
1
3
2
9

S1

8
10
4
3

6
5

LPB

1
2
6

S0*

4
5

RPB

6
1
3
2

RL

LL

3
2

Figure 12, Circuit 4.

Circuit Diagram 5: S1* Logic layout

LPB

RPB

6
1
9

3
8

10

RL

2
3

S1*
1

4
5
9

1
2
8

LL

10

4
6
5

S0

2
1
2
13

12

3
4
5

9
10
11

Figure 13, Circuit 5.

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Circuit Diagram 6: Remote Control logic layout

To main circuit board
Left Push Button

Right Push Button

VCC

VCC

3
2

5.6k
6

5.6k

Figure 14, Circuit 6.

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Circuit Diagram 7: Scoring implementation Part 1

2

RPB
RL

1
3
2
2

S1

Score_Player_1

Score_Player_2

3
2
1
3

S0

LPB
LL

1
3
2
3
2

S1
S0

2
1
3

Figure 15, Circuit 7.

Circuit Diagram 8: Scoring implementation Part 2

Score_Player_1

2
3
1
4

Clock

Q
Q

11

CLK

4
10
3
11

CLR
PRE

13
10

Player_1 Seven Segment

5
6

7474
12

Score_Player_2

8
6
Q
Q

9
8

CLK
CLR
PRE

13
1

A
B
C
D

QA
QB
QC
QD

5
9
2
12

Player_2 Seven Segment

CLK1
CLK2
CLR
LOAD
74196

7474

Figure 16, Circuit 8.

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CONCLUSION
It can be seen that a fully functional sequential logic circuit can be implemented to create a game of
Ping-Pong. Throughout this project, it was seen that memory forms an integral part of the design of
sequential logic circuits and also that memory can be used to perform a large variety of tasks.

BIBLIOGRAPHY

Digital Systems ERS 220. Studyguide.

Digital Systems ERS 220. [Online].Available:

<http://www.ee.up.ac.za/main/en/undergrad/subjects/ers220/index>. [Accessed 19 October
2011].

Wakerley, J. (2007). Digital Design: Principles and Practices 4th Edition. Pearson Prentice Hall.

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