Implemetation of a

Post-Layout Optimization method with Automatic Device Type Selection

within practical analog circuit design processes
Torsten Reich, Boyko Dimov, Christian Lang, Volker Boos, Eckhard Hennig

Outline
Motivation Proposed approaches
Post-layout-optimization Automatic Device Type Selection

Applications
BiCMOS buffer amplifier Photodetector IC for a high-speed Blu-ray Disc R/W pickup system

Conclusions

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Motivation (1): Pre-Layout vs. Post-Layout Performance

Problem: discrepancy between pre- and post-layout performance of analog and mixed-signal circuits
Pre-layout medium performance circuits Post-layout

330 MHz

270 MHz

high performance circuits

800 MHz

380 MHz

Reason: layout parasitics due to devices (20%) and interconnects (80%) Requirement: Parasitic-Aware design (pre-layout or post-layout)

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Motivation (2): Device Type Selection in BiCMOS Circuits

Fixed set of bipolar transistor device types (non-scalable or scalable in discrete steps) Device types must be chosen manually approach inefficient trial and error

BJT Type 1? BJT Type 2?

BJT Type n?

Requirement: Computer-aided circuit sizing with Automatic Device Type Selection

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Goal

Apply post-layout optimization and Automatic Device Type Selection simultaneously to BiCMOS circuit design for
increased design efficiency reduced performance discrepancies (schematic vs. post-layout) improved layout reuse capability

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Post-Layout Optimization: Proposed Approach

First way: course pre-layout optimization + post-layout optimization

Second way: layout-reuse

Reference: T.Reich et al, IEEE ICECS, 2009

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Automatic Device Type Selection: Proposed Approach

Post-layout optimization

circuit simulator model card Supertransistor

type 1 (emitter length 0.5 .. 50 m)

type 2 (fixed emitter length = 1 m)

Pre-layout optimization

parameter: type = emitter length =

type n (emitter length 10 .. 180 m)

Supertransistor device model interpolates continuously over all available BJT types (fixed and scalable) 2 continuous sweeping parameters type and emitter length Piecewise linear interpolation over BJT model card set Suitable for gradient-based optimization algorithm (snap-to-grid required after optimization) Reference: B.Dimov et al, Adv. Radio Sci. 7, 2009
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Implementation: Optimization Environment

Pre- and post-layout optimization using WickeD (MunEDA) Additional validation using Cadence 6 optimizer
Deterministic Optimization Sensitivity analysis

Regular design parameters (MOS W/L, R, C, ...)

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Sweeping parameters of Supertransistor (discrete and continuous)

Application 1: BiCMOS Buffer Amplifier, Layout Reuse

Redesign existing BiCMOS buffer amplifier for new load specifications Goals: improve performance, reuse layout 17 design parameters (9 regular device parameters and 8 sweeping parameters of Supertransistor model instances)

Size Device Parameters

Select Device Types

Simplified circuit diagram of the BiCMOS amplifier (Ref. P. M. Furth, MSCS 1993)

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Application 1: Results
Performance/ device parameters Goal postlayout Initial (aex) Optimization method Pre-layout Opt0 (aex) Post-layout (ADTS) Opt2

3dB-Bandwidth (MHz) Phase margin ( ) Peaking (dB) SR rise (MV/s) Supply current (mA)
Q1: type/el (m) Q2: type/el (m) Q3: type/el (m) Q4: type/el (m)

>700 >55 <1.0 >300 <2.0

-

323 (269) 69 (64) 0.6 199 (248) 1.8 (1.8)

3/2.4 3/2.4 3/4 3/4

806 (384) 61 (57) 0.7 (1.3) 304 (365) 2.0 (2.0)

3/4 3/2 3/3.9 3/4.3

700 55 0.9 331 2.0

1/4 1/1.5 1/1.5 3/5.6

Automatic Device Type Selection

initial aex

Pre-layout-opt: opt-results aex

Post-layout-opt: what you optimize is what you get ! opt-result aex

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Application 1: Results
Cost: 1.5 days for post-layout optimization and layout modifications Strongly decreased discrepancy schematic (sch) vs. post-layout (aex): > 20% (270 MHz) < 5% (700 MHz)
Pre-layout opt (sch)

Pre-layout opt (aex)

Post-layout opt = aex

Comparison of frequency responses CDNLIVE! 04.05.2011

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Application 1: Layout Modifications

BJT types exchanged Scalable circuit elements resized Layout modified in < 0.5 days 90% time saved (vs. new layout)

Modifications within the existing layout of the BiCMOS buffer amplifier CDNLIVE! 04.05.2011
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Application 2: High-speed Blu-ray Disc Pickup System

disc

objective lens (DVD/CD) coupling lens collimator (DVD/CD) laser diode (DVD: 650nm) dichotic mirror grating (DVD: 650nm)

reflection mirror (DVD/CD)

detection lens (DVD/CD)

laser diode CD: 780nm

Grating lens CD: 780nm

half mirror

Photodetector IC (PDIC)

Reference: Blu-ray Disc Founders (2004) CDNLIVE! 04.05.2011

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Application 2: High-Speed Blu-ray Disc Pickup System

Post-layout optimization (worst-case) of the complete amplifier chain Goal: > 300 MHz bandwidth for all 8 channel gain settings Specification not achieved with manual design > 50 design parameters and supermodel sweeping parameters
4x Main path

1x rf path

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Application 2: Results
Post-layout bandwidth > 300 MHz was achieved for all gains Post-layout optimization of the whole amplifier chain took less than 2 days

300 MHz
Fabricated chip of the pickup system

Measured frequency responses for one gain

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Conclusion
Discrepancy between pre- and post-layout performances was nearly removed due to parasitic awareness in post-layout optimization Automatic Device Type Selection is very efficient for automated circuit design (EDA) Successful application of both methods in a complex industrial project
excellent post-layout performance (> 300 MHz for 12x Blu-ray PDIC) less time and manpower as in comparable projects (cost saving ~25%)

The method is easy to implement in common design environments (e.g. Cadence 5/6, WickeD optimizer )

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Thank you for your attention!

Torsten Reich scientific co-worker, Department of Microelectronics IMMS GmbH Ehrenbergstrae 27 98693 Ilmenau, Germany Institutsteil Erfurt http://www.imms.de Tel.: +49 361-663 2561 Fax: +49 361-663 2501

E-Mail: Torsten.Reich@imms.de

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