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EE/OCT 2008/KJE609/ECE590/KJE416

UNIVERSITI TEKNOLOGI MARA FINAL EXAMINATION

COURSE COURSE CODE EXAMINATION TIME

: : : :

ELECTRONICS AND MICROPROCESSORS/ELECTRONICS KJE609/ECE590/KJE416 OCTOBER 2008 3 HOURS

INSTRUCTIONS TO CANDIDATES 1. 2. 3. 4. This question paper consists of five (5) questions. Answer ALL questions in the Answer Booklet. Start each answer on a new page. Do not bring any material into the examination room unless permission is given by the invigilator. Please check to make sure that this examination pack consists of: i) the Question Paper ii) an Answer Booklet - provided by the Faculty iii) a four page Appendix - MC68000 CPU instruction set

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This examination paper consists of 8 printed pages Hak Cipta Universiti Teknologi MARA CONFIDENTIAL

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QUESTION 1 a) Refer to the circuit in Figure Q1(a). The diode is made of silicon, calculate :i) ii) iii) the current that flows in the 1.5 KQ resistor, the power dissipated in the 4.7 KQ resistor, the voltage Vo.

State any assumption(s) made. 1.5K

i'wv
20 V -=
' Diode

Vo 4.7 K

Figure Q1(a) (6 marks) b) Refer to the circuit in Figure Q1(b). The transformer turns ratio is 10:1, and Vs is a 60 Hz sinusoidal voltage having peak value of 240 V. Assume that the diode is ideal. i) ii) sketch and label the voltage VL. calculate the current in RL when RL is 1 KQ.
Diode W

RL
Transformer

VL

Figure Q1(b) (6 marks)

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c)

The circuit in Figure Q1(c) below shows the voltage regulator of a DC power supply system, If IZ(max) = 32 mA, VZ = 12 V, RS = 0.5 KQ and VS = 45 V. i) ii) iii) Calculate the minimum value of RL for VL = 12 V. Calculate the minimum value of IL. Calculate the power rating of the Zener diode.
RS

V^

VS

RL

Figure Q1(c) (8 marks)

QUESTION 2 a) Figure Q2(a) shows a single-stage common emitter amplifier using a BJT transistor having the DC gain p of 120. Given that VCC = 25 V, R1 = 40 KO, R2 = 4 KQ, RC = 8 KQ, RE = 1.2 KQ. Vcc

R1

R2

Figure Q2(a) For the transistor, take VBE = 0.7V, determine :i) ii) iii) iv) the the the the Base voltage VB. Emitter voltage VE. Emitter current IE, Base current IB, and Collector current l c . Collector voltage VC and draw the DC load line for the transistor. (8 marks)
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b)

If the circuit shown in Figure Q2(a) above is used as an amplifier, calculate :i) ii) iii) the transresistance value, re. the input impedance Z|N, and output impedance ZOUTthe voltage gain, Av. (12 marks)

State and explain any assumption/s made during the analysis.

QUESTION 3 a) For the operational amplifier circuit in Figure Q3(a) below :i) ii) Derive the output voltage Vo, in terms of input voltages and the resistors, Determine the output voltage Vo, given that :V1 = 1V, R1 = 100 KQ, R2 = 150 KQ and Rf = 500 KQ.

Figure Q3(a) (5 marks)

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b)

The operational amplifier circuit in Figure Q3(b) is used to control the LED. Given that VCC = 5 V, R1 = R = 1 KQ and R2 = 2 KQ. If V1 can be varied between 0 to 5 V, calculate the input range of voltage V1 that will cause the LED to be ON.

Figure Q3(b) (6 marks) c) Convert the following numbers into the number system stated. Show all the calculations involved. i) ii) iii) 10011110100111012 convert into decimal number 52910 convert into binary number A175BEi6 convert into binary number (9 marks) QUESTION 4 a) i) ii) Deduce the Boolean expression for output F in terms of the input variables A, B and C for the logic circuit of Figure Q4(a). Obtain the simplified expression for F using the K-map method.

Figure Q4(a)
(6 marks)
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b)

Analyze the counter circuit of Figure Q4(b) below. All J-K inputs are connected to logic " 1 " , The SET and CLR inputs are inactive. i) ii) sketch the waveforms of C, B and A up to 8 clock pulses. modify the counter circuit so that the count now becomes 7, 6, 5, 7 ...

J
CLOCK

SET

Q Q

J K

SET

Q Q

J K

SET

Q Q

CLR

CLR

CLR

Figure Q4(b) (6 marks) c) Use JK-flip-flops to design a synchronous counter with the following repeated counting sequence :- 0 , 1 , 3, 2, 4, 6, 7. (8 marks)

QUESTION 5 a) Explain the function of the components of a microcomputer system below. i) ii) iii) Central Processing Unit (CPU) Memory Unit Input/Output Unit (6 marks)

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b)

Determine the contents of the registers and memory locations that are affected by the following MC68000 CPU instructions. The initial values inside the registers and memory locations are as shown in Table 1 and Table 2 below. Assume that before each instruction is executed, the registers and memory locations are restored to their original values. Every instruction is not related to each other. Table 1: Initial register contents DATA REGISTERS D0=$78904536 D1=$FFCB5A8B D2=$FFF81C18 D3=$0000186A ADDRESS REGISTERS A0=$00003000 A1=$00003001 A2=$00003002 A3=$00003003

Table 2: Initial memory contents ADDRESS $3000 $3001 $3002 $3003 i) ii) iii) iv) v) MOVE.L MOVE.B ASL.W ADD.W OR.W $3000, D3 D1,(A0) #5, D1 (A2), DO #$06, D2 (6 marks) DATA $52 $6A $06 $7D

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c)

Figure Q5(c) shows the MC68230 Pl/T connection to a 7-segment display unit. Draw the flowchart and write a MC68000 CPU assembly language program that will display the number " 1 " , when switch SW1 is pressed, and display the number "2", when switch SW2 is pressed. All other states of SW1 and SW2 causes the display to show number "0".

PAO-PAfs)
MC68230 Pl/T

BCD to 7-sagjnant Decoder

Figure Q5(c) (8 marks)

END OF QUESTION PAPER

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APPENDIX 1 (1)

EE/OCT2008/KJE609/ECE590/KJE416

Motorola MC68000 CPU Instruction Set

Assembler Syntax Data Size B-BWL -WL BWL BWL BWL BWL BWL BWL
Condition codes

Instruction Description ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ASL Add BCD with extend ADD binary ADD ADD ADD ADD binary to An Immediate 3-bit immediate extended

X N * U * * * * * * * *

Bit-wise AND Bit-wise AND with Immediate Arithmetic Shift Left

Dx,Dy - (Ax) ,-(Ay) Dn,<ea> <ea>,Dn <ea>,An #x,<ea> #<l-8>, <cea> Dy,Dx - (Ay) , - (Ax) <ea>,Dn Dn,<ea> #<data>,<ea> #<l-8>,Dy Dx,Dy <ea> Bcc.S <label> Bcc.W <label> Dn,<ea> #<data>,<ea> .. . BSR.S <label> BSR.W <label> Dn,<ea> #<data>,<ea> <ea>,Dn <ea> <ea>,Dn <ea>,An #<data>,<ea> (Ay)+, (Ax) + DBcc Dn,<label> <ea>,Dn <ea>,Dn Dn,<ea> #<data>,<ea> Rx,Ry

zV C *u * ** * -** ** ** *0 *0 ** ** -***-** * *
0 0 *

_ * _ * * *

ASR Bcc BCHG BCLR BSET BSR BTST CHK CLR CMP CMPA CMPI CMPM DBcc DIVS DIVU EOR EORI EXG EXT ILLEGAL JMP JSR LEA LINK LSL LSR MOVE MOVE MOVE

Arithmetic Shift Right Conditional Branch Test a Bit and CHanGe Test a Bit and CLeaR Test a Bit and SET Branch to SubRoutine Bit TeST

BWL BWB-L B-L B-L BWB-L -WBWL BWL -WL BWL BWL -W-W-WBWL BWL --L -WL

* * - - - - - - _ _ _ _ _ _ _ _ _ * * 0 * * * * * * * * * *

* -

uuu

CHecK Dn Against Bounds CLeaR CoMPare CoMPare Address CoMPare Immediate CoMPare Memory Looping Instruction Divide Signed Divide Unsigned Exclusive OR Exclusive OR Immediate Dn ILLEGAL Exchange any two registers on Sign EXTend <ea> ILLEGAL-Instruction Exception <ea> <ea>,An JuMP to Affective Address Jump to SubRoutine An, #<displacement> Load Effective Address Dx,Dy Allocate Stack Frame #<l-8>,Dy Logical Shift Left <ea> .. . Logical Shift Right <ea>,<ea> Between Effective Addresses To CCR <ea>,CCR To SR <ea>,SR

--L BWL

1 0 0 * * * * * * * * * * * - - * * 0 * * 0 * 0 0 * 0 0 - - * 0 0 - - - - - - - - - - * 0 *

BWL BWL -W-W-

* _ I I

* * 0 * * 0 0 I I I I I I I I

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