A VLSI IMPLEMENTATION OF PUNCTURED CONVOLUTIONAL CODES E. Garca, M. E. Guzmn, D. Torres egarcia@gdl.cinvestav.

mx CINVESTAV del IPN Unidad Guadalajara

ABSTRACT This paper presents a VLSI implementation of high punctured convolutional codes. Punctured versions of the rate-1/2, constraint length seven convolutional codes are considered. The present circuit was designed in order to complete a Viterbi decoder core, adding some extra functionality such as a convolutional encoder, differential encoder/decoder, and symbol insertion to depuncture the received data. Functional verification was done to ensure that the circuit implements intended functionality. Different bit error performance curves are shown. proposed architecture can handle other punctured patterns that may be programmed. The main goal of the present work is to provide an architecture that can handle ten different coding rates derived from the rate-1/2 convolutional encoder, the puncture of one symbol per clock cycle and to be fully programmable 2. REQUIREMENT SPECIFICATION The requirements for the punctured convolutional encoders, which we are interested in, are: 1. 2. 3. 4. 5. Rate-1/2, K=7 convolutional code Differential encoder/decoder Punctured codes for the following rates: 2/3, 3/4, 4/5, 5/6, 6/7, 7/8, 11/12, 12/13, 15/16 and 16/17. A programmable punctured pattern capability. Punctured convolutional decoder. 3. ARCHITECTURE The architecture is described in this section. Figure 1 shows the general encoder scheme. All blocks were implemented in VHDL.

1. INTRODUCTION Rate- convolutional coders have been widely used in many communication systems due to their moderate complexity and acceptable coding gain [1]. However, in many cases, it is desirable to be more flexible because the data to transmit over a channel needs different error protection since the channel can be time variant or the parameters of the channel are unknown. Consequently, flexible channel encoding is required. Given the availability of hardware to encode and decode this rate-, it is desirable to obtain high rate codes derived from the rate- coder. A technique known as puncturing provides a way to do this [2]. Puncturing means that some symbols of a code are deleted and they are not transmitted. For example, to obtain a rate-3/4 from a rate-1/2 it is necessary to periodically delete two out of six bits [3] produced by the convolutional encoder. However, it is necessary to have a proper pattern to delete such symbols in a proper way since puncturing reduces the minimum distance of a code [4]. The search of good punctured codes is often based in trial and error instead of a mathematical construction [2]. However, extensive research has been done in the past years and the literature shows good punctured patterns for sequential and Viterbi decoding [4] [10]. In this work, the punctured patterns proposed by Y. Yasuda et al. [4] are used. However, the

Data input Differential encoder Coded data Convolutional encoder Punctured encoder

Figure 1 Architecture 3.1. Differential encoder

In a typical M-ary PSK system, there is no absolute phase reference, so phase ambiguities in the modulated data may occur. The phase ambiguities must be resolved in order to properly decode the received data [6]. A differential encoder provides this function. The differential encoder transforms the input data stream into an indication of transitions rather than ones or zeros. This is, if a zero is input to the differential encoder the output remains the same, but if a one is input into the encoder the output will be a transition from zero to one or one to zero. Figure 2 shows the differential encoding process.

Figure 4. Convolutional encoder 3.3. Punctured convolutional encoder (PCE) The punctured convolutional coding is a good technique to obtain different rates derived from a rate-1/2 convolutional coder as stated in section 1. Figure 5 shows the architecture of the punctured encoder.

Figure 2. Differential encoding A one-bit delay and a modulo-2 adder as shown in Figure 3 build the differential encoder.
Mod-2 adder +

U0 U1

Memory

MUX

Symbol_1

Address
Punctured pattern Memory Address Counter Set

Symbol_2

Input data

Coded output

Counter

Set

D
One bit delay

Figure 3. Differential encoder 3.2. Convolutional Encoder The convolutional coding is one of the two major types of channel coding. Convolutional coding adds structured redundancy to a data sequence [7]. A convolutional encoder consists of a K-stage shift register, into which input data is clocked, and various modulo-2 adders connected to the stages of the shift register according to a chosen polynomial. The K value is known as the constraint length of the code. The code rate of the convolutional encoder is given as a fraction q/n, where q tells how many input data bits are shifted into the register per clock cycle while n is the number of coded symbols per input data bits. The Figure 4 shows the convolutional encoder. In this work, a K=7, rate-1/2, (113o, 155o) encoder was used. It was implemented in VHDL as a state machine.
U0
WRITE

Control

PATTERN RATE

Figure 5. Punctured convolutional encoder The architecture assumes two different clock sources: One is from the input data stream and the other clock source is a frequency division depending on the desired rate. For example if a rate-3/4 is desired, six encoded bits (three U0 and U1 pairs) are generated by the convolutional encoder for every three input data bits. These encoded bits are output from the U0 and U1 pins at 2/3 the frequency of the data input stream. The PCE implemented in this work uses a 32-bit memory to store the coded data that the rate-1/2 convolutional encoder provides (U0 and U1 in Figure 5). A counter provides the address of the memory. The counter is incremented each input data clock cycle. In order to delete the required

U1

symbols, the memory shall have 2xP stored symbols, where P is the period of the punctured pattern. For example, if a rate-3/4 is desired, the memory will store 12 bits (2x3=6 pairs of U0 and U1). Then, a MUX is needed to choose which symbols will be deleted according to the punctured pattern provided by the user. The punctured pattern provided by the user is stored in a memory. There are two ways to input the punctured pattern: One is to provide a desired rate via the RATE pin in Figure 5, i.e. 3/4, and the circuit will choose the appropriate pattern; the other way is to input a specific sequence of bits that represents the desired punctured pattern. These bits shall be input via the PATTERN pin shown in Figure 5. Depending on the desired rate, the control block shown in Figure 5 will set the appropriate address of the punctured pattern address as well as the needed configuration of the MUX and the blocks that compose the encoder. 3.4. Decoding A code must be decodable in order to be useful. There are different ways to decode a convolutional code: sequential, feedback, Fano [6], but there is an optimum decoder, known as Viterbi decoding algorithm [8]. This algorithm is optimum in the maximum likelihood sense. The Viterbi algorithm increases its complexity in an exponential way when the coding rate is increased. However, the puncturing technique allows the use of the rate-1/2 Viterbi decoding. In order to be decodable by the Viterbi algorithm, the punctured bits are replaced with dummy data [2] at the receiver. In Figure 6, the structure of the decoder is shown.

into the positions corresponding to the deleted code symbols at the transmitter. This dummy data is, in general, a weak one or a weak zero. The symbol insertion is shown in Figure 7.
PATTERN

Clk

start

Counter enabler

Control Unit

address

enabler

Symbol insertion C1 Memory MUX

I
C2

Figure 7. Symbol insertion As was stated before, the symbol insertion is the inverse operation of puncturing, so it works the same as the encoder with some brief modifications: ? ? The architecture assumes a QPSK modulation. ? ? Viterbi soft decision decoding. As in the punctured encoder, the symbols shall be stored in the memory, where the address of it is provided by a counter that increases its count every rate clock cycle. The control unit block provides the proper configuration of the blocks to perform the symbol insertion according to the punctured pattern used at the transmitter. 3.6. Differential decoding The differential decoder is shown in Figure 8. As it can be seen, it is the inverse of the diagram shown in Figure 3.
Mod-2 adder + Coded Input Decoded data

Symbol insertion

Viterbi Decoder

Diferential decoder

Figure 6. Decoder The Viterbi block shown in Figure 6 was not implemented in this work. It was implemented by M. Bazdresch [9]. 3.5. Symbol Insertion The symbol insertion is the inverse function of puncturing. Its main purpose is to insert dummy data

D
One bit delay

Figure 8. Differential decoder

4. VERIFICATION Functional verification was performed in order to ensure that the design implements intended functionality. Different kinds of stimulus were used: AA, 55, and pseudorandom data sequences were produced. All the configurations were tested and the results are shown in the next section. Behavioral models of a QPSK modulator, an AWGN channel and a QPSK demodulator were implemented in VHDL for verification purposes. The entire test was self-checking. 5. RESULTS The results obtained in the simulations are shown in Figure 9, Figure 10 and Figure 11. As can be seen in the figures, the results are close to the theoretical curves [2][4]. The design was simulated and synthesized using Synopsys. The synthesis results show that the design presented in this paper uses less than 5k logic gates and less than 16Kbits of memory. A complete top level of the design includes: Convolutional encoder, differential encoder, punctured convolutional encoder, symbol insertion, Viterbi decoder [9] and BER monitor. The top level uses less than 115k gates.

Error probability for a rate R=3/4 Theoretical Curve 10

-1

Simulation 10
-2

10 Pb 10

-3

-4

10

-5

10

-6

10

-7

3 Eb/N o

Figure 10- Bit error performance of rate-3/4

10
-1

Error Probability for a rate R=2/3

Error probability for a rate R=4/5

Theoretical Curve 10
-2

Theoretical Curve

Simulation 10
-3

Simulation 10
-2

-4 Pb10

Pb10

-4

10

-5

10

-6

10

-6

10

-7

0.5

1.5

2.5 Eb/N o

3.5

4.5

5
10
-8

3 Eb/N o

Figure 9. Bit error performance of rate-2/3

Figure 11. Bit error performance of rate-4/5

[6]

6. CONCLUSION A fully programmable device was obtained with the following features: ?? 10 programmable coding rates derived from the rate-1/2 convolutional coder. The rates are the following: 2/3, 3/4, 4/5, 5/6, 6/7, 7/8, 11/12, 12/13, 15/16. Rate-1/2, K=7 convolutional coder Differential encoder/decoder Symbol insertion (depuncturing) Symbol Encoding/Decoding per clock cycle Reasonable amount of logic gates

Proakis J.G "Digital Communications", Mc Graw Hill. [7] Forney G.D Jr., "Convolutional Codes I: Algebraic Structure", IEEE Trans. on Information Theory, Vol IT-16, No. 6, November 1970, pp. 720-738, and Vol. IT-17, No. 3, May 1971, pp 360. [8] Forney G.D Jr., The Viterbi Algorithm, IEEE Proceedings, IT-61(3), pp:268-273, March 1973. [9] Bazdresch L.M "A VLSI Implementation of the Viterbi Algorithm", CINVESTAV Unidad Guadalajara, Mexico July 2000. [10] Lee P, Construction of Rate (n-1)/n Punctured Convolutional Codes with Minimum Requiered SNR Criterion, IEEE Trans. Comunications, vol. 36, No 10. pp 1171- 1174. October 1988.

?? ?? ?? ?? ??

The BER performance curves were close to the theoretical curves in each of the rates tested, there was not improvement in the coding gain. The design can be implemented in a FPGA or in an ASIC. The speed of the design can vary depending on the technology (ASIC or FPGA). 7. REFERENCES [1] Stephen G. Wilson. Digital Modulation and Coding, Prentice Hall , Englewood Cliff, New Jersey,1996. Haccoun D. and Begin G. "High-Rate Punctured Convolutional Codes for Viterbi and Secuential Decoding", IEEE Trans. Communications, vol 37, No 11, pp. 1113-1125, November 1989. Lee C. "Convolutional Coding: Fundamentals and Applications", Artech House, INC, Norwood, MA 1997. J.B Cain, G.C. Clark, and J.Geist, "Punctured Convolutional Codes of Rate (n-1)/n and simplified maximum likelihood decoding." IEEE Trans. Inform. Theory, vol. IT-25, pp. 97-100, Jan. 1979. Yasuda, Y., Kashiki, K., and Hirata, Y., HighRate Punctured Convolutional Codes for Soft Decision Viterbi Decoding, IEEE Trans. Communications, vol. COM-32, pp. 315-319, March 1984.

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