Terence Zarb B.Sc. (Hons.) ICT in CCE Supervisor: Dr.

Ivan Grech

Design of various digital signal processing and communication blocks which form an integral part of a typical L1-band C/A-code GPS receiver
Using synthesisable VHDL code

Design of a GPS satellite signal modulation model Noise performance analysis of the designed baseband processor

The digital baseband modules are implemented on an FPGA

Benefits of an FPGA over the ASIC approach:
Re-programmability Increased flexibility in the implementation by updating functionality of the system after manufacturing Prototyping the implementation of system with minimum costs Low NRE costs

GPS main segments

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GPS uses spread-spectrum communication (CDMA) for communication between space and user segments Satellites transmit on the same frequency
two separate RF carriers are used (L1 and L2)

Each satellite is assigned a unique PRN code

three different codes: C/A-code, P-code, Y-code

Each satellites navigation message is modulated by the satellites PRN code and the resulting digital signal BPSK modulates the carrier wave

A GPS receiver is made up of 3 main parts:

Analogue front-end chip Digital baseband processor Dedicated CPU

The baseband processor is responsible for demodulation of navigation data coming from different satellites
Demodulation involves acquisition and tracking

Acquisition:
Generate local replica of incoming signal:
carrier replica + C/A-code replica

Synchronise the local and incoming signals

determine the code phase and carrier Doppler frequency

Down convert the incoming signal to baseband and cross-correlate the result with the local C/A-codes

Tracking phase starts after a satellite signal is acquired

Responsible for maintaining lock between local and incoming signals Carrier tracking loop using a Phase-Locked Loop (PLL) Code tracking loop using a Delay-Locked Loop (DLL)

Baseband Processing
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Assumptions:
Perfect carrier phase recovery GPS signals are not affected by Doppler Effect

The baseband processor hardware modules are designed using synthesisable VHDL code

The GPS satellite signal modulation model is designed using MATLAB Simulink

System Design
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Carrier Generator:
Front-end chip used is the GP2015 which down converts the L1 frequency to 4.309 MHz IF IF bandwidth = 2.046 MHz; fS = 5.102 MHz Aliasing occurs and the IF frequency is further down converted to 793 kHz Local carrier = 2.4 sin (2(793k)t)

Carrier Quantisation
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Carrier Samples:

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Baseband Mixer:
Mixes incoming 2-bit digitised IF signal with local carrier Each baseband sample requires 3-bit to be represented

2-bit combinations of digitised IF 3-bit combinations of baseband mixed signal

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C/A-Code Generator:
Generates the C/A-codes of all 24 satellites in parallel at a rate of 1.023 MHz

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Four-channel Parallel Correlator:

Correlates the baseband signal with the local C/A-codes of four satellites simultaneously Corr() =b(n)c(n ); 01022
1023-bit shift register C/A-Code Generator 1.023 MHz clock D Q D Q D Q D Q D Q

Baseband Signal

S0

S1

S2

S3

S1022

One-Channel Parallel Correlator

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Comparator:
Selects four satellites for data demodulation and determines their correct code phase delays Controls which four satellites are processed simultaneously by the correlator Accumulation interval = 2 ms

Navigation Data Demodulator:

Determination of navigation data bits

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Satellite Signal Modulation Model

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The correct functionality of each module was verified through various simulations
VHDL modules were tested using ModelSim Satellite signal modulation model was tested using MATLAB Simulink Simulation tool

Evaluation setup:
Bottom-up approach Tests for one satellite transmission Tests for multiple satellite transmissions Analyse noise performance of baseband processor

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BPSK IF Signal generation for one satellite:

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Correlation results for one satellite (SV 0) transmission:

Auto-Correlation of SV 0 C/A-Code
5000

4000

3000

Correlation Value

2000

1000

0 38 75

-1000

Code Phase Delay (in Chips)

1000

630

112

149

186

223

260

297

334

371

408

445

482

519

556

593

667

704

741

778

815

852

889

926

963

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Correlation results for one satellite (SV 0) transmission:

Cross-Correlation for the Baseband Samples and SV 2 C/A-Code
5000 4000 3000

Correlation
Value

2000 1000 0 37 73 1 -1000 1009

325

649

109

145

181

217

253

289

361

397

433

469

505

541

577

613

685

721

757

793

829

865

901

937

Code Phase Delay (in Chips)

973

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Results for multiple satellite transmissions:

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Noise Performance:

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Noise Performance:

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FPGA used: Xilinx Spartan-3E

Module
Baseband Mixer and Carrier Generator C/A-code Generator Correlator Comparator

X3S500E

Modules are synthesised using Xilinx ISE v. 11.1

Inferred Hardware
1 13-bit up counter 1 13-bit Comparator 1 2-input XOR gate 1 6-input XOR gate 8,188 comparators 62 comparators 4,105 registers (61,403 D-type flip-flops) 1,062 registers (14,759 D-type flip-flops) 1 10-bit up counter 5 multiplexors 51022 bits LUT

5 registers (21 D-type flip-flops)

4,093 adders/subtractors 8 adders /subtractors

Navigation Data Demodulator

1 6-bit register (6 flip-flops)

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Correlation between incoming and local codes is reduced when:

Number of parallel transmissions is increased SNR is reduced

Minimum SNR value that processor can tolerate is -10 dB when gain control is adopted The front-end AGC is crucial in the performance of the baseband processor

If no gain control is adopted, minimum SNR that the receiver can tolerate is greater than -10 dB

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Carrier Synchronisation

Doppler Shift Compensation

In-phase and quadrature components of the local replica to preserve phase information

Clock signals generation

Additional functionalities:
Low-power modes Re-acquisition techniques

Interfacing the FPGA-based processor with the analogue front-end module

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