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PROFET BTS 728 L2 Smart High-Side Power Switch Two Channels: 2 x 60m Status Feedback

Product Summary
Operating Voltage Vbb(on) Active channels On-state Resistance RON Nominal load current IL(NOM) Current limitation IL(SCr) 4.75...41V one two parallel 60m 30m 4.0A 6.0A 17A 17A

Package
P-DSO-20-9

General Description
N channel vertical power MOSFET with charge pump, ground referenced CMOS compatible input and diagnostic feedback, monolithically integrated in Smart SIPMOS technology. Providing embedded protective functions

Applications
C compatible high-side power switch with diagnostic feedback for 5V, 12V and 24V grounded loads All types of resistive, inductive and capacitve loads Most suitable for loads with high inrush currents, so as lamps Replaces electromechanical relays, fuses and discrete circuits

Basic Functions
Very low standby current CMOS compatible input Improved electromagnetic compatibility (EMC) Fast demagnetization of inductive loads Stable behaviour at undervoltage Wide operating voltage range Logic ground independent from load ground

Protection Functions
Short circuit protection Overload protection Current limitation Thermal shutdown Overvoltage protection (including load dump) with external resistor Reverse battery protection with external resistor Loss of ground and loss of Vbb protection Electrostatic discharge protection (ESD)

Block Diagram
Vbb

IN1 ST1

Logic Channel 1 Logic Channel 2 PROFET GND

OUT 1 Load 1 OUT 2 Load 2

IN2 ST2

Diagnostic Function
Diagnostic feedback with open drain output Open load detection in ON-state Feedback of thermal shutdown in ON-state

Semiconductor Group

1 of 14

2003-Oct-01

BTS 728 L2

Functional diagram
overvoltage protection

internal voltage supply

logic

gate control + charge pump

current limit

VBB

clamp for inductive load OUT1

IN1 ESD ST1 GND1

temperature sensor Open load detection LOAD

Channel 1

IN2 ST2 GND2

Control and protection circuit of channel 2 OUT2

PROFET

Pin configuration Pin Definitions and Functions


(top view)

Pin 1,10, 11,12, 15,16, 19,20 3 7 17,18 13,14 4 8 2 6 5,9

Symbol Function Vbb Positive power supply voltage. Design the wiring for the simultaneous max. short circuit currents from channel 1 to 2 and also for low thermal resistance IN1 Input 1,2, activates channel 1,2 in case of IN2 logic high signal OUT1 Output 1,2, protected high-side power output OUT2 of channel 1,2. Design the wiring for the max. short circuit current ST1 Diagnostic feedback 1,2 of channel 1,2, ST2 open drain, low on failure GND1 Ground 1 of chip 1 (channel 1) GND2 Ground 2 of chip 2 (channel 2) N.C. Not Connected

Vbb GND1 IN1 ST1 N.C. GND2 IN2 ST2 N.C. Vbb

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

Vbb Vbb OUT1 OUT1 Vbb Vbb OUT2 OUT2 Vbb Vbb

Semiconductor Group

2003-Oct-01

BTS 728 L2 Maximum Ratings at Tj = 25C unless otherwise specified


Parameter Supply voltage (overvoltage protection see page 4) Supply voltage for full short circuit protection Tj,start = -40 ...+150C Load current (Short-circuit current, see page 5) Load dump protection1) VLoadDump = VA + Vs, VA = 13.5 V RI2) = 2 , td = 200 ms; IN = low or high, each channel loaded with RL = 8.0 , Operating temperature range Storage temperature range Power dissipation (DC)4) Ta = 25C: Ta = 85C: (all channels active) Maximal switchable inductance, single pulse Vbb = 12V, Tj,start = 150C4), IL = 4.0 A, EAS = 220 mJ, 0 one channel: IL = 6.0 A, EAS = 540 mJ, 0 two parallel channels:
see diagrams on page 9

Symbol Vbb Vbb IL VLoad dump3) Tj Tstg Ptot

Values 43 24 self-limited 60 -40 ...+150 -55 ...+150 3.7 1.9

Unit V V A V C W

ZL

19.9 22.3 1.0 4.0 8.0 -10 ... +16 2.0 5.0

mH

Electrostatic discharge capability (ESD) IN: (Human Body Model) ST: out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993 R=1.5k; C=100pF

VESD

kV

Input voltage (DC) Current through input pin (DC) Current through status pin (DC)
see internal circuit diagram page 8

VIN IIN IST

V mA

Thermal Characteristics
Parameter and Conditions Symbol min Thermal resistance junction - soldering point4),5) each channel: Rthjs 4) junction - ambient one channel active: Rthja all channels active:
1) 2) 3) 4) 5)

Values typ Max -41 34 13.5 ---

Unit

----

K/W

Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150 resistor for the GND connection is recommended. RI = internal resistance of the load dump test pulse generator VLoad dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839 Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70m thick) copper area for Vbb connection. PCB is vertical without blown air. See page 14 Soldering point: upper side of solder edge of device pin 15. See page 14

Semiconductor Group

2003-Oct-01

BTS 728 L2 Electrical Characteristics


Parameter and Conditions, each of the two channels
at Tj = -40...+150C, Vbb = 12 V unless otherwise specified

Symbol

Values min typ Max

Unit

Load Switching Capabilities and Characteristics On-state resistance (Vbb to OUT); IL = 2 A, Vbb 7V each channel, Tj = 25C: RON Tj = 150C: two parallel channels, Tj = 25C:
see diagram, page 10

--

50 100 25

60 120 30 --

Nominal load current

one channel active: IL(NOM) two parallel channels active:

3.6 5.5 -30 30 0.15 0.15 0.15 0.15 4.75 41 43 ----

4.0 6.0 -100 100 -------47 10 -1

Device on PCB6), Ta = 85C, Tj 150C

Output current while GND disconnected or pulled up7); IL(GNDhigh)


Vbb = 30 V, VIN = 0, see diagram page 8 Turn-on time8) IN

2 200 200 1 0.8 1 0.8 41 43 -52 18 50 10

mA s

Turn-off time IN RL = 12 Slew rate on 8) Tj = -40C: dV/dton 10 to 30% VOUT, RL = 12 Tj = 25C...150C: Slew rate off 8) Tj = -40C: -dV/dtoff 70 to 40% VOUT, RL = 12 Tj = 25C...150C: Operating Parameters Operating voltage Tj=-40 Tj=25...150C: 9) Overvoltage protection Tj =-40C: Tj =25...150C: I bb = 40 mA ) Standby current10 Tj =-40C...25C: Tj =150C: VIN = 0; see diagram page 10 Leakage output current (included in Ibb(off)) VIN = 0 Operating current 11), VIN = 5V, IGND = IGND1 + IGND2, one channel on: two channels on:
6)

to 90% VOUT: ton to 10% VOUT: toff

V/s V/s

Vbb(on) Vbb(AZ) Ibb(off) IL(off)

V V A A

IGND

---

0.8 1.6

1.5 3.0

mA

Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70m thick) copper area for Vbb connection. PCB is vertical without blown air. See page 14 7) not subject to production test, specified by design 8) See timing diagram on page 11. 9) Supply voltages higher than V bb(AZ) require an external current limit for the GND and status pins (a 150 resistor for the GND connection is recommended). See also VON(CL) in table of protection functions and circuit diagram on page 8. 10) Measured with load; for the whole device; all channels off 11) Add I , if I ST ST > 0

Semiconductor Group

2003-Oct-01

BTS 728 L2
Parameter and Conditions, each of the two channels
at Tj = -40...+150C, Vbb = 12 V unless otherwise specified

Symbol

Values min typ Max

Unit

Protection Functions12) Current limit, (see timing diagrams, page 12) Tj =-40C: IL(lim) Tj =25C: Tj =+150C: Repetitive short circuit current limit, Tj = Tjt each channel IL(SCr) two parallel channels
(see timing diagrams, page 12)

21 17 12 ----

28 22 16 17 17 2.4

36 31 24 ----

Initial short circuit shutdown time

Tj,start =25C: toff(SC)

ms V

(see timing diagrams on page 12)

Output clamp (inductive load switch off)13) at VON(CL) = Vbb - VOUT, IL= 40 mA Tj =-40C: VON(CL) Tj =25C...150C: Thermal overload trip temperature Tjt Thermal hysteresis Tjt Reverse Battery Reverse battery voltage 14) Drain-source diode voltage (Vout > Vbb) IL = - 4.0 A, Tj = +150C

41 43 150 --

-47 -10

-52 ---

C K

-Vbb -VON

---

-600

32 --

V mV

12)

Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. 13) If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest VON(CL) 14) Requires a 150 resistor in GND connection. The reverse load current through the intrinsic drain-source diode has to be limited by the connected load. Power dissipation is higher compared to normal operating conditions due to the voltage drop across the drain-source diode. The temperature protection is not active during reverse current operation! Input and Status currents have to be limited (see max. ratings page 3 and circuit page 8).

Semiconductor Group

2003-Oct-01

BTS 728 L2
Parameter and Conditions, each of the two channels
at Tj = -40...+150C, Vbb = 12 V unless otherwise specified

Symbol

Values min typ Max

Unit

Diagnostic Characteristics Open load detection current, (on-condition) each channel I L (OL) Input and Status Feedback15) Input resistance
(see circuit page 8)

10

--

500

mA

RI VIN(T+) VIN(T-) VIN(T) IIN(off) IIN(on) td(ST OL4) td(ST)

2.5 1.7 1.5 -1 20 100 --

3.5 --0.5 -50 520 --

6 3.2 --50 90 900 500

k V V V A A s s

Input turn-on threshold voltage Input turn-off threshold voltage Input threshold hysteresis Off state input current VIN = 0.4 V: On state input current VIN = 5 V: Delay time for status with open load after switch off; (see diagram on page 13) Status invalid after positive input slope (open load) Status output (open drain) Zener limit voltage IST = +1.6 mA: ST low voltage IST = +1.6 mA:

VST(high) VST(low)

5.4 --

6.1 --

-0.4

15)

If ground resistors RGND are used, add the voltage drop across these resistors.

Semiconductor Group

2003-Oct-01

BTS 728 L2 Truth Table


Channel 1 Channel 2 Input 1 Input 2 level Normal operation Open load Overtemperature L = "Low" Level H = "High" Level L H L H L H Output 1 Output 2 level L H Z H L L Status 1 Status 2
BTS 728L2

H H H L H L

X = don't care Z = high impedance, potential depends on external circuit Status signal valid after the time delay shown in the timing diagrams

Parallel switching of channel 1 and 2 is easily possible by connecting the inputs and outputs in parallel. The status outputs ST1 and ST2 have to be configured as a 'Wired OR' function with a single pull-up resistor.

Terms
V Ibb bb I IN1 3 I ST1 V IN1 V ST1 4 ST1 IN1 Leadframe Vbb I L1 PROFET Chip 1 GND1 2 R GND1 IGND1 V OUT1 OUT1 17,18 V VON1 I ST2 IN2 V ST2 8 ST2 I IN2 7 IN2 Leadframe Vbb I L2 PROFET Chip 2 GND2 6 R GND2 IGND2 V OUT2 OUT2 13,14 VON2

Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20 External RGND optional; two resistors RGND1, RGND2 = 150 or a single resistor RGND = 75 for reverse battery protection up to the max. operating voltage.

Semiconductor Group

2003-Oct-01

BTS 728 L2
Input circuit (ESD protection), IN1 or IN2
R IN I

Overvolt. and reverse batt. protection


+ 5V + Vbb V IN

R ST RI Logic R ST ST
V Z1

Z2

ESD-ZD I GND

OUT

PROFET
GND

The use of ESD zener diodes as voltage clamp at DC conditions is not recommended.

R GND
Signal GND

R Load

Load GND

Status output, ST1 or ST2


+5V

R ST(ON)

ST

VZ1 = 6.1 V typ., VZ2 = 47 V typ., RGND = 150 , RST= 15 k, RI= 3.5 k typ. In case of reverse battery the load current has to be limited by the load. Temperature protection is not active

GND

ESDZD

Open-load detection OUT1 or OUT2


ON-state diagnostic Open load, if VON < RONIL(OL); IN high
+ V bb

ESD-Zener diode: 6.1 V typ., max 5.0 mA; RST(ON) < 375 at 1.6 mA. The use of ESD zener diodes as voltage clamp at DC conditions is not recommended.

Inductive and overvoltage output clamp,


OUT1 or OUT2
+Vbb VZ V
Logic unit

ON

VON

OUT

Open load detection

ON

OUT

GND disconnect

Power GND

VON clamped to VON(CL) = 47 V typ.

IN

Vbb PROFET OUT

ST GND V bb V IN V ST V GND

Any kind of load. In case of IN = high is VOUT VIN - VIN(T+). Due to VGND > 0, no VST = low signal available.

Semiconductor Group

2003-Oct-01

BTS 728 L2
GND disconnect with GND pull up Inductive load switch-off energy dissipation
E bb
IN Vbb PROFET ST GND OUT

E AS Vbb PROFET OUT ELoad

IN

=
V V bb IN ST V V GND

ST GND ZL

{
R L

EL

ER

Any kind of load. If VGND > VIN - VIN(T+) device stays off Due to VGND > 0, no VST = low signal available.

Energy stored in load inductance:

Vbb disconnect with energized inductive load

EL = 1/2LI L While demagnetizing load inductance, the energy dissipated in PROFET is EAS= Ebb + EL - ER= VON(CL)iL(t) dt,

high

IN

Vbb PROFET OUT

with an approximate solution for RL > 0 : EAS= IL L (V + |VOUT(CL)|) 2RL bb

ST GND

ln (1+ |V

ILRL

OUT(CL)|

bb

Maximum allowable load inductance for a single switch off (one channel)4)
L = f (IL ); Tj,start = 150C, Vbb = 12 V, RL = 0 ZL [mH]
1000

For inductive load currents up to the limits defined by ZL (max. ratings and diagram on page 9) each switch is protected against loss of Vbb. Consider at your PCB layout that in the case of Vbb disconnection with energized inductive load all the load current flows through the GND connection.

100

10

1 2 3 4 5 6 7 8 9 10 11 12

IL [A]

Semiconductor Group

2003-Oct-01

BTS 728 L2
Typ. on-state resistance
RON = f (Vbb,Tj ); IL = 2 A, IN = high RON [mOhm] Ibb(off) [A]
45

Typ. standby current


Ibb(off) = f (Tj ); Vbb = 9...34 V, IN1,2 = low

125 Tj = 150C

40 35 30 25 20

100

75

50

25C -40C

15 10 5

25

0 3 5 7 9 30 40
Vbb [V]

0 -50 0 50 100 150 200

Tj [C]

Semiconductor Group

10

2003-Oct-01

BTS 728 L2

Timing diagrams
Both channels are symmetric and consequently the diagrams are valid for channel 1 and channel 2
Figure 1a: Vbb turn on: IN1 Figure 2b: Switching a lamp:

IN2
IN

V bb V
ST

OUT1

OUT2

OUT

ST1 open drain


I

ST2 open drain t

Figure 2a: Switching a resistive load, turn-on/off time and slew rate definition:

The initial peak current should be limited by the lamp and not by the current limit of the device.

IN

Figure 2c: Switching an inductive load


IN

VOUT
90% t on dV/dton 10% t dV/dtoff
ST

off

OUT

IL
I
L

I L(OL) t

Semiconductor Group

11

2003-Oct-01

BTS 728 L2
*) if the time constant of load is too large, open-load-status may occur

Figure 3a: Turn on into short circuit: shut down by overtemperature, restart by cooling
IN1 other channel: normal operation

Figure 4a: Overtemperature: Reset if Tj <Tjt


IN

ST
I
L1

L(lim) I L(SCr)

OUT

t ST

off(SC)

t
Heating up of the chip may require several milliseconds, depending on external conditions

Figure 3b: Turn on into short circuit: shut down by overtemperature, restart by cooling (two parallel switched channels 1 and 2)
IN1/2

Figure 5a: Open load: detection in ON-state, open load occurs in on-state
IN

L1

+I

L2

ST

t d(ST OL)

d(ST OL)

2xIL(lim)

V
I L(SCr)

OUT

I
t ST1/2 off(SC)

normal
L

open

normal

t
t
td(ST OL) = 10 s typ.

ST1 and ST2 have to be configured as a 'Wired OR' function ST1/2 with a single pull-up resistor.

Semiconductor Group

12

2003-Oct-01

BTS 728 L2
Figure 5b: Open load: turn on/off to open load

IN

ST

d(STOL4)

Semiconductor Group

13

2003-Oct-01

BTS 728 L2

Package and Ordering Code


Standard: P-DSO-20-9
Sales Code Ordering Code
All dimensions in millimetres

BTS 728 L2 Q67060-S7014-A2

Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81669 Mnchen Infineon Technologies AG 2001 All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Definition of soldering point with temperature Ts: upper side of solder edge of device pin 15.

Pin 15

Printed circuit board (FR4, 1.5mm thick, one layer 70m, 6cm2 active heatsink area) as a reference for max. power dissipation Ptot, nominal load current IL(NOM) and thermal resistance Rthja

Semiconductor Group

14

2003-Oct-01

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