Академический Документы
Профессиональный Документы
Культура Документы
Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London
Based on slides/material by
P. Cheung http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/index.html J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html Digital Integrated Circuits: A Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Addison Wesley
Lecture 2 - 2
Recommended Reading
J. Rabaey et. al. Digital Integrated Circuits: A Design Perspective: Chapter 2 (2.1 2.3), Chapter 3 (3.3) Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective: Chapter 2, Chapter 3 (3.2), Chapter 5.
Lecture 2 - 3
Outline
MOS transistors SPICE simulation CMOS fabrication process Layout rules
Lecture 2 - 4
MOS Transistor
Shown here is the cross-section of an n-channel enhancement transistor: Substrate is moderately doped with p-type material. Substrate in digital circuit is usually connected to VGnd (ground). The source and drain regions are heavily doped with n-type material through diffusion. These are often referred to as the diffusion regions.
Lecture 2 - 5
Lecture 2 - 6
Lecture 2 - 7
G S
NMOS Enhancement
NMOS Depletion
S
PMOS Enhancement
S
G S
Lecture 2 - 8
S -
+ V GS G
n+
n+
n-channel p-substrate B
Depletion Region
Lecture 2 - 9
Lecture 2 - 10
Lecture 2 - 11
Lecture 2 - 12
Current-Voltage Relations
V GS G
V DS D n+ L x ID
n+
V(x)
p-substrate B
Current-Voltage Relations
Lecture 2 - 14
Transistor in Saturation
VG S V DS > VGS - V T D
G S n+
-
VG S - VT
n+
Lecture 2 - 15
Lecture 2 - 16
I-V Relation
Lecture 2 - 17
Lecture 2 - 18
CGS S
CGD D
CSB
CGB
CDB
B
MOS Theory, SPICE, Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 - 19
Lecture 2 - 20
Lecture 2 - 21
Lecture 2 - 22
Threshold Variations
L Threshold as a function of the length (for low VDS) Drain-induced barrier lowering (for low L)
Lecture 2 - 23
Parasitic Resistances
Lecture 2 - 24
Lecture 2 - 25
1.5 VGS = 5 1.0 I D (mA) VGS = 4 VGS = 3 0.5 VGS = 2 VGS = 1 0.0 1.0 2.0 3.0 VDS (V) 4.0 5.0
Linea r Dependence
0.5
ID (mA) 0 0.0
3.0
(a) I D as a function of V DS
Sub-Threshold Conduction
102 104 ln(ID) (A) 106 108 1010 1012 0.0 Subthreshold exponential region Linear region
VT 1.0
3.0
Lecture 2 - 27
Lecture 2 - 28
Outline
MOS transistors SPICE simulation CMOS fabrication process Layout rules
Lecture 2 - 30
Resistors, Capacitors, Inductors Independent sources (V, I), Dependent sources (V, I) Transmission lines Active devices (diodes, BJTs, JFETS, MOSFETS) non-linear d.c. non-linear transient linear a.c. Noise & temperature
Introduction to Digital Integrated Circuit Design Lecture 2 - 31
You can use SPICE to perform the following types circuit analysis:
SPICE MODELS
Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Em perical - Simple and Popular
Lecture 2 - 32
Lecture 2 - 33
Lecture 2 - 34
Lecture 2 - 35
V GS = 5 V
Long-channel approximation V DS = 5 V V DS
Lecture 2 - 36
Technology Evolution
VDD decreases
Save dynamic power Protect thin gate oxides and short channels No point in high value because of velocity sat.
Vt must decrease to maintain device performance But this causes exponential increase in OFF leakage Major future challenge
Lecture 2 - 37
Outline
MOS transistors SPICE simulation CMOS fabrication process Layout rules
Lecture 2 - 38
CMOS Fabrication
CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
Lecture 2 - 39
Inverter Cross-section
Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
Vi Qn VDD
Qp Vo
A GND Y VDD SiO2 n+ diffusion n+ n+ p substrate nMOS transistor pMOS transistor p+ n well p+ p+ diffusion polysilicon metal1
Lecture 2 - 40
p+
n+
n+ p substrate
p+ n well
p+
n+
substrate tap
MOS Theory, SPICE, Fabrication Introduction to Digital Integrated Circuit Design
well tap
Lecture 2 - 41
n well
Polysilicon
n+ Diffusion
p+ Diffusion
Contact
Metal
Lecture 2 - 43
Fabrication Steps
Start with blank wafer Build inverter from the bottom up First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2
p substrate
Lecture 2 - 44
Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
Lecture 2 - 45
Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer Softens where exposed to light
Photoresist SiO2
p substrate
Lecture 2 - 46
Lithography
Expose photoresist through n-well mask Strip off exposed photoresist
Photoresist SiO2
p substrate
Lecture 2 - 47
Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Photoresist SiO2
p substrate
Lecture 2 - 48
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
SiO2
p substrate
Lecture 2 - 49
n-well
n-well is formed with diffusion or ion implantation Diffusion
Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si
Ion Implantation
Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si
SiO2 n well
Lecture 2 - 50
Strip Oxide
Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps
n well p substrate
Lecture 2 - 51
Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Lecture 2 - 52
Polysilicon Patterning
Use same lithography process to pattern polysilicon
Polysilicon
Lecture 2 - 53
Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact
n well p substrate
Lecture 2 - 54
N-diffusion
Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing
n+ Diffusion
n well p substrate
Lecture 2 - 55
N-diffusion cont.
Historically dopants were diffused Usually ion implantation today But regions are still called diffusion
n+
n+ n well p substrate
n+
Lecture 2 - 56
N-diffusion cont.
Strip off oxide to complete patterning step
n+
n+ n well p substrate
n+
Lecture 2 - 57
P-diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+ p substrate
p+ n well
p+
n+
Lecture 2 - 58
Contacts
Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed
Contact
Lecture 2 - 59
Metalization
Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires
M e ta l
Lecture 2 - 60
Outline
MOS transistors SPICE simulation CMOS fabrication process Layout rules
Lecture 2 - 61
Layout
Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of = f/2
E.g. = 0.3 m in 0.6 m process
Lecture 2 - 62
Design Rules
Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)
Lecture 2 - 63
Layer
Color
Representation
Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via
Lecture 2 - 64
Well
3
4
Lecture 2 - 65
Transistor Layout
Transistor
Lecture 2 - 66
2 2
Lecture 2 - 67
Select Layer
2 3 2 1 3 3 Select
Substrate
MOS Theory, SPICE, Fabrication Introduction to Digital Integrated Circuit Design
Well
Lecture 2 - 68
GND
In
VD D
A p-substrate n
+
A n p
+
Field Oxide
Summary
MOS transistor: majority carrier device building block of integrated circuits SPICE: popular circuit level simulator that applies nodal analysis of circuit CMOS transistors are fabricated on silicon wafer
Lithography process Different materials are deposited or etched in each step
Lecture 2 - 70