Axel Berny

EE240 Term Project

SPRING 2001



Outline:
1. Design Approach
2. Amplifier Schematic
3. Biasing Network Schematic
4. Performance Summary
5. Design Process and Equations
6. Simulation Plots:
a. Differential AC Loop Frequency Response
b. Common-Mode AC Loop Frequency Response
c. Open Loop Gain vs. Differential Output Voltage
d. Positive Settling
e. Negative Settling
f. Total Integrated Output Voltage Noise
7. Comments and Conclusion
8. Appendix
a. Circuit Netlist
b. Non-dominant Pole Optimization
c. Doublet Analysis



1. Design Approach
Choice of topology
Selecting an optimal topology for the given specifications is one of the most crucial design
steps since this is where the biggest difference can be made in terms of achievable performance.
It is also important in the sense that turning back may not be an option due to time constraints.
Thus, the first task at hand is to evaluate trade-offs among candidate topologies.
A quick back-of-the-envelope set of calculations tell us that our OTA needs a very high dc
gain (A
dc
) on the order of (g
m
r
o
)
3
and unity-gain bandwidth on the order of 900MHz. In addition,
meeting the specified dynamic range (DR) of 70dB using minimum power calls for a
combination of high output swing and small noise factor. A
dc
requirements narrow down our
possible choices to either 2-stage designs, or single-stage gain-boosted or triple-cascode designs.
The triple-cascode design is ruled out for several reasons. Though it appears capable of
achieving low-power (only two current legs), the only way to push the two non-dominant poles
for far enough for decent stability (and settling) is by increasing the bias current (and C
L

simultaneously). Although this is fine in terms of noise, it severely degrades the achievable dc
gain. Another major drawback is that its output range is the worst out of all candidates (on the
order of V
DD
7V
d
sat
~ 1.6V). Two-stage designs are attractive for several reasons. For one, they
are fairly easy to design and thus may be optimized more readily (say, compared to a gain-
boosted topology). Also, they can achieve very high swing (on the order of V
DD
2V
d
sat
~ 2.6V)
thus relaxing the required noise performance for the given DR. Perhaps the only drawback is that
a 2-stage design implies a minimum of four currents legs (all drawing comparable current) and
thus may not achieve the lowest power. On the other hand, a gain-boosted topology only has two
current legs that draw significant current and can easily achieve the required dc gain and
bandwidth. The only catch consists of insuring that the inherent doublet does not produce a slow-
settling (over-damped) component. Despite its additional complexities, the gain-boosted
topology is chosenmainly because it appears more power efficient.

Gain-Boosting Considerations
One of the first considerations to be made was choosing between a telescopic and a folded-
cascode configuration for the main amplifier. The folded-cascode provides high gain, high
PSRR/CMRR (for PMOS inputs), and slightly higher (by about V
d
sat
) output swing. However it
consumes typically twice the power as its telescopic cousin. But there are yet more severe
problems: 1) there is about twice the stray capacitance at the folding node, significantly
degrading stability; 2) the noise factor is quite larger (1.5-2 times) since the drain of the
transistor at the folding node runs the same current as the input device. The telescopic topology
is preferred for its overall higher power-efficiency. NMOS inputs are chosen in order to achieve
maximum Gm/Id. The tail current source is sized to provide a small V
d
sat
to allow for high
swing; its V
DS
is biased at roughly 1.5V
d
sat
to maintain reasonable output resistance. These
decisions are made on the basis that PSRR/CMRR do not need to be addressed for this project.
Practical implementations where this is a concern should cascode the tail current source and may
have to use source-to-bulk connected PMOS as input devices in order to reduce mismatches in
V
TH
.


2. Amplifier Schematics

Device W (m) L (m) I
D
(A) g
m
(mS) g
m
/I
D
(V
-1
)
M1a,b 230 0.35 325 6.20 19.0
M2a,b 80 0.35 325 4.89 15.0
M3a,b 35 0.35 325 2.29 7.0
M4a,b 30 0.35 325 1.68 5.2
M5a,b 130 0.35 325 5.17 15.9
MXia,b 30 0.35 30 0.457 15.2
MX1a,b 2 0.60 30 0.163 5.42
MX2a,b 7 0.60 30 0.339 11.3
MX3a,b,c 15 0.60 30 0.283 9.4
MX4a,b,c 5 0.60 30 0.155 5.2
MYia,b 20 0.35 25 0.524 21.0
MY1a,b 2.25 0.70 25 0.149 6.0
MY2a,b 7 0.70 25 0.285 11.4
MY3a,b,c 12 0.70 25 0.207 8.3
MY4a,b,c 6 0.70 25 0.144 5.8

Ccm Cxcm Cycm
20fF 30fF 30fF
Main Amplifier Schematic


P-Booster Schematic N-Booster Schematic

MY4a MY4b
MY3a
MY3b
MY2a MY2b
MY1a
MY1b
MYia MYib
MY2c
MY1c
Vyop
Cycm
Vyon
Cycm
MY1c
Vyop Vyon
Vya Vyb
Vyb4
Vyb3 Vyb3
Vyb2
Vyb1 Vyb1
MX4a MX4b
MX3a
MX3b
MX2a MX2b
MX1a MX1b
MXia MXib
MX3c
Vxop
Cxcm
Vxon
Cxcm
Vxb1
Vxb2
Vxb3
Vxb4
MX4c MX4c
Vxa Vxb Vxb2
Vxb4
m=2 m=2
m=2
m=2
m=2 m=2
Vxon Vxop
M4a M4b
M3a
M3b
M2a M2b
M1b M1a
M5a M5b
Von Vop
Vip
Vin
Vbp
Vbn
Vop
Von
Ccm
Ccm
Vss
Vdd
N-Booster
P-Booster
Vxb Vxa
Vya Vyb
Vxop Vxon
Vyon Vyop


3. Biasing Network Schematic
Ms1
Ms2
Ms3
Ms4
Mr1
Mr2
Mxa1
Mxa2
Mxa3
Mxa4
Mxb1
Mxb2
Mxb3
Mxb4
Mxc1
Mxc2
Mxc3
Mxc4
Mxd1
Mxd2
Mxd3
Mxd4
Mya1
Mya2
Mya3
Mya4
Myb1
Myb2
Myb3
Myb4
Myc1
Myc2
Myc3
Myc4
Myd1
Myd2
Myd3
Myd4
Ma1
Ma2
Mb1
Mb2
Ma3
Mb3
Mb4
Ma4
Ma4
Ma4
Mc3
Mc4
Md3
Md4
Mc2
Mc1
Mc1
Mc1
Md1
Md2
Iss
Vdd
Vss
Vxb3
Vxb4
Vxb1
Vxb2
Vyb3
Vyb4
Vyb1
Vyb2
Vbp
Vbn




Device W ( m) L ( m) I
D
( A) g
m
(mS) g
m
/I
D
(V
-1
)
Ma1, Mb1 15 (m=2) 1.0 50 0.660 13.2
Ma2, Mb2 15 (m=2) 1.0 50 0.671 13.4
Ma3 15 0.35 50 0.545 10.9
Mb3 5.4 0.35 50 0.329 6.6
Mb4 4.75 0.35 50 0.261 5.2
Md1 20 0.35 50 0.796 15.9
Mc2 15 0.35 50 0.807 16.1
Md2 38.5 0.35 50 0.981 19.6
Mc3, Md3 15 (m=2) 1.0 50 0.383 7.7
Mc4, Md4 15 (m=2) 1.0 50 0.382 7.7
Mxa1, Mxb1 18 1.0 30 0.392 13.1
Mxa2, Mxb2 18 1.0 30 0.403 13.4
Mxa3, Mxb3 15 0.6 30 0.281 9.4
Mxb4 5.0 0.6 30 0.155 5.2
Mxd1 2.0 0.6 30 0.163 5.4
Mxc2, Mxd2 7.0 0.6 30 0.340 11.3
Mxc3, Mxd3 18 1.0 30 0.227 7.6
Mxc4, Mxd4 18 1.0 30 0.230 7.7
Mya1, Myb1 15 1.0 25 0.327 13.1
Mya2, Myb2 15 1.0 25 0.335 13.4
Mya3, Myb3 12 0.7 25 0.207 8.3
Myb4 6.0 0.7 25 0.143 5.7
Myd1 2.25 0.7 25 0.149 6.0
Myc2, Myd2 15 0.35 25 0.279 11.2
Myc3, Myd3 15 1.0 25 0.191 7.6
Myc4, Myd4 15 1.0 25 0.191 7.6

Triode TXs Ma4 Mc1 Mxa4 Mxc1 Mya4 Myc1
W (um) 37.4 7.7 10 1.8 12 4.0
L (um) 5.0 5.0 3.0 3.0 5.0 10

top n-booster
bias network
bottom n-booster
bias network
bottom p-booster
bias network
bottom main amp
bias network
top p-booster
bias network
top main amp
bias network


4. Performance Summary

Simulated Performance
Parameter
NOMINAL SLOW FAST
Specification
Settling Time to 0.05% Accuracy (ns) 24.1 ns 25.0 ns 23.4 ns 25.0 ns
Differential Total Output Voltage Noise
Integrated to 100GHz ( V
rms
)
444 V
rms
447 V
rms
442 V
rms
-
Differential Peak Output Voltage (V) 2.0 V -
Dynamic Range (dB) 70.06 dB 70.00 dB 70.10 dB 70.0 dB
Amplifier Core Power Consumption (mW) 2.61 mW 2.63 mW 2.60 mW Minimize
Bias Network Power Consumption (mW) 1.41 mW 1.41 mW 1.40 mW -
Total Power Consumption (mW) 4.02 mW 4.04 mW 4.00 mW -
Open Loop DC Gain for Vod = 0V (dB) 113.2 dB 113.3 dB 112.4 dB -
Open Loop DC Gain for Vod = 2V (dB) 109.1 dB 108.7 dB 109.0 dB -
Differential AC Loop Gain (dB) 87.5 dB 88.6 dB 86.2 dB -
Differential AC Loop Unity Gain BW (MHz) 70.0 MHz 68.3 MHz 71.8 MHz -
Differential AC Loop Phase Margin (
o
) 86.6
o
86.9
o
86.4
o
-
Common-Mode AC Loop Gain (dB) 43.6 dB 43.4 dB 43.7 dB -
Common-Mode AC Loop Unity BW (MHz) 436 MHz 421 MHz 453.1 MHz -
Common-Mode AC Loop Phase Margin (
o
) 55.0
o
55.1
o
55.1
o
-


Simulation Setup




C
s
4.96pF
C
f
0.31pF
C
L
0.30pF
V
DD
3V











C
s
C
s
C
f
=C
s
/16
C
f
=C
s
/16
C
L
C
L
V
i
+
V
i
-
V
o
-
V
o
+
Id
min
76uA = (per branch)
Thus under the above (ideal) conditions, the absolute minimum power is about 456uW.
For a telescopic (gain-boosted) topology, we make the following assumptions:
Output Swing: Vo = 2Vpeak differential (maximum is Vdd - 5Vdsat)
DC Gain: Adc = 106dB over +/-2V output range (this is easily achieved using gain-boosting)
Feedback Factor: F = 1/18 (assuming Cs=Ci as a starting point)
One Pole Linear Settling:
1) No Slewing because for a closed-loop gain of 16, the maximum input step is only
125mV (typically less than or equal to Vdsat1)
2) Placing the doublet frequency in the safe range:
F
u

b

p2
[K. Bult and J.G.M. Geaelen]
where
u
is the unity gain bandwidth of the amplifier,
b
is the doublet frequency (also the
unity gain bandwidth of the booster amplier) and
p2
is the non-dominant pole of the main
amplifier formed at the source of the M2. Satisfying the above, the amplifier will show one-pole
linear settling as long as
p2
is placed sufficiently far away from F
u
(i.e.
m
60
o
).
Noise Considerations
Ignoring the noise due to the boosting amplifiers, the telescopic amplifier has noise given by:
Von
2 4
3
Kb T
CLt

1
F
1
gm4
gm1
+

,
= (CLt is the total effective output capacitance)
5. Design Process and Equations
In order to gain some insight on what power consumption one might expect for the given
specifications, we first consider an ideal case as shown below:
Iss
M1
Cf=Cs/16
Cs
Vi
Vo
C
L
F
min
1
17
= CL
min
0.3pF =
Von
2 2
3
Kb T
CL

1
F
min
= 156.5
nV
2
Hz
=
Peak swing: Vo
VDD
2
Vdsat =
so: Vo 1.5 0.1 = 1.4V =
(single-ended equivalent)
thus: DR
1
2
1.4
2

2
3
Kb T
CL

1
F
min

= 70.33dB =
Hence in this ideal case, CL is not noise-limited.
With = 0.05% (since infinite gain), we have:
fu
min
1
2
ln ( )
1
F
min
t
s

= 805MHz = Thus: Gm
min
u
min
CL
min
= 1.52mS =
If we assume maximum Gm/Id ~ 20, then:
M2-M3: M2 and M3 are sized to achieve a good compromise between low Vdsat (for high swing of
about +/-2V) and high
p2
. Their noise can be safely neglected. Hence they are sized so that the
non-dominant pole created at their source is optimally pushed far out. Doing so yields a Vdsat that is
sufficiently low for swing considerations. This is achieved once the total gate capacitance of the
cascode device is made approximately (exactly if ideal square law) equal to the parasitic capacitance
at the source node. A derivation is included in Appendix (b). We obtain:
gm
2
~ 2*gm
3
~ 5mS
M1: M1 is stricly sized in terms of Gm/Id based on requirements identified above. Since Gm/Id is made
purposely very large (~20; limited by velocity saturation) to achieve high power efficiency, Vdsat1 is
correspondingly low (~0.1V assuming square law) and thus M1 limits the output swing only marginally.
Device Sizing Considerations
But this is very optimistic and the actual current required
in the design is 325uA.
Id
min
Gm
min
20
= 212A =
Assuming Gm/Id = 20, we get the minimum bias current:
Gm
min
u
min
CLt
min
= 4.24mS = Thus:
for now, assume Cf/ CLt
min
= 1. We get: u
min
2 900 MHz =
u
min
1
t
s
1
F
ln
d
1 F
Cf
CLt
min

1
1
]
=

d

s
= 0.041% = thus:
s
1
F Adc
= 0.009% =
s

d
+ = Settling error:
Settling Considerations
Where it is assumed that Cf fully loads the output (very good approx.) and 150fF is allocated for stray
output capacitance.
CL = 0.3pF Cf = 0.3pF Cs = 4.8pF
Using the above result we can directly size CL, Cf, and Cs. For optimal performance, CL is made its
minimum value and Cf (and thus Cs) is sized to provide the rest. A large Cf is best to keep F large.
CLt
min
0.75pF =
This is very optimistic since the boosters will contribute noise as well. To get a more realistic
estimate we increase the noise factor from 1.25 to 1.50. Thus the minimum effective load capacitance
is:
(where we assumed gm4/gm1 = 1/4) CLt
min
4
3
Kb T
Von
2
( )
max
1
F
1
1
4
+

,
= 0.62pF =
Therefore, the minimum effective load capacitance is:
Von
2
( )
max
1
2
Vod
2
( )
DR
=
1
2
4
10
7
= 200
nV
2
Hz
=
The dynamic range is specified as 70dB. Thus the maximum noise that can be tolerated is:
Gmx
2 CL
Ccm
Ccm
Cx
2
+
x
1
F

Gm
CL

u
Gm
CL
= but: u
cm
x
1
F
u
We would like the common-mode unity-gain BW shown above to be
placed a factor x above the differential loop unity-gain BW:
u
cm
Gmx
2 CL
Ccm
Ccm
Cx
2
+
=
First consider the common-mode FB loop of the main amplifier:
CL CL Ccm
Ccm
Cx
Gmx
Gm Gm
Stability:
Common-Mode Feedback Considerations
Little emphasis is placed on this part of the design.High-swing biasing schemes are used for the main
amplifier and the booster amplifiers. In the main amplifier, the Vds of M4 and M5 change with process
variations. The bias circuit replicates Vds
4,5
such that slow/fast process variations only cause a small
deviation (1% or less) in the desired bias current.
Biasing Network Considerations
Device Lengths: Lengths in the booster amplifiers are made as large as needed in order to achieve
the desired gain. Since they are running at low currents, high gain is easily achieved for relatively
small lengths (L 1m < ). Lengths of input transistors are made minimal in order to achieve
maximum Gm/Id.
Bandwidth: ~ 150MHz (2x of the main amplifier unity-gain loop BW) to satisfy the safety criterion
(see above) by an ample margin. The bandwidth is fine-tuned using an additional load capacitance.
DC Gain: ~ 65dB. This releaves the burden of having to achieve high gain in the main amplifier,
which typically limits its achievable output swing and frequency response.
Topology: Folded-Cascode. Chosen for the following reasons:
1) Does not limit the swing at source of cascodes in main amplifier
2) Not constrained by DC level at source of cascodes in main amp
3) Power is not a concern since required BW is fairly low.
The design of the booster amplifier is very straight forward and is only summarized below:
Booster Amplifier Design Considerations
L1-L5: Lengths of all transistors in the main amplifier are made minimal in order to decrease
parasitic loading at the output and cascode-source nodes. The penalty in lower dc gain is not a
problem since the gain-boosted topology provides gain almost for free via the booster amplifiers.
L
1,2,3,4,5
= 0.35um
M4: M4 must be sized by considering dynamic range and dc gain. Swing 1/Vdsat and Noise
1/Vdsat. Since DR Swing
2
/Noise, low Vdsat appears to be preferable. However, in order to achieve
sufficient dc gain Vdsat cannot be lowered excessively. An optimum is found mainly using spice (since
rds is not easy to calculate). We obtain:
gm
4
~ 1.7mS
2) Slow-settling: although the doublet introduced by the booster amplifiers has been placed where it is
considered safe, the discrepancy in required bandwidth suggests that a slow-settling component must
still be present. Future work should attempt to provide a more optimal doublet placement than what was
achieved following K.Bult et. al.'s somewhat heuristic safety range.
this causes the required bandwidth to increase by about 8%.
1) Slewing: the above settling time approximations assumed that no slewing occurs. This is in fact not
exactly true. The large Gm/Id of M1 causes a Vdsat << 100mV (short-channel) and thus a small amount
of slewing results for Vo = +/-2V.
t
slew
1
F
Vi
step
Vdsat1
( )

CLt
Iss
= 1.95ns =
Sources of Errors
The one catch is that Rout
cm
is NOT boosted by the booster amplifier since those operate fully
differentially. Hence the CM Loop gain is mainly determined by the unboosted main amplifier (which
has a relatively low gain ~40dB).
Tcm s ( )
Gmx
x
Rout
cm
1
s CL

Rout
cm
1
s CL
+

Ccm
Ccm
Cx
2
+
=
The gain of the CMFB is typically not a major concern. However considering the main amplifier, we
note that the CMFB Loop gain is actually relatively small which may at first be non-intuitive:
CM Loop Gain:
For all three amplifiers, the above design values of CMFB capacitors result in close to negligible output
loading.
Again, we thus make them close to minimum size ensuring that enough common-mode BW is
provided. Although this results in a higher than needed BW, the simulated CM loop phase margin
remains above 80
o
in both cases thus ensuring stability.
Ccmx = 30fF (x~1.75) Ccmy = 30fF (x~0.99)
The exact same approach is directly applied to the booster amplifiers, only the common-mode unity
gain BW is now set with respect to the booster amplifier unity-gain BW (also the doublet frequency):
We obtain: Ccmx 2.8fF Ccmy 4.11fF (for x=1/2)
(x~2.65) => Ccm = 20fF
Thus make Ccm minimum cap
and should get plenty enough BW.
for x=1/2, we get Ccm 10.3fF Ccm
Cx
2
1
1
F x
Gmx
2 Gm
1
solving for Ccm, we get:


6. Simulation Plots

a) Differential AC Loop Frequency Response
b) Common-Mode AC Loop Frequency Response
c) Open Loop Gain vs. Differential Output Voltage
d) Positive Settling
e) Negative Settling
f) Total Integrated Output Voltage Noise


NOTE: Only the plots of the hardcopy have annotations.


COLOR CODING:
Dark blue: NOMINAL
Purple: FAST
Light blue: SLOW
Symbol Wave
D0:A0:par(tmag)
D0:A1:par(tmag)
D0:A2:par(tmag)
P
a
r
a
m
s

(
l
i
n
)
-60
-40
-20
0
20
40
60
80
Frequency (log) (HERTZ)
10
100 1k 10k 100k 1x 10x 100x 1g
10g
|T(s)|=0.0000e+00
f (Hz)=7.1809e+07
|T(s)|=0.0000e+00
f (Hz)=6.8314e+07
AC Loop Gain (dB)
Symbol Wave
D0:A0:par(tpha)
D0:A1:par(tpha)
D0:A2:par(tpha)
P
a
r
a
m
s

(
l
i
n
)
-150
-100
-50
0
Frequency (log) (HERTZ)
10
100 1k 10k 100k 1x 10x 100x 1g
10g
<T(s)=-9.3595e+01
f (Hz)=7.1809e+07
<T(s)=-9.3404e+01
f (Hz)=6.8314e+07
Loop Gain Phase Response
Symbol Wave
D0:A0:par(tmag)
D1:A0:par(tmag)
D2:A0:par(tmag)
P
a
r
a
m
s

(
l
i
n
)
-60
-40
-20
0
20
40
Frequency (log) (HERTZ)
100k
1x 10x 100x 1g
10g
|Tcm(s)|=0.0000e+00
f (Hz)=4.5308e+08
|Tcm(s)|=0.0000e+00
f (Hz)=4.2115e+08
Common Mode AC Loop Gain
Symbol Wave
D0:A0:par(tpha)
D1:A0:par(tpha)
D2:A0:par(tpha)
P
a
r
a
m
s

(
l
i
n
)
-150
-100
-50
0
50
100
150
Frequency (log) (HERTZ)
100k
1x 10x 100x 1g
10g
<Tcm(s)=-1.2487e+02
f (Hz)=4.2115e+08
<Tcm(s)=-1.2757e+02
f (Hz)=4.5308e+08
Common Mode Loop Phase Response
Symbol Wave
D0:A0:par(adc)
D0:A1:par(adc)
D0:A2:par(adc)
P
a
r
a
m
s

(
l
i
n
)
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
Voltages (lin) (v(vod)
-2.5 -2 -1.5 -1 -500m 0 500m 1 1.5 2 2.5
ADC=1.087e+02
Vod (V)=-2.000e+00
ADC=1.088e+02
Vod (V)=2.000e+00
ADC=1.092e+02
Vod (V)=2.000e+
.092e+02
)=-2.000e+00
OTA DC Open Loop Gain (dB) vs. Vod (V)
Symbol Wave
D0:A0:v(vod)
D0:A1:v(vod)
D0:A2:v(vod)
V
o
l
t
a
g
e
s

(
l
i
n
)
0
200m
400m
600m
800m
1
1.2
1.4
1.6
1.8
2
Time (lin) (TIME)
0
5n 10n 15n 20n 25n
30n
Differential Positive Step Response
Symbol Wave
D0:A0:Enominal
D0:A1:Efast
D0:A2:Eslow
R
e
s
u
l
t

(
l
i
n
)
-100m
-95m
-90m
-85m
-80m
-75m
-70m
-65m
-60m
-55m
-50m
-45m
-40m
-35m
-30m
-25m
-20m
-15m
Time (lin) (TIME)
20n
25n
30n
settling error (%)=-5.0000e-02
time=2.3439e-08
fast
settling error (%)=-5.0000e-02
time=2.4149e-08
nominal
settling error (%)=-5.0000e-02
time=2.5029e-08
slow
Positive Settling Error (%)
Symbol Wave
D0:A0:v(vod)
D0:A1:v(vod)
D0:A2:v(vod)
V
o
l
t
a
g
e
s

(
l
i
n
)
-2
-1.8
-1.6
-1.4
-1.2
-1
-800m
-600m
-400m
-200m
0
Time (lin) (TIME)
0
5n 10n 15n 20n 25n
30n
Differential Negative Step Response
Symbol Wave
D0:A0:Enominal
D0:A1:Efast
D0:A2:Eslow
R
e
s
u
l
t

(
l
i
n
)
-100m
-95m
-90m
-85m
-80m
-75m
-70m
-65m
-60m
-55m
-50m
-45m
-40m
-35m
-30m
-25m
-20m
-15m
-10m
-5m
0
5m
Time (lin) (TIME)
20n
25n
30n
settling error (%)=-5.0000e-02
time=2.5029e-08
slow
settling error (%)=-5.0000e-02
time=2.4149e-08
nominal
settling error (%)=-5.0000e-02
time=2.3439e-08
fast
Negative Settling Error (%)
Symbol Wave
D0:A3:Votn
D0:A4:Votf
D0:A5:Vots
R
e
s
u
l
t

(
l
i
n
)
0
20u
40u
60u
80u
100u
120u
140u
160u
180u
200u
220u
240u
260u
280u
300u
320u
340u
360u
380u
400u
420u
440u
460u
Frequency (log) (HERTZ)
100
1k 10k 100k 1x 10x 100x 1g 10g
100g
Von (Vrms)=4.47e-04
f (Hz)=4.40e+10
Total Integrated Output Noise Voltage (Vrms)


7. Comments and Conclusion
A fast-settling OTA has been designed and simulated in a 0.35m CMOS technology with a
3V supply. The final design meets the specifications for dynamic range and settling time under
nominal/slow/fast process corners. The amplifier consumes 2.63mW by itself, and a total of
4.04mW including biasing.

The design was initiated with a set of equations used to estimate circuit design parameters and
the expected power budget. Estimates of capacitors values did not need further adjustments from
hand-calculated results. Transistor sizes had to be adjusted via Spice to correct for discrepancies
due short-channel effects. Although, the frequency at which the doublet occurs is placed in the
safe range as described in [1], the resulting settling time is about 4ns longer than expected
given the achieved bandwidth and dc gain. Hence, the current consumption had to be increased
accordingly in order to meet the specifications. As shown in the previous section, a small
slewing component is responsible for a part of this error. The remainder of this error is believed
to stem from a doublet-induced overdamped component. Although the heuristic design criteria
introduced in [1] cannot explain this discrepancy, it is shown in [2] that in the case of high
settling accuracy, lower frequency doublets show much slower settling behavior than higher
frequency doublets (everything else kept the same) for any doublet spacing. This means that
designing booster amplifiers with higher bandwidth might have eliminated the above
discrepancy. Of course, the booster unity-gain frequency (where the doublet is located) cannot be
made excessively large for reasons of stability (non-dominant pole
p2
has to remain sufficiently
far). This suggests that an optimum location the doublet frequency,
p2
, may exist in the range
2
1
p d u
F
< < . The surprisingly small number of publications relating to the design of gain-
boosted amplifiers, combined with the time constraints imposed on this project made it difficult
to address this issue herein. It would be interesting to investigate this further in a future project.



REFERENCES:
[1] K. Bult and G. J. G. M. Geelen, A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB
DC Gain, IEEE J. Solid-State Circuits, vol.25, No. 6, December 1990.
[2] B. Y. Kamath, R. G. Meyer, P. R. Gray, Relationship Between Frequency Response and
Settling Time of Operational Amplifiers, IEEE J. Solid-State Circuits, vol. sc-9, No. 6,
December 1974.
[3] K. Gulati and H-S Lee, A High-Swing CMOS Telescopic Operational Amplifier, IEEE J.
Solid-State Circuits, vol. 33, No. 2, December 1998.
[4] D. Flandre, A. Viviani, et. al, Improved Synthesis of Gain-Boosted Regulated-Cascode
CMOS Stages Using Symbolic Analysis and gm/ID Methodology, J. Solid-State Circuits, vol.
32, No. 7, July 1997.
[5] D. Johns and K. Martin, Analog Integrated Circuit Design, Wiley 1997, pages 261-262.


8. Appendix a) Circuit Netlist

ee240 - project - Fast-settling OTA - Axel Berny

.param lc=.35u
.param wnt=130u
.param wn1=230u
.param wn2=80u
.param wp3=35u
.param wp4=30u

* signal sources
vs vs 0 ac=1 pwl 0 0 5n 0 5.1n -.125 60n -.125
vic vic 0 dc=0.81

* bias network
vdd vdd 0 dc=3
iss vdd vr2 dc=25u

x0 vr1 vr2 vr3 vr4 vbn vbp vdd amp_bias

* n-side mirror
mr1 vr1 vr1 0 0 nmos w=15u l=1u
mr2 vr2 vr2 vr1 0 nmos w=15u l=1u

* p-side mirror
ms1 vs1 vr1 0 0 nmos w=15u l=1u
ms2 vr3 vr2 vs1 0 nmos w=15u l=1u
ms3 vr3 vr3 vr4 vr4 pmos w=15u l=1u
ms4 vr4 vr4 vdd vdd pmos w=15u l=1u

* this is to establish the desired dc operating point
vcma vcma 0 dc=670.6m
rcma vcma vcmb Rr r=10g

* cmfb loop
ccmp vop vcmb 20f
ccmn von vcmb 20f

* boosters
x1 vd6 vd5 g5 g6 vod_n vr1 vr2 vr3 vr4 vdd nboostt
x2 vd4 vd3 g3 g4 vod_p vr1 vr2 vr3 vr4 vdd pboostt

* amplifier
mta vx vbn 0 0 nmos w='wnt' l='lc'
mtb vx vcmb 0 0 nmos w='wnt' l='lc'

m1a vd5 vin vx 0 nmos w='wn1' l='lc'
m1b vd6 vip vx 0 nmos w='wn1' l='lc'

m2a vop g5 vd5 0 nmos w='wn2' l=.35u

m2b von g6 vd6 0 nmos w='wn2' l=.35u

m3a vop g3 vd3 vd3 pmos w='wp3' l=.35u

m3b von g4 vd4 vd4 pmos w='wp3' l=.35u

m4a vd3 vbp vdd vdd pmos w='wp4' l=.35u
m4b vd4 vbp vdd vdd pmos w='wp4' l=.35u

* baluns for simulations
x3 vs vic v1p v1n balun
x4 vid vic v2p v2n balun
x5 vid vic vip vin balun
x6 vod voc vop von balun

* load/feedback/input capacitors
csp v1p v2p 4.96p
csn v1n v2n 4.96p
cfp vop vin 0.31p
cfn von vip 0.31p
clp vop 0 0.30p
cln von 0 0.30p

* simulation setup
.options list brief post dccap accurate=1
.op

.ac dec 100 10 100g
.probe avd=par('20*log10(v(vod)/v(vs))')

.tran .01n 60n
.noise v(vod) vs

.model Rr R noise=0
.include 'spice_lib.txt'
.include 'ckt_lib.txt'
.lib 'cmos35.txt' nominal



.alter fast
vcma vcma 0 dc=679.6m
.param vcman=1.896723
.param vcmap=875.215m
.del lib 'cmos35.txt' nominal
.lib 'cmos35.txt' fast

.alter slow
vcma vcma 0 dc=660.8m
.param vcman=1.921231
.param vcmap=861.299m
.del lib 'cmos35.txt' fast
.lib 'cmos35.txt' slow
********************************************************************
************************
** N-SIDE BOOSTER AMP
********************************************************************
************************
.subckt nboostt vip vin vop von vod vr1 vr2 vr3 vr4 vdd

.param lcn=.6u
.param wpin=30u
.param wn1n=2u
.param wn2n=7u
.param wp3n=15u
.param wp4n=5u
.param vcman=1.906168

con von 0 0.38p
cop vop 0 0.38p

* cmfb loop
ccmp vop vcmb 30f
ccmn von vcmb 30f
* this is to establish the desired dc operating point
rcma vcma vcmb Rr r=10g
vcma vcma 0 dc='vcman'

x0 vod voc vop von balun
x1 vr1 vr2 vr3 vr4 vb1 vb2 vb3 vb4 vdd nbooster_bias

* amplifier
mt4a vt4 vb4 vdd vdd pmos w='wp4n' l='lcn' m=1
mt4b vt4 vcmb vdd vdd pmos w='wp4n' l='lcn' m=1
mt3 vx vb3 vt4 vt4 pmos w='wp3n' l='lcn' m=2


mia vd5 vin vx vx pmos w='wpin' l=.35u m=1
mib vd6 vip vx vx pmos w='wpin' l=.35u m=1
m1a vd5 vb1 0 0 nmos w='wn1n' l='lcn' m=2
m1b vd6 vb1 0 0 nmos w='wn1n' l='lcn' m=2

m2a vop vb2 vd5 0 nmos w='wn2n' l='lcn' m=1

m2b von vb2 vd6 0 nmos w='wn2n' l='lcn' m=1

m3a vop vb3 vd3 vd3 pmos w='wp3n' l='lcn' m=1

m3b von vb3 vd4 vd4 pmos w='wp3n' l='lcn' m=1

m4a vd3 vb4 vdd vdd pmos w='wp4n' l='lcn' m=1

m4b vd4 vb4 vdd vdd pmos w='wp4n' l='lcn' m=1


.ends


********************************************************************
************************
** P-SIDE BOOSTER AMP
********************************************************************
************************
.subckt pboostt vip vin vop von vod vr1 vr2 vr3 vr4 vdd

.param lcp=.7u
.param wnip=20u
.param wn1p=2.25u
.param wn2p=7u
.param wp3p=12u
.param wp4p=6u
.param vcmap=868.4835m

cop vop 0 0.05p
con von 0 0.05p

* for ac cmfb loop (part of actual circuit)
ccmp vop vcmb 30f
ccmn von vcmb 30f
a s ( )
gm2
s CL
gds1 gds2 1
s
p2
+

gm1 Ag 1 + ( )
+
=
Thus
Gout
gds1 gds2 1
s
p2
+

gm1 Ag 1 + ( )
= Rout gm1 rds1 Ag 1 + ( ) z2 =
Ag
Ao
1
s
p1
+
=
z2
rds2
1
s
p2
+
=
p2
1
2
=
1
rds2 Cx
=
also call define gds2 = 1/rds2
Let z2 = 1/Cx || rds2
Start as on page 261 Fig. 6.4
of [5] but replace rds2 with z2
C
x
M1
M2
C
L
R
out
V
in
V
ref
V
o
A
g
8. Appendix c) Gain-Boosting Pole-Zero Doublet Analysis
We conclude that, optimal sizing of M2 in terms of stability is achieved when its total source
capacitance is made equal to the parasitic capacitance Cx present at the same node. Since this
assumes an ideal square law device, this approach should only be used as a starting point.
We obtain: Cx k2 W2 = Cgs2 Csb2 + = .
Now take
W2

p2
d
d
0 =
p2
W2 ( )
k1 W2
Cx k2 W2 +
=
Let Gm
2
k1 W2 = and Cgs2 Csb2 + k2 W2 =
(typically Cx ~ Cdb1)
p2
Gm
2
Cx Cgs2 + Csb2 +
=
Cx
M1
M2
8. Appendix b) Non-dominant Pole Optimization
a s ( )
gm2 Ag 1 + ( )
s CL Ag 1 + ( )
gds1 gds2
gm1
1
s
p2
+

,
+
=
a s ( )
gm2
Ao
1
s
p1
+
1 +

s CL
Ao
1
s
p1
+
1 +

gds1 gds2
gm1
1
s
p2
+

,
+
=
a s ( )
gm2 Ao 1 +
s
p1
+

s CL Ao 1 +
s
p1
+

gds1 gds2
gm1
1
s
p2
+

,
1
s
p1
+

,
+
=
Since Ao >> 1, we have:
a s ( )
gm2 Ao
s
p1
+

s CL Ao
s
p1
+

gds1 gds2
gm1
1
s
p2
+

,
1
s
p1
+

,
+
=
If dealing with freq's near wu, then we can simplify as follows:
a s ( )
u
s
Ao
s
p1
+

,
Ao
s
p1
+

,
gds1 gds2
gm1 CL
s
p1 p2
+
=
a s ( )
u
s
Ao s 1 + ( )
Ao s 1
1 2
gm1 rds1 rds2 CL
+

,
+
=
a s ( )
u
s
1 s
1
Ao
+

,
1 s
1
Ao
1 2
gm1 rds1 rds2 CL Ao
+

,
+
=
But this now become identical to where part (b) of the class notes [Effect of Doublet on
Amplifier Settling Time] starts... The results from there can be used from here on...
A s ( )
1
F
1
1
1
a s ( ) F
+
=
There are two main effects from the loading:
1) CL increases by factor (1+Cf/CL*(1-F))
2) RHP zero introduced at Cf/gm2
Note: here we are ignoring the feedback loading (buffer) Now let us add feedback:
So we can exect to be close to unity, especially since Cx/CL is small... Good!
Hence we gain some insight on what it takes to achieve an "accurate" doublet.
1
Cx
CL
1
gm1 rds1
+ = so z
p

=
Now let's look at z:
Already we note the resemblance to safe region claimed in [1]. Expression of suggests that
gmo/Co (i.e. the doublet frequency) should be higher than u (or Fu as we close the
feedback loop) to minimize effects of the doublet.
CL/Co should be large but gmo/gm2 is typically small...
CL
Co
gmo
gm2
=
Which is approximately:

gmo
Co 1
Cx
gm1 rds1 CL
+

CL
gm2
=
CL
Co
gmo
gm2

1
1
Cx
CL
1
gm1 rds1
+

,
=
Thus :
p
Ao
1 1
Cx
gm1 rds1 CL
+

=
gmo
Co 1
Cx
gm1 rds1 CL
+

=
p u = Where: a s ( )
u
s
1
s
z
+
1
s
p
+
=
Let us redefine a(s) as follows:
pole
Ao
1 1
Cx
gm1 rds1 CL
+

= zero
Ao
1
=