Sathyabama University M.E. Embedded Systems Regulations 2010 Syllabus

SATHYABAMA UNIVERSITY
(Established under section 3 of UGC Act, 1956)
Jeppiaar Nagar, Rajiv Gandhi Salai, Chennai - 119.
SYLLABUS MASTER OF ENGINEERING PROGRAMME IN EMBEDDED SYSTEMS (4 SEMESTERS) REGULATIONS 2010
FACULTY OF ELECTRONICS ENGINEERING
SATHYABAMA UNIVERSITY REGULATIONS 2010

Effective from the academic year 2010-2011 and applicable to the students admitted to the Master of Engineering / Technology / Architecture /Science (Four Semesters) 1. Structure of Programme 1.1 Every Programme will have a curriculum with syllabi consisting of theory and practical such as: (i) (ii) (iii) (iv) 1.2 General core courses like Mathematics Core course of Engineering / Technology/Architecture / Science Elective course for specialization in related fields Workshop practice, Computer Practice, laboratory Work, Industrial Training, Seminar Presentation, Project Work, Educational Tours, Camps etc.
Each semester curriculum shall normally have a blend of lecture course not exceeding 7 and practical course not exceeding 4.
2.
1.3 The medium of instruction, examinations and project report will be English. Duration of the Programme A student is normally expected to complete the M.E/M.Tech./M.Arch/M.Sc Programme in 4 semesters but in any case not more than 8 consecutive semesters from the time of commencement of the course. The Head of the Department shall ensure that every teacher imparts instruction as per the number of hours specified in the syllabus and that the teacher teaches the full content of the specified syllabus for the course being taught.
3.
Requirements for Completion of a Semester A candidate who has fulfilled the following conditions shall be deemed to have satisfied the requirement for completion of a semester. 3.1 3.2 He/She secures not less than 90% of overall attendance in that semester. Candidates who do not have the requisite attendance for the semester will not be permitted to write the University Exams.
4.
Examinations The examinations shall normally be conducted between October and December during the odd semesters and between March and May in the even semesters. The maximum marks for each theory and practical course (including the project work and Viva Voce examination in the Fourth Semester) shall be 100 with the following breakup. (i) Theory Courses
Internal Assessment : University Exams : 20 Marks 80 Marks
(ii)
Practical courses
Internal Assessment : University Exams : - 100 Marks
M.E. (EMBEDDED SYSTEMS)
REGULATIONS 2010
5.
Passing requirements (i) A candidate who secures not less than 50% of total marks prescribed for the course (For all courses including Theory, Practicals and Project work) with a minimum of 40 marks out of 80 in the University Theory Examinations, shall be declared to have passed in the Examination. If a candidate fails to secure a Pass in a particular course, it is mandatory that he/she shall reappear for the examination in that course during the next semester when examination is conducted in that course. However the Internal Assessment marks obtained by the candidate in the first attempt shall be retained and considered valid for all subsequent attempts.
(ii)
6.
Eligibility for the Award of Degree A student shall be declared to be eligible for the award of the M.E/M.Tech./M.Arch./M.Sc degree provided the student has successfully completed the course requirements and has passed all the prescribed examinations in all the 4 semesters within the maximum period specified in clause 2.
7.
Award of Credits and Grades All assessments of a course will be done on absolute marks basis. However, for the purpose of reporting the performance of a candidate, Letter Grades will be awarded as per the range of total marks (out of 100) obtained by the candidate as given below:
RANGE OF MARKS FOR GRADES

Range of Marks 90-100 80-89 70-79 60-69 50-59 00-49 ABSENT Grade A++ A+ B++ B+ C F W Grade Points (GP) 10 9 8 7 6 0 0
CUMULATIVE GRADE POINT AVERAGE CALCULATION

The CGPA calculation on a 10 scale basis is used to describe the overall performance of a student in all courses from first semester to the last semester. F and W grades will be excluded for calculating GPA and CGPA.
CGPA = i C i GP i i Ci
where Ci - Credits for the subject

GP i - Grade Point for the subject i - Sum of all subjects successfully cleared during all the semesters
ii
REGULATIONS 2010
8.
Classification of the Degree Awarded 1 A candidate who qualifies for the award of the Degree having passed the examination in all the courses of all the semesters in his/her first appearance within a maximum period of 4 consecutive semesters after commencement of study securing a CGPA not less than 9.0 shall be declared to have passed the examination in First Class Exemplary. A candidate who qualifies for the award of the Degree having passed the examination in all the courses of all the semesters in his/her first appearance within a maximum period of 4 consecutive semesters after commencement of study, securing a CGPA not less than 7.5 shall be declared to have passed the examination in First Class with Distinction. A candidate who qualifies for the award of the Degree having passed the examination in all the courses of all the semesters within a maximum period of 4 consecutive semesters after commencement of study securing a CGPA not less than 6.0 shall be declared to have passed the examination in First Class. All other candidates who qualify for the award of the Degree having passed the examination in all the courses of all the 4 semesters within a maximum period of 8 consecutive semesters after his/her commencement of study securing a CGPA not less than 5.0 shall be declared to have passed the examination in Second Class. A candidate who is absent in semester examination in a course/project work after having registered for the same, shall be considered to have appeared in that examination for the purpose of classification of degree. For all the above mentioned classification of Degree, the break of study during the programme, will be counted for the purpose of classification of degree. A candidate can apply for revaluation of his/her semester examination answer paper in a theory course, within 1 week from the declaration of results, on payment of a prescribed fee along with prescribed application to the Controller of Examinations through the Head of Department. The Controller of Examination will arrange for the revaluation and the result will be intimated to the candidate concerned through the Head of the Department. Revaluation is not permitted for practical courses and for project work.
2.
3.
Final Degree is awarded based on the following :

CGPA 9.0 CGPA 7.50 < 9.0 CGPA 6.00 < 7.50 CGPA 5.00 < 6.00 First Class - Exemplary First Class with Distinction First Class Second Class
Minimum CGPA requirements for award of Degree is 5.0 CGPA. 9. Discipline Every student is required to observe disciplined and decorous behaviour both inside and outside the University and not to indulge in any activity which will tend to bring down the prestige of the University. If a student indulges in malpractice in any of the University theory / practical examination, he/she shall be liable for punitive action as prescribed by the University from time to time. 10. Revision of Regulations and Curriculum The University may revise, amend or change the regulations, scheme of examinations and syllabi from time to time, if found necessary.
M.E. (EMBEDDED SYSTEMS) iii REGULATIONS 2010
M.E - EMBEDDED SYSTEMS REGULATIONS 2010 - CURRICULUM SEMESTER I

Sl.No. THEORY 1. 2. 3. 4. 5. PRACTICAL 6. SECX6501 Embedded Systems Lab I 0 0 4 2 12 TOTAL CREDITS : 19 SECX5016 SECX5017 SECX5018 SECX5001 SECX5002 Transforms and Probability for Electronics Engineering Advanced Digital System Design VLSI Design Microcontrollers System Design Embedded C 3 3 3 3 3 1 0 0 1 0 0 0 0 0 0 4 3 3 4 3 1 2 3 4 5 SUBJECT CODE SUBJECT TITLE L T P C Page No.
SEMESTER II
Sl.No. THEORY 1. 2. 3. 4. 5. PRACTICAL 6. SECX6502 Embedded Systems Lab. II 0 0 4 2 13 TOTAL CREDITS: 18 SECX5003 SECX5004 SECX5005 DSP Processors Real Time Operating System Embedded System Design Elective-I Elective-II 3 3 3 3 3 0 1 0 0 0 0 0 0 0 0 3 4 3 3 3 6 7 8 SUBJECT CODE SUBJECT TITLE L T P C Page No.
SEMESTER III
Sl.No. THEORY 1. 2. 3. 4. 5. PRACTICAL 6. SECX6512 Design Project Lab. 0 0 4 2 12 TOTAL CREDITS: 18 SECX5006 SECX5007 SECX5031 Programming in Matlab and Labview Embedded Networking Cryptography and Network Security Elective-III Elective-IV 3 3 3 3 3 0 1 0 0 0 0 0 0 0 0 3 4 3 3 3 9 10 11 SUBJECT CODE SUBJECT TITLE L T P C Page No.
iv
REGULATIONS 2010
SEMESTER IV
Sl.No. 1. SUBJECT CODE S88XPROJ SUBJECT TITLE Project work & Viva Voce L 0 T 0 P 30 C 15
TOTAL CREDITS FOR THE COURSE: 70
LIST OF ELECTIVE SUBJECTS

Sl.No. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. SUBJECT CODE SECX5021 SECX5008 SECX5031 SECX5084 SECX5085 SECX5009 SECX5010 SECX5011 SECX5079 SECX5012 SICX5010 SECX5013 SECX5086 SECX5014 SECX5069 SUBJECT TITLE Advanced Digital Signal and Image Processing Embedded Processor and Peripherals Electromagnetic Interference and Compatibility Fuzzy Logic and Neural Network Blue Tooth Technology Mixed Signal Embedded System Data Compression Techniques Advanced Embedded Systems Wireless Sensor Networks Embedded Communication Software Design Advanced Robotics and Automation DSP Integrated Circuits Wireless and Mobile Communication Embedded Control Systems Analysis and Modeling of Digital System Using VHDL L 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Page No. 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
L Lecture hours; T Tutorial hours; P Practical hours; C Credits
REGULATIONS 2010
SECX5016
TRANSFORMS & PROBABILITY FOR ELECTRONICS ENGINEERING (Common to VLSI, Embedded, NanoTech.)
L 3
T 1
P 0
Credits 4
Total Marks 100
UNIT I ID TRANSFORMS
10 hrs.
Review of Fourier analysis - Analysis of different periodic & non periodic waveforms Sampling Theorem DFS - DTFT - DFT - inverse DFT- properties - FFT radix r algorithm DIT FFT & DIF FFT - Convolution review of Z transform- Hilbert transform
UNIT II 2D TRANSFORMS
10 hrs.
Need for transform 2D Orthogonal and Unitary transform and its properties 2D DFT Properties FFT Statement, proof and properties of Separable transforms Walsh, Hadamard, Haar, Discrete Sine, DCT, Slant, SVD & KL transforms
UNIT III WAVELET TRANSFORMS
10 hrs.
Wavelet transform - 1D & 2D Wavelet transform - Time and frequency decompositions - STFT - Continues and discrete - CWT, DWT, Harr wavelet and Shannon wavelet- Fast Wave let transform Wavelet Packets.
UNIT IV PROBABILITY AND RANDOM VARIABLES
10 hrs.
Probability concepts- Random variable - moment generating function - discrete types, continues types -2D variable random variables marginal, conditional, joint probability distribution - Binomial, Poisson, uniform, normal and Exponential distributions
UNIT V RANDOM PROCESS
10 hrs.
Notion of stochastic processes, Auto Correlation Cross Correlation WSS Ergodicity - power spectral density function properties - Discrete random process expectations variance, co variance scalar product energy of discrete signals parseval,s theorem Wiener Khintchine relation Discrete random signal processing by linear systems - response of linear discrete systems to white noise - Two dimensional random variables - transformation of random variables - regression system - simulation of white noise low pass filtering of white noise.
TEXT BOOK:
1. Ronald W. Schafer, Alan V. Oppenheim, Discrete Time Signal Processing, Prentice Hall, 3
rd
Edition,2009.
REFERENCE BOOKS:
1. 2. 3. 4. 5. Gonzalez, Woods, and Eddins, Digital Image Processing, Prentice Hall, 3rd Edition, 2008. Raghuveer M. Rao, Ajit S. Bopardikar, Wavelet Transforms: Introduction to Theory & Applications, Prentice Hall, 1st Edition, 1998. Yaglon.A.M, Probability and information, Springer Publication, 1983. W. John Wodds, Probability and random process with application to signal processes, Prentice Hall, 2001. Atkinson.F.V, Discrete and continuous boundary problems, Academic Press Inc, Volume 8, 1998.
UNIVERSITY EXAM QUESTION PAPER PATTERN

Max. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each No choice. 30 marks Part B: 5 Questions from each of the five units of internal choice, each carrying 10 marks. 50 marks (40% - Problems, 60% - Theory)
M.E. (EMBEDDED SYSTEMS) 1 REGULATIONS 2010
SECX5017
ADVANCED DIGITAL SYSTEM DESIGN (Common to VLSI, Embedded, Appl. Elec.)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I SEQUENTIAL LOGIC CIRCUITS
10 hrs.
Mealy machine, Moore machine, Trivial/Reversible/Isomorphic sequential machines, State diagrams, State table minimization, Incompletely specified sequential machines, State assignments, Design of synchronous and asynchronous sequential logic circuits working in fundamental and pulse mode.
UNIT II SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN
10 hrs.
Analysis of clocked synchronous sequential Networks (CSSN), Modeling of CSSN-State table assignment and reduction Design of CSSN-Design of iterative circuits- ASM Chart- ASM Realization.
UNIT III ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN
10 hrs.
Analysis of Asynchronous sequential Circuits (ASC)-Flow table reduction -Races in ASC--State assignmentProblem and the Transition table-Design of ASC-Static and Dynamic hazards-Data synchronizers-Designing of Vending machine controller-Mixed operating mode Asynchronous circuits.
UNIT IV PROGRAMMABLE LOGIC DEVICES
10 hrs.
Basic concepts, programming technologies, Programmable Logic Element(PLE),Programmable Logic Array(PLA), Programmable Array Logic(PAL), Structure of standard PLDs,Complex PLDs(CPLD)-System design using PLDs-Design of combinational and sequential circuits using PLDs,Programmable PAL device using PALASM,Design of state machine using Algorithmic State Machines(ASM) chart as design tool.
UNIT V STUDY OF FPGA AND XILINX
10 hrs.
Introduction to Field Programmable Gate Arrays-Types of FPGA Xilinx XC3000 series, Logic Cell Array(LCA), Configurable Logic Blocks (CLB), Input/Output Block (IOB)-Programmable Interconnect Point(PIP),Introduction to ACT2 family and Xilinx XC4000 families, Design examples.
TEXT BOOK:
1. Donald G.Givone, Digital Principles and Design, Tata Mc Graw Hill, 2002.
REFERENCE BOOKS:
1. John M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2001. 2. Nripendra N Biswas, Logic Design Theory, Prentice Hall of India, 2001. 3. Charles H Roth Jr, Fundamentals of Logic Design, Thomson Learing, 2004.

Max. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each No choice. 30 marks Part B: 5 Questions from each of the five units of internal choice, each carrying 10 marks. 50 marks (60% - Problems, 40% - Theory)
SECX5018
VLSI DESIGN (Common to VLSI, Embedded, NanoTech)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I
10 hrs.
Review of MOS electrical properties Expression for threshold voltage and drain current - Energy band structure and band bending in the different region of operation - Secondary effects of MOSFET review of CMOS and bipolar technologies.
UNIT II
10 hrs.
Basic inverter - Inverter Device sizing - Enhancement load and depletion-load inverters CMOS inverter CMOS inverter logic levels Inverter device sizing combinational logic implementation using NMOS and CMOS inverters - NMOS and CMOS design rules stick diagram and layout.
UNIT III
10 hrs.
Steering logic design programmable logic arrays Folded PLAs structured gate arrays Dynamic MOS storage circuits performance of Dynamic logic clocked CMOS logic
UNIT IV
10 hrs.
CMOS static flip-flops-dynamic sequential circuits CMOS Logic NORA CMOS - True single phase clocked logic Capacitors and performance in CMOS driving large capacitance - Resistance and performance
UNIT V
10 hrs.
Design of order Static, dynamic, Manchester carry chain, carry bypass adder, CSA,carry look ahead adder multipliers : Baugh wooley, Booth Multiplier Barrel shifter NOR and NAND ROMs operations in CMOS SRAM Sence amplifiers
TEXT BOOK:
1. Jan M. Rabaey Digital Integrated Circuits, Pearson Education Ltd, 2003.
REFERENCES BOOKS:
1. 2. 3. 4. 5. Randall L, Geigar and Allence, VLSI Design for Analog and Digital circuits, Mc Graw Hill, 1990. Fabricious E Design, Introduction to VLSI Design, Mc Graw Hill, 1990. Douglas A. Pucknell, Basic VLSI Design, Prentice Hall, 1994. Franco Maloberti, Kluwer, Analog design for CMOS VLSI systems, Academic Publishers, 2001. Abdellatif Bellaouar, Low-Power Digital VLSI Design: Circuits and Systems, Kluwer Academic Publishers, 2000.

Max. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each No choice. 30 marks Part B: 5 Questions from each of the five units of internal choice, each carrying 10 marks. 50 marks (90% - Theory, 10% - Problems)
SECX5001
MICROCONTROLLERS SYSTEM DESIGN
L 3
T 1
P 0
Credits 4
Total Marks 100
UNIT I 8-BIT MICROCONTROLLER
10 hrs.
Introduction-Intel 8051 architecture-Counters and Timers-Serial interface-Interrupts-Interfacing to external memory and 8255-Instruction set-Addressing modes.
UNIT II 8051 ALP AND APPLICATIONS
10 hrs.
Assembly language programming-Timers and Counters programming-DAC, ADC, Sensor, Keyboard and LCD.
UNIT III PIC MICROCONTROLLER
10 hrs.
Introduction: PIC microcontroller features, PIC Architecture, Program memory, Addressing Modes, Instruction set, Instruction Format, Byte-Oriented Instructions, Bit-Oriented Instructions, Literal Instructions, Control Instructions (CALL and GOTO),Destination Designator (d). MPLAB overview: Using MPLAB, Toolbars, Select Development Mode and Device Type, Project, Text Editor, Assembler, MPLAB Operations.
UNIT IV PIC HARDWARE
10 hrs.
Reset, clock, control registers, register banks, program memory paging, Ports, interrupts, Timer and Counter, watchdog timer, power up timer, sleep mode, ports-interrupts-I2C Bus-A/D converter.
UNIT V HIGH PERFORMANCE RISC ARCHITECTURE
10 hrs.
ARM: The ARM architecture - ARM organization and implementation - The ARM instruction set - The thumb instruction set - Basic ARM Assembly language program - ARM CPU cores.
TEXT BOOK:
1. Ayala, Kenneth, "The 8051 Microcontroller", Thomson, 2nd Edition, 2000.
REFERENCES BOOKS:
1. Muhammad Ali Mazidi, Janice Gillispie Mazidi., "The 8051 Microcontroller and Embedded systems", Person Education, 2nd Edition, 2004. 2. John.B.Peatman, "Design with Microcontrollers", Person Education, 1st Edition, 2004. 3. Steave Furber, "ARM system - on - chip architecture", Addison Wesley, 2nd Edition, 2000. 4. A. V. Deshmukh, "Microcontrollers: theory and applications", Tata Mc Graw Hill, 12th reprint, 2005.

Max. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each No choice. 30 marks Part B: 5 Questions from each of the five units of internal choice, each carrying 10 marks. 50 marks
SECX5002
EMBEDDED C
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I
10 hrs.
Introduction-basic features-data types-input and output statement-if statement-else if-switch statement-for loop-while loop-do while loop.
UNIT II
10 hrs.
Arrays-strings - pointers- structures and unions-functions and macros-pre-processor-C compilation system-file handling.
UNIT III
10 hrs.
System programming Vs. Application programming-option of C for embedded programming-review of C language with embedded perspective.
UNIT IV
10 hrs.
Bitwise operators-pointers arithmetic-bit fields-mixing assembly and C-Memory Management in C-Optimization techniques-testing and debugging,Communication with Matlab and Labview.
UNIT V
10 hrs.
Reading switches-using the serial interface-meeting real time constraints-creating hardware delay using timers-creating loop timeouts. Case study: Intruder Alarm System.
TEXT BOOK:
1. K R Venugopal and Sudeep R Prasad. Programming with C, Tata Mc Graw-Hill, 1st Edition, 2003.
REFERENCE BOOKS:
1. Michael J Pont, "Embedded C", Addison-Wesley, 1st Edition, 2002. 2. John catsoulis, "Designing embedded hardware", OReilly Media, 2nd Edition, 2005.

SECX5003
DSP PROCESSORS
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I FOURIER TRANSFORM AND SPECTRUM ESTIMATION
10 hrs.
Sampling of Band Pass signals-Sampling rate conversion-Decimation by an integer factors- Interpolation by an integer Factor -Discrete Fourier transform properties Fast Fourier transform periodogram estimator- Bartlett spectrum estimation- Welch estimation.
UNIT II FILTERS
10 hrs.
FIR Filter windowing technique optimum equiripple linear phase FIR filter IIR filter Bilinear transformation technique impulse invariance method Butterworth filter chebyshev filter.
UNIT III TEXAS PROCESSORS FOR DSP

Architecture -Addressing modes -Instruction set -Programming -Peripherals -Memory -Applications.
10 hrs.
UNIT IV ANALOG DEVICES PROCESSORS FOR DSP
10 hrs.
Architecture - Addressing modes - Instruction set Data address generator-PMD-DMD Bus exchange unit-ALU-MAC-Barrel Shifter Memory - ADC and DAC interfacing.
UNIT V BLACKFIN PROCESSORS
10 hrs.
Architecture of BF533, Peripherals, processor memory architecture, Computational units, DAG, Program sequencer.
TEXT BOOK:
1. John G.Proakis, Dimitris, G.Manolakis, "Digital Signal Processing: Principles, Algorithms and Applications", Prentice Hall; 4th edition, 2006.
REFERENCE BOOKS:
1. 2. 3. 4. A.V. Oppenheim and R.W. Schafer. "Discrete-Time Signal Processing", Prentice Hall, 3rd Edition, 2009. Lawrence R.Rabiner, BernardGold,"Theory And Application Of Digital Signal Processing", Prentice Hall, 3rd Edition, 2009. Venkatramani, "Digital Signal Processors", Tata Mc Graw-Hill, 1st Edition, 2001. Website: www.ti.com,www.analog.com.

SECX5004
REAL TIME OPERATING SYSTEM (Common to Embedded, Appl. Elec.)
L 3
T 1
P 0
Credits 4
Total Marks 100
UNIT I REVIEW OF OPERATING SYSTEMS
10 hrs.
Basic Principles-system calls-Files-Processes - Design and implementation of processes-Communication between processes - operating system structures.
UNIT II DISTRIBUTED OPERATING SYSTEMS

Topology-Network Types-Communication-RPC-Client server model-Distributed file systems
10 hrs.
UNIT III REAL TIME MODELS AND LANGUAGES
10 hrs.
Event based Process based- Graph models - Pettrinet models - RTOS tasks - RT scheduling - Interrupt processing-Synchronization - Control blocks-Memory requirements.
UNIT IV REAL TIME KERNEL
10 hrs.
Principles - Polled loop systems - RTOS porting to a target - Comparison and Study of RTOS - VxWorks and mCoS, Introduction to POSIX and OSEK standards
UNIT V RTOS AND APPLICATION DOMAINS
10 hrs.
RTOS for image processing - Embedded RTOS for voice over IP-RTOS for fault tolerant applications - RTOS for control systems
TEXT BOOK:
1. Hermann K, "Real time systems-design principles for distributed embedded Applications", Springer, 1st Edition, 1997. 2. Charles Crowley "operating systems - A design oriented approach", Tata Mc Graw Hill, 1st Edition, 2009.
REFERENCE BOOKS:
1. R.J.A. Buhr, D.L. Bailey, "An introduction to real time systems" Prentice Hall International, 1999. 2. CM Krishna,Kang G. Shin, "Real time Systems", Mc Graw Hill, 1st Edition, 1997. 3. Raymond J.A., Donald L Baily, "An introduction to real time operating systems", Prentice Hall International, 1999.

SECX5005
EMBEDDED SYSTEM DESIGN (Common to VLSI, E&C, Embedded, Appl. Elec.)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION
10 hrs.
Embedded system- characteristics of embedded system- categories of embedded system- requirements of embedded systems- challenges and design issues of embedded system- trends in embedded system- system integration- hardware and software partition- applications of embedded system- control system and industrial automationbiomedical-data communication system-network information appliances- IVR systems- GPS systems.
UNIT II DEVELOPMENT OF SOFTWARE ARCHITECTURE
10 hrs.
Development of software architecture simple round robin architecture- design and implementation of digital multimeter- round robin with interrupt architecture- implementation of communication bridge- function queue scheduling architecture- RTOS architecture.
UNIT III HARDWARE ARCHITECTURE
10 hrs.
Hardware architecture- block schematic of a typical hardware architecture- CPU-memeory-I/O Devices- design with microprocesors development-ADC- DAC interfacing LED/LCD interfacing. Case study of processor- 16 bit and 32 bit processor-DSP processor.
UNIT IV EMBEDDED SYSTEM PLATFORM AND DEVELOPMENT TOOLS
10 hrs.
Inter process communication- UART-IEEE 1394-IRDA-USB-PCI development tools- EPROM ERASER-signature validator- accelerated design for video accelerator.
UNIT V OVERVIEW OF DESIGN TECHNOLOGIES
10 hrs.
Design methodologies and tools- designing hardware and software components- system analysis and architecture design- system integration- structural and behavioral description smart cards.
TEXT BOOK:
1. Wayne wolf, Computers as components, Morgan Kaufmann publishers, 2nd Edition, 2008.
REFERENCE BOOKS:
1. Jean J.Labrosse, Embedded system building blocks, CMP books, 2nd Edition, 1999. 2. Arnold berger, Embedded system design, CMP books, 1st Edition, 2001. 3. Narayan and gong, Specifications and design of embedded systems, Pearson education, 2nd Edition, 1999.

SECX5006
PROGRAMMING IN MATLAB AND LABVIEW
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION TO MATLAB
10 hrs.
Matlab environmenttypes of files-constants and variables- Matrices and Vectors, matrix manipulations Cell Array Structure Array -Strings function Script files - Input and Output statements File input and output Opening & Closing Writing & Reading data from files.
UNIT II PROGRAMMING IN MATLAB
10 hrs.
Arithmetic, Relational and logical operators - Control statements IF, SWITCH CASE, BREAK, CONTINUE FOR loop While loop Matlab Debugger polynomials.
UNIT III PLOTTING AND SIMULINK
10 hrs.
Basic 2D plots modifying line styles markers and colors grids placing text on a plot Various / Special Mat Lab 2D plot types Semilogx Semilogy Log Log Polar Comet Multiple Plots-Subplots- Simulink-Simulink Modelling,Simulating a Model, Data Import/Export, State Space Modeling, Creating Sub-Systems.
UNIT IV INTRODUCTION TO LABVIEW
10 hrs.
Introduction to Virtual Instrumentation, advantages, architecture of a Virtual Instrument, block diagram, front panel, VIs, loading and saving VIs,debugging techniques, creating sub VIs, loops, shift registers, case structure, flat sequence.
UNIT V STRUCTURES, GRAPHS, FILE I/O AND INSTRUMENT CONTROL
10 hrs.
Formula node, expression node charts, arrays, clusters and graphs, string, file input output, data acquisition in Labview, instrument control in labview.
TEXT BOOK:
1. Raj kumar Bansal, Ashok kumar Goel, Manoj kumar Sharma, Matlab and its applications in engineering, Pearson Education, 1st edition, 2009.
REFERENCE BOOKS:
1. Stephen J.Chapmen, Matlab Programming for Engineers, Thomson learning, 4th Edition, 2008. 2. Rudra Pratap, Getting Started with MATLAB, Oxford University press, 2nd Edition, 1999. 3. Jeffrey Travis, Jim Kring, Labview for Everyone: Graphical Programming Made Easy and Fun, 3rd Edition, 2009.

Max. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each No choice. 30 marks Part B: 5 Questions from each of the five units of internal choice,each carrying 10 marks. (80% - Theory, 20% - Programs) 50 marks
SECX5007
EMBEDDED NETWORKING
L 3
T 1
P 0
Credits 4
Total Marks 100
UNIT I
10 hrs.
Embedded networking code requirements Communication requirements Introduction to CAN open CAN open standard Object directory Electronic Data Sheets & Device Configuration files Service Data Objectives Network management CAN open messages Device profile encoder.
UNIT II
10 hrs.
CAN open configuration Evaluating system requirements choosing devices and tools Configuring single devices Overall network configuration Network simulation Network Commissioning Advanced features and testing.
UNIT III
10 hrs.
Controller Area Network Underlying Technology CAN Overview Selecting a CAN Controller CAN development tools.
UNIT IV
10 hrs.
Implementing CAN open Communication layout and requirements Comparison of implementation methods Micro CAN open CAN open source code Conformance test Entire design life cycle.
UNIT V
10 hrs.
Implementation issues Physical layer Data types Object dictionary Communication object identifiers Emerging objects Node states.
TEXT BOOK:
1. Glaf P.Feiffer, Andrew Ayre and Christian Keyold Embedded Networking with CAN and CAN open, Embedded System Academy, 1st edition, 2008.
REFERENCE BOOKS:
1. Mohammad Farsi, Manuel Bernardo Barbosa, CANopen: Implementation Made Simple, Research Studies Press,1999. 2. Konrad Etschberger, Controller area network : basics, protocols, chips and applications, IXXAT Press,1st edition, 2001. 3. Wolfhard Lawrenz, CAN System Engineering: From Theory to Practical Applications, Springer, 1st edition,1997.

SCSX5031
CRYPTOGRAPHY AND NETWORK SECURITY (Common to VLSI, Embedded)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION AND MATHEMATICAL FOUNDATION
10 hrs.
Beginning with a simple communication game wresting between safeguard and attack Probability and Information Theory - Algebraic foundations Number theory.
UNIT II ENCRYPTION SYMMETRIC TECHNIQUES
10 hrs.
Substitution Ciphers - Transposition Ciphers - Classical Ciphers DES AES Confidentiality Modes of Operation Key Channel Establishment for symmetric cryptosystems.
UNIT III ENCRYPTION ASYMMETRIC TECHNIQUES AND DATA INTEGRITY TECHNIQUES
10 hrs.
Diffie-Hellman Key Exchange protocol Discrete logarithm problem RSA cryptosystems & cryptanalysis ElGamal cryptosystem Need for stronger Security Notions for Public key Cryptosystems Combination of Asymmetric and Symmetric Cryptography Key Channel Establishment for Public key Cryptosystems - Data Integrity techniques Symmetric techniques - Asymmetric techniques.
UNIT IV AUTHENTICATION
10 hrs.
Authentication Protocols Principles Authentication protocols for Internet Security SSH Remote logic protocol Kerberos Protocol SSL & TLS Authentication frame for public key Cryptography Directory Based Authentication framework Non - Directory Based Public-Key Authentication framework.
UNIT V SECURITY PRACTICES
10 hrs.
Protecting Programs and Data Information and the Law Rights of Employees and Employers Software Failures Computer Crime Privacy Ethical Issues in Computer Security.
TEXT BOOK
1. Wenbo Mao, Modern Cryptography Theory and Practice, Pearson Education, 1st Edition, 2006.
REFERENCE BOOKS:
1. Douglas R. Stinson, Cryptography Theory and Practice , 3rd Edition, Chapman & Hall/CRC,2006. 2. Charles B. Pfleeger, Shari Lawrence Pfleeger, Security in Computing, 4th Edition, Pearson Education, 2007. 3. Wade Trappe and Lawrence C. Washington, Intrduction to Cryptography with Coding Theory 2nd Edition, Pearson Education, 2007.

SECX6501
EMBEDDED SYSTEMS LAB - I
L 0
T 0
P 4
Credits 2
Total Marks 100
LIST OF EXPERIMENTS Using 89S52 Microcontroller

1. Read input from switches and display on LEDs 2. Make LEDs blink 3. Write a program for serial communication to communicate with PC 4. Different types of Encryption and Decryption schemes 5. Read data from temperature sensor and display values in PC 6. Simulate an elevator movement 7. Display message in LCD display 8. Set time in RTC and display on LCD
Using PIC Microcontroller

9. Make LEDs blink 10. Read input from switches 11. Display message in LCD 12. Simulate RTC and display in seven segment LEDs 13. Using PWM facility control a DC motor 14. Rotate a stepper motor with different speeds 15. Read data from temperature sensor and display values in PC
SECX6512
DESIGN PROJECT LAB
L 0
T 0
P 4
Credits 2
Total Marks 100
1. Experiments using VHDL/Verilog, RTOS, DSP processor, Matlab & Labview. 2. Mini projects using the above tools.
12
REGULATIONS 2010
SECX6502
EMBEDDED SYSTEMS LAB - II
L 0
T 0
P 4
Credits 2
Total Marks 100
Programs Using ARM Processor

1. Write a Simple Assembly Program for a. Addition b. Subtraction b. Multiplication d. Division. 2. Write a Program for a. 8-Bit Digital Output (LED Interface). b. 8-Bit Digital Inputs (Switch Interface). 3. Write a Program for a. 4 4 Matrix Keypad Interface. b. Buzzer Interface. c. Relay Interface. 4. Write a Program for character based LCD Interface. 5. Write a Program for Analog to Digital Conversion (On chip ADC) 6. Write a Program for I2-C Device Interface a. Serial EEPROM b. Seven Segment LED Display Interface c. Real Time Clock 7. Interfacing with Temperature Sensor 8. Stepper Motor Interface
Hands on Exercise Based on RTOS.

9. (a) Study and Implement Multitasking. (b) Write a Simple Program with Two Separate LED Blinking Tasks. 10. Study and Implement Priority Scheduling and OS TimeDelay Functions by writing 3 different UART Transmitting Tasks. 11. Implement OS Real Time Multitasking by writing a multitasking program with the tasks a. Interface RTC and Display on LCD First Line Continuously b. Interface ADC and Display on LCD second line Continuously 12. Implement OS Real Time Multitasking by Implementing the tasks. a. Read the Key input and display on seven segment LED. b. Read the ADC Analog input and Plot the Corresponding signal on a LCD.
SECX5021
ADVANCED DIGITAL SIGNAL AND IMAGE PROCESSING (Common to VLSI, NanoTech, Embedded)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I SPECTRUM ESTIMATION & PREDICTION
10 hrs.
Review of FIR, IIR, filters-Signal analysis using Fourier Transform - Periodogram- sample auto correlation- sum decomposition theorem- spectral factorization theorem- non parametric method- correlation method- co variance estimator- unbiased, consistant estimator- periodogram estimator- Bartlett spectrum estimation- Welch estimation- model based approach- AR- MA- ARMA signal modeling- parameter estimation using yule walker method- least mean square error criterion- Wiener filter-linear prediction- forward backward prediction- levinson recursion algorithm for solving toeplitz system of equations
UNIT II ADAPTIVE FILTERS
10 hrs.
FIR adaptive filter- Newton steepest descent method widrow hoff LMS adaptive algorithm- adaptive channel equalization- adaptive echo cancellor- adaptive noise cancellation- RLS adaptive filter- simplified IIR LMS adaptive filter.
UNIT III MULTI RATE SIGNAL PROCESSING
10 hrs.
Mathematical description of change of sampling rate- interpolation- decimation- continuous time model- direct digtal domain approach- decimation by an integer factor- interpolation by an integer factor- single and multi stage realization-poly phase realization- filter bank implementation- application to sub band coding.
UNIT IV IMAGE ENHANCEMENT AND RESTORATION
10 hrs.
Elements of digital image processing systems- elements of visual perception- structure of human eyeMonochrome vision model- image enhancement and restoration-Spatial domain method- histogram processing- spatial filtering- edge crispening- interpolation- homomorphic filtering degradation model- diagonalization of Circulant and Block Circu;ant Matrices-Algebraic Approach to restoration- constrained and unconstrained restoration- inverse filtering and wiener filter-Image morphology.
UNIT V IMAGE DATA COMPRESSION
10 hrs.
Fundamentals of coding- image compression model- fundamental coding theorem shannons coding, Huffman coding- pixel coding- predictive techniques- lossy and loseless predictive coding- variable length coding, bit plane coding- transform coding, zonal and threshold coding, image compression standard- CCITT and JPEG standards.
TEXT BOOK:
1. Monson H.Hayes, Statistical digtal signal processing and modeling, John Wiley Sons, 2002.
REFERENCE BOOKS:
1. 2. 3. 4. John G Proakis, Digtal signal processing, Pearson Prentice Hall, 2007. Simon Haykin, Adaptive filter theory, Mc.Graw Hill, 2nd Edition, 1998. Anil K Jain, Fundamental of Digtal image processing, Prentice Hall, 1989. Gonzalez R.C., Digtal image processing, Pearson Prentice Hall, 2008.

Max. Marks: 80 Part A: 6 Questions of 5 marks each No choice. Part B: 5 Questions from each of the five units of internal choice, each carrying 10 marks.
M.E. (EMBEDDED SYSTEMS) 14
Exam Duration: 3 hrs 30 marks 50 marks

REGULATIONS 2010
SECX5008
EMBEDDED PROCESSORS AND PERIPHERALS
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION
10 hrs.
Introduction to Processor and peripherals keyboards Multiplexed LED Displays Character LCD modules Time of Day Clock Timer Manager Discrete Inputs and Outputs Fixed point Math Analog Math.
UNIT II ANALOG DSP
10 hrs.
Analog DSP Blackfin Processor introduction, architecture, features, applications -instruction-set architecture and hardware micro architecture ADSP 2100 introduction, architecture, features, applications.
UNIT III ARM PROCESSOR
10 hrs.
Introduction, architecture, instruction set, addressing modes, applications Palm One OS5-based device with ARM processor ARM application processor ARM720T and ARM920T.
UNIT IV OPEN MULTIMEDIA APPLICATION PLATFORM
10 hrs.
Introduction, architecture, instruction set, addressing modes, applications OMAP5910 module overview, display specification, LCD controller operation, Lookup palette, color dithering, output FIFO, LCD controller pins, LCD controller registers, interface to LCD panel signal reset values.
UNIT V CASE STUDY
10 hrs.
Audio/video and VOIP application for multimedia application using OMAP TI-5012 TI OMAP Applications Processor - OMAP2420 and OMAP1710 architecture, features,and applications.
TEXT BOOK:
1. Jean J Labrose, Embedded Systems Building Blocks, CMP Books, second edition,2005.
REFERENCE BOOKS:
1. ARM reference manual from Texas Instruments, 2006. 2. OMAP reference manual from Texas Instruments, 2006. 3. Technical documents from Texas Instruments Hall for OMAP TI 5012, 2006.

SECX5031
ELECTROMAGNETIC INTERFERENCE & COMPATIBILITY (Common to VLSI, Embedded, Appl. Elec.)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I EMI ENVIRONMENT
10 hrs.
Introduction to EMI/EMC-Basics of electro Magnetic interference(EMI)Fundamentals of electromagnetic compatibility(EMC)-Radiation hazards Transients and other EMI sources, Transients, Electrostatics discharge (ESD) Tempest - Lightning Standards of EMI.
UNIT II EMI Coupling
10 hrs.
EMI from apparatus and circuits: Introduction-Electromagnetic emission-Appliances-noise from relays and switches-nonlinearities in circuits-Passive inter modulation-Cross talk in transmission lines-Transmission in power supply lines-Electromagnetic interference.
UNIT III EMI SPECIFICATION/STANDARDS AND MEASUREMENTS
10 hrs.
Units of specification-civilian standards and military standards.Basics of EMI measurements-EMI measurement tools-TEM cell-measurement using TEM cell-Reverberating chamber-GTEM cell-Anechoic chamber-Open area test site-RF absorbers-conducted interference measurements-conducted EMI from equipments-Experimental setup for measuring conducted EMI-Measurement of DM interferences.
UNIT IV EMI CONTROL TECHNIQUE

Shielding technique-Filter techniques-Grounding components-Isolation transformer-Transient suppressor. techniques-Bonding techniques-Cable
10 hrs.
connectors and
UNIT V EMC DESIGN OF PCB
10 hrs.
Designing for EMC:Introduction-Different techniques involved in designing for EMC-EMC guide lines for PCB designs-EMC design guide line for audio and control circuit design-EMC guide lines for RF design-EMC guidelines for power supply design-Mother board designs and propagation delay performance models
TEXT BOOK:
1. Bernhard Keiser, Principles of Electromagnetic Compatibility, Artech house, 3rd Edition, 1986.
REFERENCES BOOKS:
1. 2. 3. 4. 5. Henry W.Ott, Noise reduction Techniques in Electronics systems, Johnwiley and sons., New York, 1976. DonWhite consultant incorporate, Handbook of EMI/EMC, Vol 1-1985 Clayton R. Paul, Introduction to EMC, Wiley & sons, 2006. Sathyamurthy S., Basics of Electro Magnetic Compatibility, Society of EMC Engineers (India), 2003. Kodali V.P., "Engineering EMC Principles, Measurements and Technologies", IEEE Press, 2001.

SECX5084
FUZZY LOGIC AND NEURAL NETWORK (Common to VLSI, Embedded, Appl. Elec)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I FUNDAMENTALS OF ANN
10 hrs.
Introduction Neuron Physiology Specification of the brain Eye neuron model - Fundamentals of ANN Biological neurons and their artificial models Learning processes different learning rules types of activation functions training of ANN Perceptron model ( both single & multi layer ) training algorithm problems solving using learning rules and algorithms Linear seperability limitation and its over comings
UNIT II ANN ALGORITHM
10 hrs.
Back propagation training algorithm Counter propagation network structure & operation training applications of BPN & CPN -Statistical method Boltzmann training Cauchy training Hop field network and Boltzmann machine Travelling sales man problem - BAM Structure types encoding and retrieving Adaptive resonance theory Introduction to optical neural network Cognitron & Neocognitron
UNIT III APPLICATION OF ANN

Traffic control routing and scheduling Articulation Controller - Neural Acceleration Chip ( NAC )
10 hrs.
Hand written and character recognition Visual Image recognition - Communication systems call processing Switching
UNIT IV INTRODUCTION TO FUZZY LOGIC
10 hrs.
Introduction to fuzzy set theory membership function - basic concepts of fuzzy sets Operations on fuzzy sets and relations, classical set Vs fuzzy set properties of fuzzy set fuzzy logic control principles fuzzy relations fuzzy rules Defuzzification Time dependent logic Temporal Fuzzy logic ( TFC ) Fuzzy Neural Network (FANN) - Fuzzy logic controller Fuzzification & defuzzification interface.
UNIT V APPLICATION OF FUZZY LOGIC
10 hrs.
Application of fuzzy logic to washing machine Vaccum cleaner Water level controller temperature controller Adaptive fuzzy systems Fuzzy filters Sub band coding Adaptive fuzzy frequency hoping.
TEXT BOOK:
1. Freeman & Skapura, Neural Networks, Addison, Wesley, 1991.
REFERENCE BOOKS:
1. J.M.Zurada, Introduction to Artificial Neural Systems, West, 1992. 2. Simon Haykin, Neural Networks, Macmillan, 1994. 3. B.Yagnanarayana, Artificial Neural Networks, Prentice Hall of India, 2006.

Max. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each No choice. 30 marks Part B: 5 Questions from each of the five units of internal choice, each carrying 10 marks. (80% - Theory, 20% - Problems) 50 marks
SECX5085
BLUETOOTH TECHNOLOGY (Common to VLSI, Embedded)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION
10 hrs.
Introduction to Wireless technologies: WAP services, serial and parallel Communication, Asynchronous and synchronous communication, EDM, TFM, Spread spectrum technology. Introduction to Bluetooth: Specification, core protocols, cable replacement protocol.
UNIT II BLUETOOTH RADIO AND NETWORKING
10 hrs.
Bluetooth Radio: Type of Antenna, Antenna Parameters, Frequency hoping Bluetooth Networking: Wireless networking, Wireless network types, devices roles and states, adhoc network, scatter net.
UNIT III CONNECTION ESTABLISHMENT PROCEDURE
10 hrs.
Connection establishment procedure, notable aspects of connection establishment, Mode of connection, Bluetooth Security, Security architecture, Security level of services, profile and usage model: Generic access profile (GAP),SDA,serial profile, Secondary Bluetooth profile.
UNIT IV HARDWARE
Hardware: Bluetooth implementation, Baseband overview, packet format, Transmission
10 hrs.
Buffers, Protocol implementation: link manager protocol, logical link control Adaptation protocol, Host control interface, protocol interaction with layers.
UNIT V APPLICATIONS
10 hrs.
Programming with Java: Java Programming, J2ME architecture,Javax,Bluetooth package interface, classes, exceptions, Javax.obex package:interfaces, classes, Bluetooth services overview of IRDA, Home RF, Wireless LANs, JINI.
TEXT BOOK:
1. C.S.R.Prabhu and A.P.Reddi, Bluetooth Technology, Prentice Hall of India, 2004.
REFERENCE BOOKS:
1. Charels P.Pfleeger, Security in computing, Prentice Hall, 2003. 2. Andreas F.Molisch, Wideband wireless Digital Communication, Prentice Hall PTR, 2001. 3. George.V.Tsoulous, Adaptive Antennas for wireless Communication, IEEE Press, 2001.

SECX5009
MIXED SIGNAL EMBEDDED SYSTEMS
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION TO ANALOG AND MIXED SIGNAL CIRCUITS
10 hrs.
Design & Verification Applications Challenges - Market Perspective - Analog CMOS circuits - Current Mirrors Current and Voltage References - Bandgap References.
UNIT II CMOS AMPLIFIERS
10 hrs.
Opamps - High Performance CMOS amplifiers Comparators Characterization - Two stage open loop comparators - Discrete time comparators - High-speed comparators.
UNIT III SWITCHED CAPACITOR CIRCUITS
10 hrs.
Switched Capacitor (SC) Introduction - offset cancellation - clock feed - through - Switched Capacitor amplifiers Switched Capacitor Integrators - Switched Capacitor filters.
UNIT IV DATA CONVERTERS
10 hrs.
Introduction - Nyquist rate converters Over sampling converters - Pipelined/parallel converters - High speed ADC design, High speed DAC design and Mixed signal design for radar application - ADC and DAC modules used for LIGO.
UNIT V PHASE LOCKED LOOPS
10 hrs.
Introduction - Frequency Synthesizers - Design of PLL and Frequency Synthesizers PLL with voltage driven oscillator PLL with current driven oscillator ETPLL PLL synthesizer oscillator by MC14046B.
TEXT BOOKS:
1. Allen, CMOS Analog Circuit Design, Oxford, 2005. 2. Behzad Razavi, Design of Analog CMOS integrated circuit, Tata Mc Graw Hill,2004.
REFERENCE BOOKS:
1. 2. 3. 4. 5. Breems, Continuous-Time Sigma Delta Modulations for A/D Conversion,Kluwer,2002. Michelle Steyaert, Analog Circuit Design, Kluwer, 2003. Gray & Meyer, Analysis and Design of Analog Integrated Circuits, Wiley, 2004. Jacob Baker, CMOS Mixed-Signal Circuit Design, Wiley, 2004. Behzad Razavi, Design of Analog CMOS Integrated Circuit, Tata Mc Graw Hill, 2004.

SECX5010
DATA COMPRESSION TECHNIQUES
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION
10 hrs.
Special features of Multimedia Graphics and Image Data Representations Fundamental Concepts in Video and Digital Audio Storage requirements for multimedia applications -Need for Compression - Taxonomy of compression techniques Overview of source coding, source models, scalar and vector quantization theory Evaluation techniques Error analysis and methodologies
UNIT II TEXT COMPRESSION
10 hrs.
Compaction techniques Huffmann coding, Adaptive Huffmann Coding, Arithmatic coding, Shannon-Fano coding, Dictionary techniques, LZW family algorithms.
UNIT III AUDIO COMPRESSION
10 hrs.
Audio compression techniques - - Law and A- Law companding. Frequency domain and filtering Basic sub-band coding Application to speech coding G.722 Application to audio coding MPEG audio, progressive encoding for audio Silence compression, speech compression techniques Formant and CELP Vocoders.
UNIT IV IMAGE COMPRESSION
10 hrs.
Predictive techniques DM, PCM, DPCM: Optimal Predictors and Optimal Quantization Contour based compression Transform Coding JPEG Standard Sub-band coding algorithms - Design of Filter banks Wavelet based compression - Implementation using filters EZW, SPIHT coders JPEG 2000 standards - JBIG, JBIG2 standards.
UNIT V VIDEO COMPRESSION
10 hrs.
Video compression techniques and standards MPEG Video Coding I - MPEG 1 and 2 MPEG Video Coding II MPEG 4 and 7 Motion estimation and compensation techniques H.261 Standard, DVI technology PLV performance DVI real time compression, Packet Video.
TEXT BOOK:
1. Peter Symes, Digital Video Compression, Mc Graw Hill, 1st Edition, 2004. 2. Mark S.Drew, Ze-Nian Li, Fundamentals of Multimedia, Prentice Hall International, 1st Edition, 2003.
REFERENCE BOOKS:
1. Khalid Sayood, Introduction to Data Compression, Morgan Kauffman Harcourt India, 2nd Edition, 2000. 2. David Salomon, Data Compression The Complete Reference, Springer Verlag New York Inc., 2nd Edition, 2001. 3. Yun Q.Shi, Huifang Sun, Image and Video Compression for Multimedia Engineering - Fundamentals, Algorithms & Standards, CRC press, 2003.

SECX5011
ADVANCED EMBEDDED SYSTEMS
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION AND REVIEW OF EMBEDDED HARDWARE
10 hrs.
Terminology Gates Timing diagram Memory Microprocessor buses Direct memory access Interrupts Built interrupts Interrupts basis Shared data problems Interrupt latency - Embedded system evolution trends Round-Robin Round Robin with interrupt function Rescheduling architecture algorithm.
UNIT II REAL TIME OPERATING SYSTEM
10 hrs.
Task and Task states Task and data Semaphore and shared data operating system services Message queues timing functions Events Memory management Interrupt routines in an RTOS environment Basic design using RTOS.
UNIT III EMBEDDED HARDWARE, SOFTWARE AND PERIPHERALS
10 hrs.
Custom single purpose processors: Hardware Combination Sequence Processor design RT level design optimising software: Basic Architecture Operation Programmers view Development Environment ASIP Processor Design Peripherals Timers, counters and watch dog timers UART Pulse width modulator LCD controllers Key pad controllers Stepper motor controllers A/D converters Real time clock.
UNIT IV MEMORY AND INTERFACING
10 hrs.
Memory: Memory write ability and storage performance Memory types composing memory Advance RAM interfacing communication basic Microprocessor interfacing I/O addressing Interrupts Direct memory access Arbitration multilevel bus architecture Serial protocol Parallel protocols Wireless protocols Digital camera example.
UNIT V CONCURRENT PROCESS MODELS AND HARDWARE SOFTWARE CO-DESIGN
10 hrs.
Modes of operation Finite state machines Models HCFSL and state charts language state machine models Concurrent process model Concurrent process Communication among process Synchronization among process Implementation Data Flow model. Design technology; Automation synthesis Hardware software co-simulation IP cores Design Process Model.
TEXT BOOK:
1. David. E.Simon An Embedded Software Primer, Pearson Education, 2001.
REFERENCES BOOKS:
1. Frank Vahid and Tony Gwargie, Embedded System Design, John Wiley & sons, 2002. 2. Steve Heath, Embedded System Design, Newnes, 2nd Edition, 2004.

SECX5079
WIRELESS SENSOR NETWORKS (Common to CSE, Appl. Elec., Embedded)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I SENSOR NETWORK ARCHITECTURE

Concept of sensor network: Introduction, Applications, sensors
10 hrs.
Single node architecture: hardware and software components of a sensor node, Tiny OS operating system, nesC language. Wireless Sensor Network architecture: typical network architectures, data relaying strategies, aggregation, role of energy in routing decisions.
UNIT II ADDRESSING AND SYNCHRONISATION
10 hrs.
MAC layer strategies: MAC layer protocols, scheduling sleep cycles, energy management, contention-based protocols, schedule-based protocols, 802.15.4 standard. Naming and addressing: Addressing services, publish-subscribe topologies. Clock Synchronization: clustering for synchronization, sender-receiver and receiver-receiver synchronization, error analysis. Power Management: per node, system-wide, sentry services, sensing coverage
UNIT III LOCALIZATION
10 hrs.
Node Localization: absolute and relative localization, triangulation, multi-hop localization and error analysis, anchoring, geographic localization, target tracking, localization and identity management, Walking GPS, range free solutions. Data Gathering: Tree construction algorithms and analysis - Asymptotic capacity- Lifetime optimization formulations- Storage and retrieval. Deployment & Configuration: Sensor deployment, scheduling and coverage issues, self configuration and topology control.
UNIT IV ROUTING TECHNIQUES
10 hrs.
Routing: Agent-based routing, random walk, trace routing data centric, hierarchical, location-based, energy efficient routing Querying: Data collection and processing, collaborative information processing and group connectivity. Distributed Computation: Detection, estimation and classification problems - Energy-efficient distributed algorithms
UNIT V SENSOR NETWORK PLATFORMS AND TOOLS
10 hrs.
Sensor node hardware, programming challenges, node level software platforms, node level simulators, programming beyond individual nodes. Security: Privacy issues - Attacks and counter measures.
REFERENCES:
1. Feng Zhaoand Leonidas J Guibas, Wireless Sensor Networks Morgan Kaufmann Publishers and imprint of Elsevier, 2004. 2. C. S. Raghavendra, Krishna M. Sivalingam, Taieb F. Znati, Wireless Sensor Networks, 2nd Edition, Springer, 2004. 3. Holger Karl, Andreas Willig, Protocols and Architectures for Wireless Sensor Networks, John Wiley and Sons, 2005.

SECX5012 EMBEDDED COMMUNICATION SOFTWARE DESIGN
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I
10 hrs.
OSI Reference Model Communication Devices Communication Echo System Design Consideration Host Based Communication Embedded Communication System OS Vs RTOS.
UNIT II
10 hrs.
Software Partitioning Limitation of strict Layering Tasks & Modules Modules and Task Decomposition Layer2 Switch Layer3 Switch / Routers Protocol Implementation Management Types Debugging Protocols.
Unit III
10 hrs.
Tables & other Data Structures Partitioning of Structures and Tables Implementation Speeding Up access Table Resizing Table access routines Buffer and Timer Management Third Party Protocol Libraries.
Unit IV
10 hrs.
Management Software Device Management Management Schemes Router Management Management of Sub System Architecture Device to manage configuration System Start up and configuration.
Unit V
10 hrs.
Multi Board Communication Software Design Multi Board Architecture Single control Card and Multiple line Card Architecture Interface for Multi Board software Failures and Fault Tolerance in Multi Board Systems Hardware independent development Using a COTS Board Development Environment - Test Tools.
TEXT BOOK:
1. Sridhar.T, Designing Embedded Communication Software CMP Books, 2003.
REFERENCE BOOKS:
1. Sundararajan Sriram, Shuvra S. Bhattacharyya, Embedded multiprocessors, CRC Press, 2nd Edition, 2009 2. Jean J. Labrosse, Tammy Noergaard, Robert Oshana, Colin Walls, Keith Curtis, Embedded Software, Newnes, 1st Edition, 2007.

SICX5015
ADVANCED ROBOTICS AND AUTOMATION (Common to Appl. Elec., E&C, Embedded)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION
10 hrs.
Geometric configuration of robots - manipulators - drive systems - internal and external sensors - end effectors - control systems - robot programming languages and applications - Introduction to robotic vision.
UNIT II ROBOT ARM KINEMATICS
10 hrs.
Direct and Inverse Kinematics - rotation matrices - composite rotation matrices - Euler angle representation homogeneous transformation - Denavit Hattenberg representation and various arm configurations.
UNIT III ROBOT ARM DYNAMICS
10 hrs.
Lagrange - Euler formulation, joint velocities - kinetic energy - potential energy and motion equations - generalized DAlembert equations of motion.
UNIT IV ROBOT APPLICATONS Material Transfer & Machine Loading / Unloading
10 hrs.
General Consideration in robot material handling transfer applications Machine loading and unloading.
Processing Operations
Spot welding Continuous arc welding - spray coating other processing operations using robots.
UNIT V ASSEMBLY AND INSPECTION
10 hrs.
Assembly and robotic assembly automation Parts presentation methods assembly operation Compliance and the Remote Center Compliance(RCC) device Assembly system Configurations Adaptable, Programmable assembly system Designing for robotic assembly Inspection automation.
REFFERENCE BOOKS:
1. 2. 3. 4. 5. Fu, K.S.Gonazlez, R.C. and Lee, C.S.G. Robotics (Control, Sensing, Vision and Intelligence), Mc Graw Hill, 1968 (II printing). Wesley E Snyder R, Industrial Robots, Computer Interfacing and Control, Prentice Hall International Edition, 1988. Asada and Slotine, Robot analysis and Control, John Wiley and sons, 1986. Philippe Coiffet, Robot technology Vol.II (Modelling and control), Prentice Hall Inc., 1983. Groover M.P.Mitchell Weiss Industrial Robotics Technology Programming and Applications, Tata Mc Graw Hill, 1986.

Max.Marks: 80 Exam Duration: 3 hrs Part A : 6 Questions of 5 marks each No Choice. 30 marks Part B : 5 Questions from each of the five units of Internal choice, each carrying 10 marks. 50 marks
SECX5013
DSP INTEGRATED CIRCUITS (Common to Appl. Elec, Power, Embedded)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I DSP INTEGRATED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES
10 hrs.
Standard digital signal processors, Application specific ICs for DSP, DSP systems, DSP system design, Integrated circuit design. MOS transistors, MOS logic, VLSI process technologies, Trends in CMOS technologies.
UNIT II DIGITAL SIGNAL PROCESSING
10 hrs.
Digital signal processing, Sampling of analog signals, Selection of sample frequency, Signal-processing systems, Frequency response, Transfer functions, Signal flow graphs, Filter structures, Adaptive DSP algorithms, DFT-The Discrete Fourier Transform, FFT-The Fast Fourier Transform Algorithm, Image coding, Discrete cosine transforms.
UNIT III DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS
10 hrs.
FIR filters, FIR filter structures, FIR chips, IIR filters, Specifications of IIR filters, Mapping of analog transfer functions, Mapping of analog filter structures, Multirate systems, Interpolation with an integer factor L, Sampling rate change with a ratio L/M, Multirate filters. Finite word length effects -Parasitic oscillations, Scaling of signal levels, Round-off noise, Measuring round-off noise, Coefficient sensitivity, Sensitivity and noise.
UNIT IV DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES
10 hrs.
DSP system architectures, Standard DSP architecture, Ideal DSP architectures, Multiprocessors and multicomputers, Systolic and Wave front arrays, Shared memory architectures. Mapping of DSP algorithms onto hardware, Implementation based on complex PEs, Shared memory architecture with Bit serial PEs.
UNIT V ARITHMETIC UNITS AND INTEGRATED CIRCUIT DESIGN
10 hrs.
Conventional number system, Redundant Number system, Residue Number System. Bit-parallel and Bit-Serial arithmetic, Basic shift accumulator, Reducing the memory size, Complex multipliers, Improved shift-accumulator. Layout of VLSI circuits, FFT processor, DCT processor and Interpolator as case studies.
TEXT BOOK:
1. Lars Wanhammer, DSP Integrated Circuits, Academic press, New York, 1999.
REFERENCE BOOKS:
1. Oppenheim A.V., Discrete-time Signal Processing Pearson education, 3rd Edition, 2009. 2. Emmanuel C. Ifeachor, Barrie W. Jervis, Digital signal processing A practical approach, Pearson Edition, 2nd Edition, 2009. 3. Keshab K.Parhi, VLSI digital Signal Processing Systems design and Implementation, John Wiley & Sons, 2nd Edition, 1999.

SECX5086
WIRELESS AND MOBILE COMMUNICATIONS
L 3
T 0
P 0
Credits 3
Total Marks 100
Unit I
10 hrs.
Introduction: PCS Architecture Cellular Telephony Cordless telephony Mobility Management: Handoff Roaming Management Roaming Management under SS7 Roaming Management for CT2 Handoff Management: Detection and Assignment: Handoff Detection Strategies for Handoff Detection Channel Assignment. Radio Link Transfer: Link transfer types Hard Handoff Soft Handoff.
UNIT II
10 hrs.
IS-41 Network Signaling: Signaling System No.7 Interconnection and Message Routing Mobility Management using TCAP PCN / PSTN Call control using ISUP Intersystem Handoff. PACS Network Signaling: Network Elements Network Interfaces AIN / ISDN Internetworking Registration Call Origination Call Termination Intersystem Handoff Feature Interactions.
UNIT III
10 hrs.
GSM System GSM Architecture Location tracking and Call Setup Security Data services GSM Network Signaling GSM Mobility Management: GSM Location Update Mobility Databases VLR Identification Algorithm VLR Overflow Control.
Unit IV
10 hrs.
GPRS: GPRS Functional Groups GPRS Architecture GPRS Network Nodes GPRS Interfaces GPRS Procedures GPRS Billing. WAP: WAP model WAP Gateway WAP Protocols WAP UAProf and Caching.
Unit V
10 hrs.
3G Mobile Services: W-CDMA and CDMA 2000 Improvement on Core Network Quality of Service Wireless Operating System 3G Systems Wireless Local Loop: Architecture WLL Technologies WLL OAM Functions.
TEXT BOOK:
1. Yi-Bing Lin, Imrich Chlamtac, Wireless and Mobile Network Architectures, Wiley, 1st Edition, 2000.
REFERENCE BOOKS:
1. Kaveth Pahlavan, K.Prasanth Krishnamurthy, Principles of Wireless Networks, Pearson Education Asia, 2002 2. Leon Garcia, Widjaja, Communication Networks, Tata Mc Graw Hill, New Delhi, 2000. 3. William Stallings, Wireless Communications and Networks, Prentice Hall, 2002.

26
REGULATIONS 2010
SECX5014
EMBEDDED CONTROL SYSTEMS (Common to Appl.Elec., Power, Embedded)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION
10 hrs.
Controlling the hardware with software Data lines Address lines - Ports Schematic representation Bit masking Programmable peripheral interface Switch input detection 74 LS 244.
UNIT II INPUT-OUTPUT DEVICES
10 hrs.
Keyboard basics Keyboard scanning algorithm Multiplexed LED displays Character LCD modules LCD module display Configuration Time-of-day clock Timer manager - Interrupts - Interrupt service routines IRQ - ISR - Interrupt vector or dispatch table multiple-point - Interrupt-driven pulse width modulation.
UNIT III D/A AND A/D CONVERSION
10 hrs.
R 2R ladder - Resistor network analysis - Port offsets - Triangle waves analog vs. digital values - ADC0809 Auto port detect - Recording and playing back voice - Capturing analog information in the timer interrupt service routine - Automatic, multiple channel analog to digital data acquisition.
UNIT IV ASYNCHRONOUS SERIAL COMMUNICATION
10 hrs.
Asynchronous serial communication RS-232 RS-485 Sending and receiving data Serial ports on PC Low-level PC serial I/O module - Buffered serial I/O.
UNIT V CASE STUDIES: EMBEDDED C PROGRAMMING
10 hrs.
Multiple closure problems Basic outputs with PPI Controlling motors Bi-directional control of motors H bridge Telephonic systems Stepper control Inventory control systems.
TEXT BOOK:
1. Jean J. Labrosse, Embedded Systems Building Blocks: Complete and Ready-To-Use Modules in C, CMP, 2nd Edition, 2009.
REFERENCE BOOKS:
1. Ball S.R., Embedded microprocessor Systems Real World Design, Prentice Hall, 2nd Edition, 1996. 2. Herma K, Real Time Systems Design for distributed Embedded Applications, Kluwer Academic, 1st Edition, 1997. 3. Daniel W. Lewis, Fundamentals of Embedded Software where C and Assembly meet, Prentice Hall of India, 2nd Edition, 2002.

SECX5069
ANALYSIS AND MODELING OF DIGITAL SYSTEM USING VHDL (Common to Power, Embedded)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I VHDL FUNDAMENTALS
10 hrs.
Fundamental Concepts Modeling Digital Systems Domains and Levels of Modeling Modeling Languages VHDL Modeling concepts Scalar Data Types and Operations Constants and variables Scalar Types Type Classification Attributes and Scalar types Expressions and operators Sequential Statements If statements Case statements Null Statements Loop statements Assertion and Report statements.
UNIT II COMPOSITE DATA TYPES AND BASIC MODELING CONSTRUCTS
10 hrs.
Arrays Unconstrained Array types Array Operations and Referencing Records Basic Modeling Constructs Entity Declarations Architecture Bodies Behavioral Descriptions Structural Descriptions Design Processing. Case Study: A pipelined Multiplier Accumulator.
UNIT III SUBPROGRAMS AND PACKAGES
10 hrs.
Procedures Procedure Parameters Concurrent Procedure Call Statements functions Overloading Visibility of Declarations Packages and Use Clauses Package declarations Package bodies Use Clauses The predefined Aliases - Aliases for data objects Aliases for Non-Data Items. Case Study: A Bit-Vector Arithmetic Package.
UNIT IV SIGNALS, COMPONENTS AND CONFIGURATIONS
10 hrs.
Basic Resolved signals IEEE Std_Logic_1164 Resolved subtypes Resolved signal parameters Generic Constants Parameterizing behavior Parameterizing structure Components and Configurations Components Configuring component Instances Configuration Specification Generate Statements generating iterative structure Conditionally generating structures Configuration of generate Statements. Case Study: The DLX Computer System.
UNIT V ADTS AND FILES
10 hrs.
Access Types Linked Data structures Abstract Data Types using Packages Files and Input/Output Files The Package Textio Verilog.Case Study: Queuing Networks.
TEXT BOOK:
1. Peter J.Ashenden, The Designers Guide to VHDL, Morgan Kaufmann Publishers, San Francisco, Second Edition, 2001.
REFERENCE BOOKS:
1. Zainalabedin Navabi, VHDL Analysis and Modeling of Digital Systems, Mc Graw Hill International Editions, 2nd Edition, 1998. 2. James M.Lee, Verilog Quick start, Kluwer Academic Publishers, 2nd Edition, 1999.

Max. Marks: 80 Part A: 6 Questions of 5 marks each No choice. Part B: 5 Questions from each of the five units of internal choice, each carrying 10 marks.
M.E. (EMBEDDED SYSTEMS) 28
Exam Duration: 3 hrs 30 marks 50 marks

REGULATIONS 2010

Sathyabama University M.E. Embedded Systems Regulations 2010 Syllabus

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SATHYABAMA UNIVERSITY

(Established under section 3 of UGC Act, 1956)

Jeppiaar Nagar, Rajiv Gandhi Salai, Chennai - 119.

SYLLABUS MASTER OF ENGINEERING PROGRAMME IN EMBEDDED SYSTEMS (4 SEMESTERS) REGULATIONS 2010

FACULTY OF ELECTRONICS ENGINEERING

SATHYABAMA UNIVERSITY REGULATIONS 2010

M.E. (EMBEDDED SYSTEMS)

FACULTY OF ELECTRONICS ENGINEERING

RANGE OF MARKS FOR GRADES

CUMULATIVE GRADE POINT AVERAGE CALCULATION

where Ci - Credits for the subject

M.E. (EMBEDDED SYSTEMS)

FACULTY OF ELECTRONICS ENGINEERING

Final Degree is awarded based on the following :

FACULTY OF ELECTRONICS ENGINEERING

M.E - EMBEDDED SYSTEMS REGULATIONS 2010 - CURRICULUM SEMESTER I

M.E. (EMBEDDED SYSTEMS)

FACULTY OF ELECTRONICS ENGINEERING

TOTAL CREDITS FOR THE COURSE: 70

LIST OF ELECTIVE SUBJECTS

L Lecture hours; T Tutorial hours; P Practical hours; C Credits

M.E. (EMBEDDED SYSTEMS)

FACULTY OF ELECTRONICS ENGINEERING

Total Marks 100

UNIT III WAVELET TRANSFORMS

UNIT IV PROBABILITY AND RANDOM VARIABLES

UNIT V RANDOM PROCESS

UNIVERSITY EXAM QUESTION PAPER PATTERN

FACULTY OF ELECTRONICS ENGINEERING

ADVANCED DIGITAL SYSTEM DESIGN (Common to VLSI, Embedded, Appl. Elec.)

Total Marks 100

UNIT I SEQUENTIAL LOGIC CIRCUITS

UNIT II SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN

UNIT III ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN

UNIT IV PROGRAMMABLE LOGIC DEVICES

UNIT V STUDY OF FPGA AND XILINX

UNIVERSITY EXAM QUESTION PAPER PATTERN

FACULTY OF ELECTRONICS ENGINEERING

VLSI DESIGN (Common to VLSI, Embedded, NanoTech)

Total Marks 100

UNIVERSITY EXAM QUESTION PAPER PATTERN

FACULTY OF ELECTRONICS ENGINEERING

MICROCONTROLLERS SYSTEM DESIGN

Total Marks 100

UNIT I 8-BIT MICROCONTROLLER

UNIT II 8051 ALP AND APPLICATIONS

UNIT III PIC MICROCONTROLLER

UNIT IV PIC HARDWARE

UNIT V HIGH PERFORMANCE RISC ARCHITECTURE

UNIVERSITY EXAM QUESTION PAPER PATTERN

FACULTY OF ELECTRONICS ENGINEERING

Total Marks 100

UNIVERSITY EXAM QUESTION PAPER PATTERN

FACULTY OF ELECTRONICS ENGINEERING

Total Marks 100

UNIT I FOURIER TRANSFORM AND SPECTRUM ESTIMATION

UNIT III TEXAS PROCESSORS FOR DSP

UNIT IV ANALOG DEVICES PROCESSORS FOR DSP

UNIT V BLACKFIN PROCESSORS

UNIVERSITY EXAM QUESTION PAPER PATTERN

FACULTY OF ELECTRONICS ENGINEERING

REAL TIME OPERATING SYSTEM (Common to Embedded, Appl. Elec.)