CSULB -- CECS 285 -- Chapter Five Fall 2010 -- R.W.

Allison

8051 implements a Harvard Architecture

Instruction space (64K) Data space (2K) Instructions and data are in separate memories and the processor knows where to go (either an instruction fetch or an operand read/write)

As opposed to a Von Neumman Architecture

John von Neumann (1903 - 1957) Instruction and data memory shared the same address space (e.g. x86, Pentium architectures)

CSULB -- CECS 285 -- Chapter Five Fall 2010 -- R.W. Allison

FFFF

Lower 128 bytes (00-7F) Directly & Indirectly Addressable Upper 128 bytes (80-FF) Indirectly Addressable Only Special Function Registers (80-FF) Directly Addressable Only Expanded RAM Bytes (000-6FF) Indirectly Addressable Only by MOVX instructions with EXTRAM bit cleared in AUXR

64K Bytes FLASH

6FF

1792 Bytes XRAM

(Indirect Access)

FF

Upper 128
(Indirect Access)

FF

SFR
(Direct Access)

80 7F

80

Lower 128
Dir./Indir. Access
ACC, PSW, SP, Status and Control bits, Ports, Timers, Serial Control, etc.

0000

000

00

CSULB -- CECS 285 -- Chapter Five Fall 2010 -- R.W. Allison

Special Function Registers

F0 E0
F7 E7 F6 E6 F5 E5 F4 E4 F3 E3 F2 E2 F1 E1 F0 E0 D0

7F
General Purpose RAM

D0 B8 B0
7F 7E 7D 7C 7B 7A 79 78

D7 D6 D5 D4 D3 D2 -

B ACC PSW IP P3 IE P2 SCON P1

BC BB BA B9 B8

Bit Addressable Locations

30 2F 2E 2D 2C 2B 24 23 22 21 20
1F 18 17 10 0F 08 07 00

B7 B6 B5 B4 B3 B2 B1 B0 AF AC AB AA A9 A8

A8
A0 99 98 90 8D 8C 8B 8A 89 88 87 83 82 81 80

77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68

A7 A6 A5 A4 A3 A2 A1 A0 9F SBUF 9E 9D 9C 9B 9A 99 98

67 66 65 64 63 62 61 60

97 96 95 94 93 92 91 90 TH1 TH0 TL1 TL0 TMOD 8E 8D 8C 8B 8A 89 88 PCON DPH DPL SP 87 86 85 84 83 82 81 80

1F

1E 1D 1C 1B 1A 19 18

17 16 15 14 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08

07 06 05 04 03 02 01 00 Bank 3 Bank 2 Bank 1 Default register bank for R0-R7

8F

TCON

P0

CSULB -- CECS 285 -- Chapter Five Fall 2010 -- R.W. Allison

CPU can access data three ways Register Access Memory Access Immediate Access CPU has Eight Addressing Modes Immediate: operand is constant w/in instruction Register: operand is a register Direct: on-chip variable or hardware register Indirect: R0 and R1 may point to RAM Relative: Certain Jump Instructions Only Absolute: ACALL and AJMP only Long: LCALL and LJMP only Register Indirect Indexed Uses base register (PC or DPTR) and an offset to form the effective address

CSULB -- CECS 285 -- Chapter Five Fall 2010 -- R.W. Allison

Immediate

operand is constant w/in instruction E.g. mov A, #12 operand is a register E.g. add A, R7

Register Addressing
Direct Addressing (for accessing all the SFRs)

on-chip variable or hardware register E.g. mov P1, A mov 90h, A E.g. mov SCON, #55h mov 98h, #55h

Indirect (for RAM 00..FF and XRAM 0000..6FFF)

R0, R1 and DPTR may point to RAM/XRAM locations E.g. mov A, @R1 E.g. mov A, @DPTR

CSULB -- CECS 285 -- Chapter Five Fall 2010 -- R.W. Allison

Relative Addressing

(implicit with conditional and short jumps)

Two-byte instruction (2nd byte specifies PC relative offset -128 to +127) E.g. sjmp Inner_Loop (see previous slides)

Absolute Addressing

(only for jump or call instructions)

ACALL and AJMP instructions only Two byte instructions allow branch within 2k page of code memory by providing 11 lsb's of destination address (see previous slides)
(only for jump or call instructions)

Long Addressing

Indexed Addressing

LCALL and LJMP only Three byte instructions provide complete 16-bit destination address E.g. ljmp 8AF2h
(only for jump or movc instructions)

Uses a base register (PC or DPTR) and an offset (ACC) to form 16bit effective address for a JMP or MOVC Use to access data elements or tables in ROM E.g. movc A, @A+DPTR

CSULB -- CECS 285 -- Chapter Five Fall 2010 -- R.W. Allison

Table-lookup Functions

Example: create a table of all the values of x2 (where 0 x 15) Write a subroutine that returns the square of x, where x is in ACC.
ORG db ljmp ..... lcall ..... ..... ORG mov movc ret ORG 0000h 0, 1, 4, 9, 16, 25, 36, 49, 64, 81, 100, 121, 144, 169, 196, 225 Main

X_Squared

Main:

Calc_x2

Calc_x2:

1FE0h DPTR, #1FF0h A, @A+DPTR 1FF0h

0, 1, 4, 9, 16, 25, 36, 49, 64, 81, 100, 121, 144, 169, 196, 225

db

CSULB -- CECS 285 -- Chapter Five Fall 2010 -- R.W. Allison

More Table-lookup Functions

Example: create a table of all the values of sin (x) (where 0 x 90) Write a subroutine that returns sin(x), where x is in ACC.
;sin(x) values scaled by 255 ORG 0000h4, 9, 13, 18, 22, 27, 31, 35, 40 db 0, ljmp Main49, 53, 57, 62, 66, 70, 75, 79, 83 db 44, ..... ..... ..... 251,252,253,253,254,254,254,255,255,255,255 db lcall Calc_sin_x ..... ..... ORG 1E00h mov DPTR, #1E10h movc A, @A+DPTR ret ORG 1E10h db 0, 4, 9, 13, 18, 22, 27, 31, 35, 40 db 44, 49, 53, 57, 62, 66, 70, 75, 79, 83 ..... ..... db 251,252,253,253,254,254,254,255,255,255,255 ; 0 to 9 ; 10 to 19 ; ..... ; 80 to 90

sin_table Main:

Calc_sin_x:

; 0 to 9 ; 10 to 19 ; ..... ; 80 to 90

CSULB -- CECS 285 -- Chapter Five Fall 2010 -- R.W. Allison

Using BIT Directive

The BIT directive is a widely used directive to assign the bit-addressable RAM and I/O locations. The BIT directive allows a program to assign the RAM or I/O bit at the beginning of the program, making it easier to modify them (similar to EQU) Assume that RAM bit location 3Fh holds the status of whether there has been a phone call or not. If it is high, it means there has been a new call since it was last checked. Write a program to display appropriate messages if bit location 3Fh is high or low.
Phone_bit BIT jnb clr mov lcall sjmp mov lcall .....
ORG db ORG db

No_call: Exit:

3Fh Phone_bit, No_call Phone_bit DPTR, #400h Display Exit DPTR, #420h Display

;check to see if Phone_bit is high ;got a new message, so clear the bit ; load address of Yes_Msg ; and display the message ; and then exit ;Phone_bit was low, so load address ; of No_Msg and display it ;Now we will ......

Yes_Msg: No_Msg:

400h New Message Waiting, 0Dh, 0Ah, 0 420h No New Messages For You, 0Dh, 0Ah, 0

CSULB -- CECS 285 -- Chapter Five Fall 2010 -- R.W. Allison

10