Interrupts Interrupts

– Example:- Lecturer at work – Example:- Bus driver.

The bus driver is normally driving the bus. If interrupted by any
Imagine a man in a room thinking (for example preparing a of the passengers ringing the bell, she will..
lecture) He may be subject to interrupts. • (a) Pull in and stop at next bus stop.
• When interrupted he will, typically, deal with the • (b) Open doors
matter, and then go back to thinking. • (c) Wait for passenger(s) to leave
• Some interrupts he may chose to ignore or postpone. • (d) Shut door
For example students comes in and asks for D6 • (e) Pull out.
manual, and is told to come back later.
That is she will initiate a fixed sequence of responses before
• Telephone may ring - if too busy ignore it. resuming driving the bus.
• Some interrupts should not be ignored - fire alarm! A major component of a processor’s architecture is dedicated
to handling interrupts.
We need to be able to respond to interrupts intelligently..
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Interrupts on 8086 Interrupts on 8086

– On the 8086 an interrupt is caused when the intr pin goes
from 0 to 1.
– This interrupt can be disabled or masked by clearing the
Interrupt Flag using the cli instruction.
– Interrupts can be enabled by the sti instruction, which re-
enables interrupts.
– There is also an NMI control line (Non Maskable Interrupt)
for real emergencies.
– Interrupts are usually generated by I/O devices.
– When an interrupt occurs the CPU deals with it by:
(1) Pushing its status (that is its registers) unto the stack.
(2) Executes an ISR (Interrupt Service Routine)
(3) Restores its status from the stack, via the iret
instruction.
An ISR is a special kind of subroutine.

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Interrupts on 8086 Interrupts on 8086

When an interrupt occurs the CPU completes the current – At the very bottom of the 20-bit 8086 memory map lies the
instruction and then:- Interrupt jump table..
– (1) Disables the maskable interrupt cli
cli. (This prevents the
Intr Num Address Memory
interrupt from itself being interrupted. Programmer may over-
ride this behaviour by executing sti within the ISR). Full Address where
000B IP
000A IP code for ISR exists.
– (2) Saves the IP program counter, CS code segment 0009 CS
register, and Flags register on the stack. 2 0008 CS CS
0007 IP IP
– (3) Jumps to an address found in memory locations 4*N, 0006 IP
0005 CS
where N is the number of the interrupt. 1 0004 CS
0003 IP
– (4) Executes an ISR found at that address 0002 IP
0001 CS
– (5) At the end of the ISR executes an iret instruction which 0 0000 CS
pulls IP, CS and the Flags register off the stack, restoring
the CPU to the status it had before the interrupt occurred.

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 Example of D6 Timer Interrupts & I/O
Example:- The D6 Timer. – Synchronisation of tasks is a very important function on the
The D6 has a built-in timer device, that can generate interrupts PC. Visualise all the components in a typical computer trying
at fixed intervals. to communicate with the processor and the processor trying
It is set-up by writing to its Control Register to communicate with them.
(0FF56 in the I/O memory map), – A fast computer normally has to interact with relatively slow
I/O devices, slow because they are mechanical, or because
and its Count Register they have to work at a human friendly speeds.
(0FF52 in the I/O memory map). – Analogy:
– Consider a Robot Dish-Washer and three methods of
The out dx,al instruction does the job. This timer’s interrupt transferring plates to a Putter-awayer.
number is 8. – Assume that the DW is very fast and has other things to be
doing, and that the PA is quite slow, and subject to break-
<refer to program #3.5 in D6 Lab Book> downs.

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Interrupts & I/O Interrupts & I/O

– Method 1 - Programmed Input/Output using – Method 2 - Programmed I/O using polling.polling
Handshakes.
Handshakes • DW to PA: “Have you got it”
– A Handshake ensures that nothing gets dropped on the • PA to DW (immediately) “No” (DW puts plate down safely,
ground. quickly does a bit of other work, comes back again picks up
• DW hold out plate to PA and says “Have you got it?”. DW plate holds it out and asks again)
does not let go, and does nothing until it hears the PA reply • DW to PA: “Have you got it?”
“Yes”. • PA to DW: “No” (DW does a bit more work)
– Here the DW is frozen out until the PA replies “Yes”. It cannot • DW to PA: “Have you got it?”
proceed with the next task. This system is very inefficient use of
the DW’s time. • PA to DW: “No”
– The DW is halted waiting for the slow PA to respond. •.
•.
• DW to PA: “Have you got it?”
• PA to DW: “Yes!” (at last)
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Interrupts & I/O Summary

– Method 3 - Interrupt Driven I/O – So... the computer need not “freeze” while waiting for
• DW to PA: “There it is” (DW leaves plate down somewhere keyboard input. It can go off and execute other programs,
safe) etc. In fact a program that is waiting for an input or output to
• Now DW forgets about it, goes away and does something else complete requires very little attention from the CPU. The
until interrupted by PA CPU’s attitude can be summed up as “Get back to me when
you have something”.
• PA to DW: “I’ve dealt with that. I’m ready for another”. DW
washes/dries another dish and then – This is very important for multi-tasking systems. While one
task is waiting for I/O to complete, another can use CPU
• DW to PA: “There it is”. cycles. And most programs spend most of their time waiting
• etc. on I/O.
.... and that is how it is really done. – For example..... if you print a file from a Word Processor,
transfer of characters to the printer takes place in the
background using interrupts. You can still type away (and
run other programs).

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 Summary
What actually happens is:
– a) The CPU passes the next character into the printer interface’s data
register.
– (b) The CPU carries on processing.
– (c) When the character is printed and the printer is ready for another, an
interrupt is generated by the printer interface
– (d) Go to (a)
In the “old” days, it was common for the whole computer system to “Freeze”
until a print-out completed. So-called “CPU intensive” tasks can still be a
problem - for example a massive mathematical calculation. Since such a
program never waits for I/O other processes might never get a look in.
For this reason many Operating Systems use a timer which automatically
interrupts every few milliseconds, and then assigns CPU cycles to each
task on a “round-robin” basis.
How do we know which device interrupted?
• Problems
– How does the CPU know which device caused the interrupt
?
– Which interrupts should the computer respond to if more
than one is pending at the same time?
• Solutions
– On some simple systems a purely software approach is
taken: The CPU asks all the peripherals, one after another,
“Did you do it?” until it gets a reply “Yes – it was me”.
(Device polling).
– The order in which the devices are interrogated enforces an
inherent priority, and the programmer can control the
priorities by changing the order of interrogation.

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How do we know which device interrupted? How do we know which device interrupted?
• Example – Using this approach (Vector Interrupt) priorities are also
allocated in Hardware, using a method known as daisy-
chaining.

– The devices are interrogated in the order 1, 2, 3, 4. If there

should be interrupts pending from devices 2 and 4 (both are
pulling on the IRQ line), device 2 will be dealt with first.
– An alternative method uses Hardware. Here the device
causing the interrupt puts onto some special Bus wires a
Vector (binary pattern) indicating to the CPU the source of
the interrupt and hence the action to be taken. This is called
a Vectored Interrupt System.
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– The CPU responds to an interrupt request with an interrupt
acknowledge. Non-interrupting devices let the ACK signal
through. The first interrupting device
• Prevents the ACK signal travelling any further.
• Puts its own vector on the special Bus Lines.
– The Hardware approach is faster, but less flexible.
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How do we know which device interrupted? Software Interrupts

– The priorities, for example, depend on the physical proximity – These are interrupts not caused by external events, but
of the Interface card to the CPU. generated explicitly or implicitly from software.
– In particular a problem arises if an Interface Card is removed – The instruction int 3 causes the CPU to react as if an
to leave an empty slot – the interrupt Acknowledgement chain will associated device had caused an interrupt, and the
be broken, leading to obscure errors. appropriate ISR is called via the Jump Table. This is useful
for testing ISRs.
– The IBM PC uses a more sophisticated Hardware/Software – Example
approach, which attempts to combine the speed of hardware with – A divide instruction is being executed, when the CPU notices
the flexibility of Software.. that the divisor is Zero. This cannot be allowed! Int 0 is
automatically invoked.
– The appropriate ISR is at the address found in locations 0-
3, at the very bottom of the jump table.
– On a PC the default ISR prints out “Divide
Divide error”
error and crashes your
program.
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