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H.D.L LAB
For IV Semester B.E
INDEX SL.NO NAME OF THE EXPERIMENT 1 LOGIC GATES 2 ADDERS AND SUBTRACTORS 3 COMBINATIONAL DESIGNS a.2 TO 4 DECODER b.8 TO 3 ENCODER c.8 TO 1 MULTIPLEXER d.4 BIT BINARY TO GRAY CONVERTER e. MULTIPLEXER, DE-MULTIPLEXER, COMPARATOR 4 5 6 7 FULL ADDER(3 MODELING STYLES) 32 BIT ALU USING THE SCHEMATIC DIAGRAM FLIP-FLOPS (SR, D, JK AND T) 4 BIT BINARY,BCD COUNTERS SYNCHRONOUS & ASYNCHRONOUS COUNTERS ADDITIONAL EXPERIMENTS RING COUNTER JHONSON COUNTER INTERFACING DC AND STEPPER MOTOR EXTERNAL LIGHT CONTROL WAVEFORM GENERATION USING DAC SEVEN SEGMENT DISPLAY 48 51 52 56 PAGE NO 6 10 14
32 37 40 45
8 9 1 2 3 4
Opcode(3:0)
Enable . ALU should use the combinational logic to calculate an output based on the four bit op-code input. ALU should pass the result to the out bus when enable line in high, and tri-state the out bus when the enable line is low. ALU should decode the 4 bit op-code according to the given in example below.
OPCODE 1. 2. 3. 4. 5. 6. 7. 8. ALU OPERATION A+B A-B A Complement A*B A AND B A OR B A NAND B A XNOR B
5. Develop the HDL code for the following flip-flop, SR, D, JK, T.
6. Design 4 bit binary , BCD counters (Synchronous reset and asynchronous reset) and any sequence counters INTERFACING (at least four of the following must be covered using VHDL/Verilog) 1. Write HDL code display messenger on the given seven segment display and LCD and accepting Hex key pad input data. 2. Write HDL code to control speed, direction of DC and stepper motor. 3. Write HDL code to accept 8 channel analog signal, Temperature sensors and display the data on LC panel or seven segment display 4. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,)using DAC change the frequency and amplitude. 5. Write H DL code to simulate Elevator operation 6. Write HDL code to control external light using relays. *******************
HDL MANUAL
It is one of most popular software tool used to synthesize VHDL code. This tool Includes many steps. To make user feel comfortable with the tool the steps are given below: Double click on Project navigator. (Assumed icon is present on desktop). Select NEW PROJECT in FILE MENU. Enter following details as per your convenience Project name : sample Project location : C:\example Top level module : HDL In NEW PROJECT dropdown Dialog box, Choose your appropriate device specification. Example is given below: Device family : Spartan2 Device : xc2s200 Package : PQ208 TOP Level Module : HDL Synthesis Tool : XST Simulation : Modelsim / others Generate sim lang : VHDL In source window right click on specification, select new source Enter the following details Entity: sample Architecture : Behavioral Enter the input and output port and modes. This will create sample.VHDL source file. Click Next and finish the initial Project preparation. Double click on synthesis. If error occurs edit and correct VHDL code. Double click on Lunch modelsim (or any equivalent simulator if you are using) for functional simulation of your design. Right click on sample.VHDL in source window, select new source Select source : Implementation constraints file. File name : sample This will create sample. UCF constraints file. Double click on Edit constraint (Text) in process window. Edit and enter pin constraints with syntax: NET NETNAME LOC = PIN NAME Double click on Implement, which will carry out translate, mapping, place and route of your design. Also generate program file by double clicking on it, intern which will create .bit file. Connect JTAG cable between your kit and parallel pot of your computer.
EXPERIMENT NO. 1
WRITE HDL CODE TO REALIZE ALL LOGIC GATES AIM: Simulation and realization of all logic gates. COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply. Truth table with symbols
VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOG IC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gates is Port ( a,b : in std_logic; c,d,e,f,g,h,i : out std_logic); end gates; architecture dataflw of gates is begin c<= a and b; d<= a or b; e<= not a; f<= a nand b; g<= a nor b; h<= a xor b; i<= a xnor b; end dataflw;
VERILOG CODE module allgate ( a, b, y ); input a,b; output [1:6] y; assign y[1]= a & b; assign y[2]= a | b, assign y[3]= ~a , assign y[4]= ~(a & b), assign y[5]= ~(a | b), assign y[6]= a ^ b; endmodule
Procedure to view output on Model sim 1. After the program is synthesized create a Test bench, load the input. 2. Highlight the tbw file and click onto Modelsim Simulate behavioral model. 3. Now click the waveform and zoom it to view the result. Modelsim Output
Output (c to i) PROCEDURE TO DOWNLOAD ONTO FPGA 1) Create a UCF(User Constraints File). 2) Click on UCF file and choose assign package pins option as shown in the figure below.
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3) save the file. 4) Click on the module and choose configure device option. 5) The following icon will be displayed.
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6) Right click on the icon and select program option. 7) Program succeeded message will be displayed. 8) Make connections to main board and daughter boards( before configuring ) , give necessary inputs from DIP SWITCH and observe the output on LEDs. NET "a" LOC = "p74" ; NET "b" LOC = "p75" ; NET "c" LOC = "p84" ; NET "d" LOC = "p114" ; NET "e" LOC = "p113" ; NET "f" LOC = "p115" ; NET "g" LOC = "p117" ; NET "h" LOC = "p118" ; NET "i" LOC = "p121" ; Repeat the above Procedure to all the Programs. RESULT: The logic gates design have been realized and simulated using HDL codes.
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EXPERIMENT NO.2
AIM: Write a HDL code to describe the functions of Half adder, Half Subtractor and Full Subtractor. COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply. (a) HALF ADDER TRUTH TABLE INPUTS A 0 0 1 1 B 0 1 0 1 OUTPUTS S 0 1 1 0 C 0 0 0 1 BASIC GATES
BOOLEAN EXPRESSIONS: S=A B C=A B VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOG IC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HA is Port ( a, b : in std_logic; s, c : out std_logic); end HA; architecture dataflow of HA is begin s<= a xor b; c<= a and b; end dataflow; VERILOG CODE module ha ( a, b, s, c) input a, b; output s, c; assign s= a ^ b; assign c= a & b; endmodule
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(b)HALF SUBTRACTOR TRUTH TABLE INPUTS A B 0 0 1 1 BASIC GATES 0 1 0 1 OUTPUTS D Br 0 1 1 0 0 1 0 0 BOOLEAN EXPRESSIONS: D=A B _ Br = A B
VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOG IC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hs is Port ( a, b : in std_logic; d, br : out std_logic); end hs; architecture dataflow of hs is begin d<= a xor b; br<= (not a) and b; Dept of E&CE, SCE
VERILOG CODE module hs ( a, b, d, br) input a, b; output d, br; assign d= a ^ b; assign br= ~a & b; endmodule
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(C)FULL SUBTRACTOR TRUTH TABLE INPUTS A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 BOOLEAN EXPRESSIONS: D= A B C Br= A B + B Cin + A Cin
_ _
OUTPUTS D 0 1 1 0 1 0 0 1 Br 0 1 1 1 0 0 0 1
BASIC GATES
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EXPERIMENT NO.3
AIM: Write HDL codes for the following combinational circuits. COMPONENTS REQUIRED:FPGA board, FRCs, jumper and power supply. 3.a) 2 TO 4 DECODER BLACK BOX Y0 Sel 0 Sel 1 E 2 to 4 Decoder Y1 Y2 Y4
Simulation is done using Modelsim Waveform window : Displays output waveform for verification.
Output
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i0 en
Truth table
En 1 0 0 0 0 0 0 0 0 0 I7 X 1 1 1 1 1 1 1 1 0 I6 X 1 1 1 1 1 1 1 0 X I5 X 1 1 1 1 1 1 0 X X I4 X 1 1 1 1 1 0 X X X I3 X 1 1 1 1 0 x X X X I2 X 1 1 1 0 X X X X X I1 X 1 1 0 X X X X X X I0 X 1 0 X X X X X X X Z2 1 1 1 1 1 1 0 0 0 0 Z1 1 1 1 1 0 0 1 1 0 0 Z0 1 1 1 0 1 0 1 0 1 0 enx 1 1 0 0 0 0 0 0 0 0 V 1 0 1 1 1 1 1 1 1 1
VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder8_3 is Port ( i : in std_logic_vector(7 downto 0); en : in std_logic; Dept of E&CE, SCE
VERILOG CODE module enc8_3 (I, en, y, v); input [7:0]I; input en; output v; output [2:0]y; sig y; sig v; always @ (en, I) 18
end behavioral ;
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "en" LOC = "p84"; NET "i<0>" LOC = "p85"; NET "i<1>" LOC = "p86"; NET "i<2>" LOC = "p87"; NET "i<3>" LOC = "p93"; NET "i<4>" LOC = "p94"; NET "i<5>" LOC = "p95"; NET "i<6>" LOC = "p100"; NET "i<7>" LOC = "p74"; NET "enx" LOC = "p112"; NET "V" LOC = "p114"; NET "z<0>" LOC = "p113"; NET "z<1>" LOC = "p115"; NET "z<2>" LOC = "p117";
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Z 8:1Mux
Truth table
Sel2 0 0 0 0 1 1 1 1 Sel1 0 0 1 1 0 0 1 1 Sel0 0 1 0 1 0 1 0 1 VERILOG CODE module mux8_1 input [7:0]I; output [2:0]S; output y; input en; reg y; always @(en,S,I,y); begin if (en= =1) 20 Z A B C D E F G H
VHDL CODE entity mux8_1 is port(I: in std_logic_vector (7 downto 0); S: in std_logic_vector (2 downto 0); en: in std_logic; y: out std_logic); end mux8_1; architecture behavioral of mux8_1 is begin process (I,s,en) is begin Dept of E&CE, SCE
Output
3.d)4-BIT BINARY TO GRAY COUNTER CONVERTER Black Box clk 4 bit en Binary to rst Dept of E&CE, SCE gray
q(3 downto 0) 21
En 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
VHDL CODE
VERILOG CODE
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Binary to gray Output PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "b<0>" LOC = "p84"; NET "b<1>" LOC = "p85"; NET "b<2>" LOC = "p86"; NET "b<3>" LOC = "p87"; NET "g<0>" LOC = "p112"; NET "g<1>" LOC = "p114"; NET "g<2>" LOC = "p113"; NET "g<3>" LOC = "p115";
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Truth Table
Sel1 0 0 1 1 Sel0 0 1 0 1 Z a b c d VERILOG CODE module mux4_1(I0,I1,I2,I3,s2,s1,y,en) input I0,I1,I2,I3,s2,s1,en; output y; assigny<=((~s2)&(~s1)&en&I0)| ((~s2)&(s1)&en&I1)|(s2&(~s1)&en&I2)| (s2&s1&en&I3); dataflow of mux1 is endmodule
VHDL CODE entity mux1 is Port ( en,I : in std_logic; sel:in std_logic_vector(1downto 0); y : out std_logic); end mux1; architecture begin z<= I0 when sel= "00" else I1 when sel= "01" else I2 when sel= "10" else I3; end dataflow;
( 4:1)Multiplexer Output
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Y(3 downto 0)
Truth table
a 1 1 1 1 0 en 0 0 0 0 1 Sel1 0 0 1 1 X Sel0 0 1 0 1 X Y3 0 0 0 1 0 Y2 0 0 1 0 0 Y1 0 1 0 0 0 Y0 1 0 0 0 0
VHDL CODE entity demux is Port ( I,en : in std_logic; sel: in std_logic_vector(1 downto 0); y:outstd_logic_vector(3downto0)); end demux; architecture dataflow of demux is signal x: std_logic_vector( 1 downto 0); begin x<= en & a; y <="0001" when sel="00" and x="01" else "0010" when sel="01" and x="01" else "0100" when sel="10" and x="01" else "1000" when sel="11" and x="01" else "0000"; end dataflow;
VERILOG CODE module demux (s2,s1,I,en,y0,y1,y2,y3) input s2,s1,I,en; output y0,y1,y2,y3; assign y0=(~s2)&(~s1)& I& en; assign y1=(~s2)& s1& I& en; assign y2=s2&(~s1)& I & en; assign y3=s2& s1 & I & en; endmodule
NET "a" LOC = "p84"; NET "en" LOC = "p85"; NET "sel<0>" LOC = "p86"; NET "sel<1>" LOC = "p87"; NET "y<0>" LOC = "p112"; NET "y<1>" LOC = "p114"; NET "y<2>" LOC = "p113"; NET "y<3>" LOC = "p115";
Outp
a b 1bit Comparat or
L E G
Truth table
a 0 0 1 1
b 0 1 0 1
L 0 1 0 0
E 1 0 0 1
G 0 0 1 0
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VHDL CODE entity b_comp1 is port( a, b: in std_logic; L,E,G: out std_logic); end; architecture structural of b_comp1 is component not_2 is port( a: in std_logic; b: out std_logic); end component; component and_2 is port( a, b: in std_logic; c: out std_logic); end component; component xnor_2 is port( a, b: in std_logic; c: out std_logic); end component; signal s1,s2: std_logic; begin X1: not_2 port map (a, s1); X2: not_2 port map (a, s2); X3: and_2 port map (s1, b, L); X4: and_2 port map (s2, a, G); X5: xnor_2 port map (a, b, E); end structural;
VERILOG CODE module b_comp1 (a, b, L, E,G); input a, b; output L, E, G; wire s1, s2; not X1(s1, a); not X2 (s2, b); and X3 (L,s1, b); and X4 (G,s2, a); xnor X5 (E, a, b); end module
output NET "a" LOC = "p74" ; NET "b" LOC = "p75" ; NET "E" LOC = "p86" ; Dept of E&CE, SCE
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1-BIT COMPARATOR(DATA FLOW) VHDL CODE entity bcomp is port( a, b: in std_logic; c, d, e: out std_logic); end bcomp; architecture dataflow of bcomp is begin c<= (not a) and b; d<= a xnor b; e<= a and (not b); end dataflow; VERILOG CODE module bcomp (a, b, c, d, e) input a, b; output c, d, e; assign c= (~a) & b; assign d= ~(a ^ b); assign e= a & (~b); end module
3.h)4-BIT COMPARATOR Black Box a(3 to 0) 4bit Comparator x y b(3 to 0) z VERILOG CODE module comp(a,b,aeqb,agtb,altb); input [3:0] a,b; output aeqb,agtb,altb; reg aeqb,agtb,altb; always @(a or b) begin aeqb=0; agtb=0; if(a==b) aeqb=1; else if (a>b)
VHDL CODE entity compart4bit is Port ( a,b : in std_logic_vector(3 downto 0); aeqb,agtb,altb: out std_logic); end compart4bit; architecture Behavioral of compart4bit is begin process (a,b) begin if a > b then aeqb<='1';agtb<=0;altb<=0; elsif a < b then agtb<='1';aeqb<=0;altb<=0; Dept of E&CE, SCE
altb=0;
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RESULT: Combinational designs have been realized and simulated using HDL codes.
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EXPERIMENT NO.4
AIM: Write HDL code to describe the functions of a full Adder Using three modeling styles. COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply. DATA FLOW a b c FULL ADDER Black box Sum
Cout
Truth table
INPUTS a 0 0 0 0 1 1 1 1 VHDL CODE b 0 0 1 1 0 0 1 1 cin 0 1 0 1 0 1 0 1 OUTPUTS SUM 0 1 1 0 1 0 0 1 VERILOG CODE Cout 0 0 0 1 0 1 1 1
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BEHAVIORAL STYLE VHDL CODE entity fulladder beh is Port ( a,b,c : in std_logic; sum,carry : out std_logic); end fulladrbeh; architecture Behavioral of fulladrbeh is begin process( a,b,c) begin if(a='0' and b='0' and c='0') carry<='0'; elsif(a='0' and b='0' and c='1') carry<='0'; elsif(a='0' and b='1' and c='0') carry<='0'; elsif(a='0' and b='1' and c='1') carry<='1'; elsif(a='1' and b='0' and c='0') carry<='0'; elsif(a='1' and b='0' and c='1') carry<='1'; elsif(a='1' and b='1' and c='0') carry<='1'; else sum<='1'; carry<='1'; end if; end process; end Behavioral; Dept of E&CE, SCE then sum<='0'; then sum<='1'; then sum<='1'; then sum<='0'; then sum<='1'; then sum<='0'; then sum<='0'; VERILOG CODE module fulladd(cin,x,y,s,co); input cin,x,y; output s,co; reg s,co; always@(cin or x or y) begin case ({cin,x,y}) 3'b000:{co,s}='b00; 3'b001:{co,s}='b01; 3'b010:{co,s}='b01; 3'b011:{co,s}='b10; 3'b100:{co,s}='b01; 3'b101:{co,s}='b10; 3'b110:{co,s}='b10; 3'b111:{co,s}='b11; endcase end endmodule
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STRUCTURAL STYLE VHDL CODE entity fullstru is Port ( a,b,cin : in std_logic; sum,carry : out std_logic); end fullstru; architecture structural of fullstru is signal c1,c2,c3:std_logic; component xor_3 port(x,y,z:in std_logic; u:out std_logic); end component; component and_2 port(l,m:in std_logic; n:out std_logic); end component; component or_3 port(p,q,r:in std_logic; s:out std_logic); end component; begin X1: xor_3 port map ( a, b, cin,sum); A1: and_2 port map (a, b, c1); A2: and_2 port map (b,cin,c2); A3: and_2 port map (a,cin,c3); Dept of E&CE, SCE 32 VERILOG CODE module fa (x,y,z,cout,sum); input x,y,z; output cout,sum; wire P1,P2,P3; HA HA1 (sum(P1),cout(P2),a(x), b(y)); HA HA2 (sum(sum),carry(P3),a(P1),b(Z)); OR1 ORG (P2,P3, Cout); endmodule
NET "a" LOC = "P74"; NET "b" LOC = "P75"; NET "cin" LOC = "P76"; NET "cout" LOC = "P84"; NET "sum" LOC = "P85";
Sum output carryoutput RESULT: Three modeling styles of full adder have been realized and simulated using HDL. codes.
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EXPERIMENT NO. 5
AIM: Write a model for 32 bit ALU using the schematic diagram shown below. COMPONENTS REQUIRED:FPGA/CPLD board, FRCs, jumper and power supply. OPCODE 1 2 3 4 5 6 7 8 9 10 11 Black box A1(3 to 0) Dept of E&CE, SCE ALU OPERATION A+B A-B A Complement A*B A and B A or B A nand B A xor B Right shift Left Shift Parallel load
ALU 35
Truth table
Operation A+B A-B A or B A and B Not A A1*B1 A nand B A xor B Opcode 000 001 010 011 100 101 110 111 A 1111 1110 1111 1001 1111 1111 1111 0000 B 0000 0010 1000 1000 0000 1111 0010 0100 Zout 00001111 00001100 00001111 00001000 11110000 11100001 11111101 00000100
VHDL CODE entity alunew is Port( a1,b1:in std_logic_vector(3 downto 0); opcode : in std_logic_vector(2 downto 0); zout : out std_logic_vector(7 downto 0)); end alunew; architecture Behavioral of alunew is signal a: std_logic_vector( 7 downto 0); signal b: std_logic_vector( 7 downto 0); begin a<= "0000" & a1; b<= "0000" & b1; zout<= a+b when opcode ="000" else a-b when opcode ="001" else a or b when opcode ="010" else a and b when opcode ="011" else not a when opcode ="100" else a1 * b1 when opcode ="101" else a nand b when opcode ="110" else Dept of E&CE, SCE
VERILOG CODE module ALU ( a, b, s, en, y ); input signal [3:0]a, b; input [3:0]s; input en; output signal [7:0]y; reg y; always@( a, b, s, en, y ); begin if(en==1) begin case 4d0: y=a+b; 4d1: y=a-b; 4d2: y=a*b; 4d3: y={4 bww, ~a}; 4d4: y={4 d0, (a & b)}; 4d5: y={4 d0, (a | b)}; 4d6: y={4 d0, (a ^ b)}; 4d7: y={4 d0, ~(a & b)}; 4d8: y={4 d0, ~(a | b)}; 4d9: y={4 d0, ~(a ^ b)}; 36
RESULT: 32 bit ALU operations have been realized and simulated using HDL codes.
EXPERIMENT NO.6
AIM: Develop the HDL code for the following flipflop: T, D, SR, JK. COMPONENTS REQUIRED:FPGA board, FRCs, jumper and power supply. T FLIPFLOP Black Box t clk rst T ff
q qb
VHDL CODE entity tff is Port ( t,clk : in STD_LOGIC; Dept of E&CE, SCE
Truth table
Rst 1 1 1 0 T 0 1 X X Clk 1 1 No +ve edge X q q qb Previous state 0
VHDL CODE entity dff is Port ( d,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end dff; architecture Behavioral of dff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process (clk) variable temp: std_logic; begin if rising_edge(clk) then temp:=d; end if; q<=temp;qb<=not temp; end process; end Behavioral;
VERILOG CODE module dff(d,clk,rst,q,qb); input d,clk,rst; output q,qb; reg q,qb; reg temp=0; always@(posedge clk,posedge rst) begin if (rst==0) temp=d; else temp=temp; q=temp; qb=~ temp ; end endmodule
Truth table
clk X 1 1 d 1 1 0 q 1 1 0 qb 0 0 1
Output at rising edge NET "clk" LOC = "P18"; NET "d" LOC = "P74"; NET "q" LOC = "P84"; NET "qb" LOC = "P85"; Dept of E&CE, SCE 39
Truth table
rst 1 0 0 0 0 0 pr X 1 0 0 0 0 Clk X X 1 1 1 1 s X X 0 0 1 1 r X X 0 1 0 1 q 0 1 Qb 0 1 1 qb 1 0 Qbprevious 1 0 1
VHDL CODE entity srff is Port ( s,r,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end srff; architecture Behavioral of srff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; Dept of E&CE, SCE
VERILOG CODE module srff(s,r,clk,rst, q,qb); input s,r,clk,rst; output q,qb; reg q,qb; reg [1:0]sr; always@(posedge clk,posedge rst) begin sr={s,r}; if(rst==0) begin case (sr) 2'd1:q=1'b0; 2'd2:q=1'b1; 2'd3:q=1'b1; default: begin end 40
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Truth table
Rst 1 1 1 1 1 0 Clk 1 1 1 1 No+ve egde J 0 0 1 1 K 0 1 0 1 Q Previous 0 1 Qb Previous 0 Qb state 1 0 Q state 1
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Output(when input 00 and rising edge) NET "clk" LOC = "p18"; NET "j" LOC = "p84"; NET "k" LOC = "p85"; NET "rst" LOC = "p86"; NET "q" LOC = "p112"; NET "qb" LOC = "p114"; RESULT: Flip-flop operations have been realized and simulated using HDL codes
EXPERIMENT NO.7
AIM: Design 4 bit Binary, BCD counter ( Synchronous reset and Asynchronous reset and any sequence counters. COMPONENTS REQUIRED:FPGA board, FRCs, jumper and power supply. Dept of E&CE, SCE 43
Truth table
Rst 1 0 0 0 0 0 0 0 0 0 Clk X 1 1 1 1 1 1 1 1 1 Q 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
VHDL CODE entity bcd is Port ( clr,clk,dir : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0); tc : out STD_LOGIC); Dept of E&CE, SCE
VERILOG CODE module bcd(clr,clk,dir, tc, q); input clr,clk,dir; output reg tc; output reg[3:0] q; always@(posedge clk,posedge clr) 44
b)GRAY COUNTER Black Box 4 bit Binary to Dept of E&CE, SCE gray 45
VHDL CODE entity gray is Port ( clr,clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (2 downto 0)); end gray; architecture Behavioral of gray is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clr,clkd) variable temp:std_logic_vector(2 downto 0); begin if(clr='0') then if rising_edge(clkd(21)) then case temp is when "000"=> temp:="001"; when "001"=> temp:="011"; when "011"=> temp:="010"; when "010"=> temp:="110"; when "110"=> temp:="111"; when "111"=> temp:="101"; when "101"=> temp:="100"; when "100"=> temp:="000"; when others => null; end case; end if; else temp:="000"; end if; q<=temp; end process; end Behavioral;
VERILOG CODE module gray(clr,clk, q); input clr,clk; output reg[2:0] q; reg temp=3'd0; always@(posedge clk,posedge clr) begin if(clr==0) begin case(temp) 3'd0:q=3'd1; 3'd1:q=3'd3; 3'd2:q=3'd6; 3'd3:q=3'd2; 3'd6:q=3'd7; 3'd7:q=3'd5; 3'd5:q=3'd4; 3'd4:q=3'd0; endcase end else q=3'd0; end endmodule
Truth table
Rst Clk En Dept of E&CE, SCE B3 B2 B1 B0 G3 G2 G1 G0 46
Truth table
Clk X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rst 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Qout 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
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48
Output 0000
Output 1111
RESULT: Asynchronous and Synchronous counters have been realized and simulated using HDL codes.
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ADDITIONAL EXPERIMENTS
EXPERIMENT NO.8
AIM: Simulation and realization of Ring counter. COMPONENTS REQUIRED:FPGA board, FRCs, jumper and power supply. RING COUNTER
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INTERFACING PROGRAMS
1.WRITE A HDL CODE TO CONTROL THE SPEED, DIRECTION OF DC & STEPPER MOTOR
DC MOTOR VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dcmotr is Port ( dir,clk,rst : in std_logic; pwm : out std_logic_vector(1 downto 0); rly : out std_logic; row : in std_logic_vector(0 to 3)); end dcmotr; architecture Behavioral of dcmotr is signal countr: std_logic_vector(7 downto 0); signal div_reg: std_logic_vector(16 downto 0); signal ddclk,tick: std_logic; signal duty_cycle:integer range 0 to 255; begin process(clk,div_reg) begin if(clk'event and clk='1') then div_reg<=div_reg+'1'; end if; end process; ddclk<=div_reg(12); tick<= row(0) and row(1) and row(2) and row(3); process(tick) begin if falling_edge(tick) then case row is Dept of E&CE, SCE 52
NET "CLK" LOC="p18"; NET "RESET" LOC="p74"; NET "dir" LOC="p75"; NET "pwm<0>" LOC="p5"; NET "pwm<1>" LOC="p141"; NET "rly" LOC="p3"; NET "ROW<0>" LOC="p64"; NET "ROW<1>" LOC="p63"; NET "ROW<2>" LOC="p60"; NET "ROW<3>" LOC="p58"; PRODEDURE:1) Make connection between FRC 9 and FPGA board to the dc motor connector of VTU card 2 2) Make the connection between FRC 7 of FPGA board to the K/B connector of VTU card 2 3) Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTV card 2. 4) Connect the down loading cable and power supply to FPGA board. 5) Then open xilinx impact s/w, select slave serial mode and select the respective bit file and click program. 6) Make the reset switch on. 7) Press the Hex keys and analyze speed changes for dc motor. Dept of E&CE, SCE 53
STEPPER MOTOR library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity steppermt is Port ( clk,dir,rst : in std_logic; dout : out std_logic_vector(3 downto 0)); end steppermt; architecture Behavioral of steppermt is signal clk_div:std_logic_vector(15 downto 0); -- speed is maximum at 15 signal shift_reg:std_logic_vector(3 downto 0); begin process(clk) begin if rising_edge (clk) then clk_div <= clk_div+'1'; end if; end process; process(rst,clk_div(15)) -- speed is maximum at 15 begin if rst='0' then shift_reg<="0001"; elsif rising_edge (clk_div(15)) then if dir='1' then shift_reg <= shift_reg(0) & shift_reg(3 downto 1); else shift_reg<= shift_reg ( 2 downto 0) & shift_reg(3); end if; end if; end process; dout<= shift_reg; end Behavioral; NET "clk" LOC = "p18"; NET "dir" LOC = "p85"; NET "rst" LOC = "p84"; NET "dout<0>" LOC = "p7"; NET "dout<1>" LOC = "p5"; NET "dout<2>" LOC = "p3"; NET "dout<3>" LOC = "p141";
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3.WRITE HDL CODE TO GENERATE DIFFERENT WAVEFORMS(SAWTOOTH, SINE WAVE, SQUARE, TRIANGLE, RAMP ETC) USING DAC CHANGE THE FREQUENCY AND AMPLITUDE. SAWTOOTH
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sawtooth is Port ( clk,rst : in std_logic; dac : out std_logic_vector(0 to 7)); end sawtooth; architecture Behavioral of sawtooth is signal temp:std_logic_vector(3 downto 0); signal cnt:std_logic_vector( 0 to 7); begin process(clk) begin if rising_edge(clk) then temp<= temp+'1'; end if; end process; process (temp(3),cnt) begin Dept of E&CE, SCE 56
SQUARE
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity squarewg is Port ( clk,rst : in std_logic; dac : out std_logic_vector(0 to 7)); end squarewg; architecture Behavioral of squarewg is signal temp:std_logic_vector(3 downto 0); signal cnt:std_logic_vector(0 to 7); signal en: std_logic; begin process(clk) begin if rising_edge(clk) then temp<= temp+'1'; end if; end process; process(temp(3)) begin if rst='1' then cnt<="00000000"; elsif rising_edge (temp(3)) then if cnt< 255 and en='0' then cnt<=cnt+1; en<='0'; dac<="00000000"; elsif cnt=0 then en<='0'; else en<='1'; cnt<=cnt-1; dac<="11111111"; Dept of E&CE, SCE 57
TRIANGLE
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity triangwg is Port ( clk,rst : in std_logic; dac : out std_logic_vector(0 to 7)); end triangwg; architecture Behavioral of triangwg is signal temp: std_logic_vector( 3 downto 0); signal cnt: std_logic_vector(0 to 8); signal en:std_logic; begin process(clk) begin if rising_edge(clk) then temp<= temp+1; end if; end process; process( temp(3)) begin if rst='1' then cnt<="000000000"; elsif rising_edge(temp(3)) then cnt<=cnt+1; if cnt(0)='1' then dac<=cnt(1 to 8); else dac<= not(cnt( 1 to 8)); end if; end if; end process; end Behavioral;
RAMP
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Dept of E&CE, SCE 58
SINE WAVE
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sinewave is Port ( clk,rst : in std_logic; dac_out : out std_logic_vector(0 to 7)); end sinewave; architecture Behavioral of sinewave is signal temp: std_logic_vector(3 downto 0); signal counter: std_logic_vector(0 to 7); signal en: std_logic; begin process(clk) is begin if rising_edge (clk) then temp<= temp+'1'; end if; end process; Dept of E&CE, SCE
4.DAC
NET "CLK" LOC="p18"; NET "dac_out<0>" LOC="p27"; NET "dac_out<1>" LOC="p26"; NET "dac_out<2>" LOC="p22"; NET "dac_out<3>" LOC="p23"; NET "dac_out<4>" LOC="p21"; NET "dac_out<5>" LOC="p19"; NET "dac_out<6>" LOC="p20"; 59 NET "dac_out<7>" LOC="p4"; NET "rst" LOC="p74";
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1 2 3 4 5 6 7 8 9 10 FRC 1 2 3 4 5 6 7 8 9
FRC3 112 114 113 115 117 118 121 123 VCC GND
FRC4 122 124 129 126 132 136 134 139 VCC GND FRC8 96 99 101 102 103 116 120 131 133
Xilinx FPGA
FRC 1 2 3 4 9 10
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Constrints file 1. External Light Controller NET "cntrl" LOC="p74"; => FRC1 NET "light" LOC="p7"; => FRC9
2. DC MOTOR
NET "CLK" LOC="p18"; NET "RESET" LOC="p74"; NET "dir" LOC="p75"; NET "pwm<0>" LOC="p5"; NET "pwm<1>" LOC="p141"; NET "rly" LOC="p3"; NET "ROW<0>" LOC="p64"; NET "ROW<1>" LOC="p63"; NET "ROW<2>" LOC="p60"; NET "ROW<3>" LOC="p58";
3. STEPPER MOTOR
FRC1
FRC9
FRC7
NET "CLK" LOC="p18"; NET "dout<0>" LOC="p7"; NET "dout<1>" LOC="p5"; NET "dout<2>" LOC="p3"; NET "dout<3>" LOC="p141"; NET "RESET" LOC="p74"; NET "dir" LOC="p75";
4.DAC
FRC9
FRC1
NET "CLK" LOC="p18"; NET "dac_out<0>" LOC="p27"; NET "dac_out<1>" LOC="p26"; NET "dac_out<2>" LOC="p22"; NET "dac_out<3>" LOC="p23"; NET "dac_out<4>" LOC="p21"; NET "dac_out<5>" LOC="p19"; NET "dac_out<6>" LOC="p20"; NET "dac_out<7>" LOC="p4"; Dept of E&CE, SCE
FRC5
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NET "CLK" LOC="p18"; NET "disp_cnt<0>" LOC="p30"; NET "disp_cnt<1>" LOC="p29"; NET "disp_cnt<2>" LOC="p31"; NET "disp_cnt<3>" LOC="p38"; NET "disp<0>" LOC="p26"; NET "disp<1>" LOC="p22"; NET "disp<2>" LOC="p23"; NET "disp<3>" LOC="p21"; NET "disp<4>" LOC="p19"; NET "disp<5>" LOC="p20"; NET "disp<6>" LOC="p4"; NET "read_l_in<0>" LOC="122"; NET "read_l_in<1>" LOC="124"; NET "read_l_in<2>" LOC="129"; NET "read_l_in<3>" LOC="126"; NET "scan_l<0>" LOC="132"; NET "scan_l<1>" LOC="136"; NET "scan_l<2>" LOC="134"; NET "scan_l<3>" LOC="139";
FRC5
FRC4
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Cost/
Amount
VHDL LAB Multi-Vendor Universal Demo Board(kit includes motherboard along with downloading Cables)
10
12
20000/ 240000
1-02-05
Power supply, Xilinx FPGA-100k gate density Xilinx CPLD. Interfacing cards VTU interface-1 & VTU interface-2 along with above motherboards to perform all experiments of VHDL lab as per revised VTU syllabus 4.2.2
CM 640 Chipmax
04
06
1-02-05
01
01
1-02-05
Analyzer from AGILENT Technologies for on-chip debugging and real-time analysis of Xilinx FPGAs 4.2.4 SiMS-VLSI Universal VLSI Trainer/Evaluation Kit J Tag Cable 1No Power Supply 1No Operation Manual 1No 4.2.5 SiMS PLD (Spartan-II, CPLD cool runner, SPROM)(3 Nos) 4.2.6 SiMS-GPIO General purpose Integrated Interface module 4.2.7 Foundation Express: XILINX 6.1i Version: ISE Inclusive of all taxes
02
02
38,270.40
19-07-04
1 set each 01 01
1 set each 01 01
19-07-04 19-07-04
Grand Total:
5,44,949.40
66
Cost/
Amount
VHDL LAB Multi-Vendor Universal Demo Board(kit includes motherboard along with downloading Cables)
10
12
20000/ 240000
1-02-05
Power supply, Xilinx FPGA-100k gate density Xilinx CPLD. Interfacing cards VTU interface-1 & VTU interface-2 along with above motherboards to perform all experiments of VHDL lab as per revised VTU syllabus 4.2.2
CM 640 Chipmax
04
06
1-02-05
01
01
1-02-05
Analyzer from AGILENT Technologies for on-chip debugging and real-time analysis of Xilinx FPGAs 4.2.4 SiMS-VLSI Universal VLSI Trainer/Evaluation Kit J Tag Cable 1No Power Supply 1No Operation Manual 1No 4.2.5 SiMS PLD (Spartan-II, CPLD cool runner, SPROM)(3 Nos) 4.2.6 SiMS-GPIO General purpose Integrated Interface module 4.2.7 Foundation Express: XILINX 6.1i Version: ISE Inclusive of all taxes
02
02
38,270.40
19-07-04
1 set each 01 01
1 set each 01 01
19-07-04 19-07-04
Grand Total:
5,44,949.40
end Behavioral; entity gray is Port ( clr,clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (2 downto 0)); end gray; architecture Behavioral of gray is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clr,clkd) variable temp:std_logic_vector(2 downto 0); begin if(clr='0') then if rising_edge(clkd(21)) then case temp is when "000"=> temp:="001"; when "001"=> temp:="011"; when "011"=> temp:="010"; when "010"=> temp:="110"; when "110"=> temp:="111"; when "111"=> temp:="101"; when "101"=> temp:="100"; when "100"=> temp:="000"; when others => null; end case; end if; else temp:="000"; end if; q<=temp; end process; end Behavioral; Dept of E&CE, SCE 70
end Behavioral; entity ring is Port ( clk,clr,l : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0)); end ring; architecture Behavioral of ring is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clkd,clr) Dept of E&CE, SCE 71
end Behavioral;
module alu1(a,b,s,en,y); input [3:0] s,a,b; input en; output reg [7:0] y; always@(a,b,s,en,y) begin if(en==1) begin case(s) 4'd0:y=a+b; 4'd1:y=a-b; 4'd2:y=a*b; 4'd3:y={4'd0,~a}; 4'd4:y={4'd0,(a&b)}; 4'd5:y={4'd0,(a|b)}; 4'd6:y={4'd0,(a^b)}; 4'd7:y={4'd0,~(a&b)}; 4'd8:y={4'd0,~(a|b)}; 4'd9:y={4'd0,(~a^b)}; default:begin end endcase end else y=8'd0; end endmodule module bcd(clr,clk,dir, tc, q); input clr,clk,dir; output reg tc; output reg[3:0] q; always@(posedge clk,posedge clr) begin if(clr==1) q=4'd0; else begin if (dir==1)
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end Behavioral; entity gray is Port ( clr,clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (2 downto 0)); end gray; architecture Behavioral of gray is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clr,clkd) variable temp:std_logic_vector(2 downto 0); begin if(clr='0') then
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end Behavioral; entity ring is Port ( clk,clr,l : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0)); end ring; architecture Behavioral of ring is signal clkd:std_logic_vector(21 downto 0);
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end Behavioral; FLIP FLOPS entity dff is Port ( d,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end dff; architecture Behavioral of dff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process (clk) variable temp: std_logic; begin if rising_edge(clk) then temp:=d; end if; q<=temp;qb<=not temp; end process; end Behavioral; entity jkff is Port ( j,k,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end jkff;
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process(clk,rst) variable jk:std_logic_vector(1 downto 0); variable temp:std_logic:='0'; begin jk:=j&k; if (rst ='0')then if rising_edge(clk) then case jk is when "01"=> temp:='0'; when "10"=> temp:='1'; when "11"=> temp:=not temp; when others=> null; end case; end if; else temp:='0'; end if; q<=temp; qb<=not temp; end process; end Behavioral; entity srff is Port ( s,r,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end srff; architecture Behavioral of srff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clk,rst) variable sr:std_logic_vector(1 downto 0); variable temp1,temp2:std_logic:='0'; begin sr:=s&r; if (rst ='0')then if rising_edge(clk) then
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