Chapter 2 FPGA Fundaments

Overview -- Categories of Programmable Logic Devices (PLDs)

Simple Programmable Logic Devices (SPLDs) Complex Programmable Logic Devices (CPLDs) Field Programmable Gate Arrays (FPGAs)

PLD Categories

Design Factors Affecting PLD Architectural Selection

PLD Design

SPLD Device Overview

Simplest PLD (SPLD) devices
PAL: Programmable Array Logic PLA: Programmable Logic Array
Two logic gate array architectures Boolean ANDs and ORs

Simplified PAL Architecture

SPLD Characteristic

CPLD Device Overview

CPLD: Complex programmable Logic Device Complexity and density:
FPGAs > CPLDs >SPLDs

Basic CPLD Structure

Input/Output

Macro
Input/Output

Macro

Macro
Input/Output

Switch Fabric
Macro Macro Macro

Input/Output

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CPLD Decision Tree

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CPLD Characteristics

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CPLD to FPGA Comparison

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A Mapping of Functionality for CPLD and FPGAs

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Operational Categories of FPGA Devices

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FPGA Device Overview

FPGA were introduced in 1985 by Xilinx FPGA were developed to address the gap between CPLD and ApplicationSpecific Integrated Circuits (ASIC) devices

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Typical FPGA Characteristics

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FPGA Types

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One-time-programmable FPGA
OTP: One-Time-Programmable

ISP: In-System-Programming

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FPGA Manufacture

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SRAM-Based FPGA Architecture

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Fundamental FPGA Structure

Logic blacks Routing matrix and global signals I/O blocks Clock resources Multiplier Memory Advance features
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FPGA Logic Block Structure

Logic block: logic cell, slice, macrocell, and logic element (LE)

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Look-Up-Tables (LUTs) Element

A LUT is simply a memory element

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Combine Logic Block

Some example names for these combined logic block groups are: tile, configurable logic block (CLB), logic array block (LAB) and MegaLAB

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FPGA Routing Matrix and Global Signals

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Carry Chain Logic

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Global Low-Skew Routing Resources

These resources are typically
Limited in quantity Be reserved for high-performance and high-load signals

Global routing resources

Clock Control signals
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FPGA I/O Blocks

The ring of I/O banks is used to interface the FPGA device to external components

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I/O Block (IOB) Structure

An IOB includes input and output registers, control signals, muxes and clock signals Unused FPGA inputs should not be left floating

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I/O Block (IOB) Structure (cont)

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I/O Interface Standards

Single-ended and differential operational modes are typically supported Single-ended standards
PCI, LVTTL

Differential standards
LVDS, LVPECL
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IOB Configurable Feature

Pull-up or Pull-down Status of unused I/O I/O slew rate I/O drive strength Supported I/O standards Characteristic impedance termination
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FPGA Clock Resource

Clock manipulation can be implemented based on
Phase-locked loop (PLL) Delay-locked loop (DLL)

PLLs generate the desired phase or frequency output by a voltagecontrolled oscillator PLLs are inherently analog circuits
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FPGA Clock Resource (cont)

DLLs access signals from a calibrated tapped delay line circuit internal to the FPGA to produce the desired clock phase or frequency DLLs are digital circuits

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PLL and DLL Clocking

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Global Clocking and Regional Clocking

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FPGA Memory
Two primary types of memory within FPGAs Distributed memory
Takes advantage of the fact that LUT elements are implementation of SRAM memory blocks

Block memory
The implementation of dedicated SRAM memory blocks within the FPGA
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FPGA Memory (cont)

Memory elements embedded within FPGA are usually refereed to as
Block RAM, Embedded system block (ESB), System RAM and Content Addressable Memory (CAM)

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Advance FPGA Features

Enhanced clock features Intellectual property (IP) Embedded processors (Hard and Soft) Digital signal processing (blocks, tools, design flow)

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Generic FPGA Architecture

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Q&A

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