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ISSN : 2230-7109(Online) | ISSN : 2230-9543(Print)

IJECT Vol. 2, IssuE 1, MarCh 2011

Effect of Temperature Fluctuations on MOSFET Characteristics


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Dept. of EEE, YMCA University of Science & Technology, Faridabad, Haryana, India 2 Dept. of ECE, S.L.I.E.T, Longowal, Sangrur, Punjab, India

Nitin Sachdeva, 2Neeraj Julka

Abstract Temperature fluctuations alter threshold voltage, carrier mobility, and saturation velocity of a MOSFET. Temperature fluctuation induced variations in individual device parameters have unique effects on MOSFET drain current. Device parameters that characterize the variations in MOSFET current due to temperature fluctuations are identified in this paper for 180nm and 65nm CMOS technologies. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature variations. A design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is presented. Circuits display a temperature variation insensitive behavior when operated at a supply voltage 45% to 53% lower than the nominal supply voltage in a 180nm CMOS technology. Similarly, the optimum supply voltages are 68% to 69% lower than the nominal supply voltage for circuits in a 65nm CMOS technology. The optimum supply voltages are similar for a diverse set of circuits in both technologies. The proposed technique of operating large scale designs at an optimum supply voltage for diminishing the performance sensitivity to temperature fluctuations is demonstrated to be feasible. Keywords Propagation delay fluctuations, supply voltage optimization, temperature variation. I. Introduction Process and environment parameter variations in scaled CMOS technologies are posing greater challenges in the design of high performance integrated circuits. Variations can be categorized into die-to-die variations and within-die variations. Die-to-die fluctuations affect every element in an integrated circuit similarly. Alternatively, within-die variations cause a non-uniformity of physical characteristics among the devices temperature range from -40C to 150C [9]. Temperature variations affect the device characteristics of MOSFETs thereby varying the performance of integrated circuits. Propagation delay of a circuit is a function of the drain saturation current produced by active transistors. Performance of an integrated circuit under temperature fluctuations is determined by a set of device parameters. Temperature fluctuations alter threshold voltage, carrier mobility, and saturation velocity of a MOSFET [3]. Temperature fluctuation induced variations in individual device parameters have unique effects on MOSFET drain current. The dominant parameter that determines circuit speed varies with the device/circuit bias conditions. Variation of the drain current (IDS) of NMOS and PMOS transistors with supply voltage (VDD) and temperature in a 65nm CMOS technology is shown in Fig. 1. At higher supply voltages, the drain saturation current of a MOSFET degrades when the temperature is increased. Alternatively, provided that the supply voltage is low, MOSFET drain current increases with temperature, indicating a change in the dominant device parameter.

Fig. 1: Variation of MOSFET saturation current (IDS) with supply voltage (VDD) and temperature in a 65nm CMOS technology. |VDS| = |VGS| = VDD. Temperature dependent device parameters that determine MOSFET current characteristics in 180nm and 65nm CMOS technologies are identified in this paper. MOSFET current is characterized at elevated temperature and scaled supply voltages for two different CMOS technologies. A design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is proposed. The optimum supply voltages for achieving temperature variation insensitive delay characteristics for a diverse set of circuits in 180nm and 65nm CMOS technologies are presented. The paper is organized as follows. Temperature dependent device parameters that determine the drain current produced by a MOSFET are identified in Section 2. Effect of temperature fluctuations on the device and circuit characteristics in 180nm and 65nm CMOS technologies are examined in Section 3. The optimum supply voltages for temperature variation insensitive circuit performance are presented in Section 4. Finally, some conclusions are provided in Section 5. II. Factors influencing MOSFET Current Under Temperature Fluctuations Device parameters that are affected by temperature fluctuations, causing variations in the drain current produced by a MOSFET, are identified in this section. BSIM3 and BSIM4 MOSFET current equations are used for an accurate characterization of temperature fluctuation induced drain current variations in deeply scaled nanometer devices. The linear and saturation region drain current of a MOSFET is [5 - 7]

where Ids, Ids0, Rds, Vdseff, Vgsteff, Abulk, eff, V T, ESAT, and Leff are the drain current with short-channel effects, drain current of a long channel device, parasitic drain-to-source resistance, effective drain-to-source voltage, effective gate overdrive
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IJECT Vol. 2, IssuE 1, MarCh 2011

ISSN : 2230-7109(Online) | ISSN : 2230-9543(Print)

(VGSVt), parameter to model the bulk charge effect, effective carrier mobility, thermal voltage, electric field at which the carrier drift velocity saturates, and effective channel length, respectively. Threshold voltage, carrier mobility, and saturation velocity are [6,7]

supply voltages are 1.8V and 1.0V for the 180nm and 65nm CMOS technologies, respectively. TABLE 1 : Delay Variation with Temperature for circuits operating at the Nominal Supply Voltage (Vdd = 1.8v) in A 180NM CMOS Technology

TABLE 2: Delay Variation with Temperature for circuits operating at the Nominal Supply Voltage (Vdd = 1.0v) in A 65NM CMOS Technology

where Vt, KT1, KT1L, KT2, Vbseff, U0, Ute, TOXE, Ua, Ub, Uc, VSAT, AT, T0, and T are the threshold voltage, temperature coefficient for threshold voltage, channel length dependence of the temperature coefficient for threshold voltage, body-bias coefficient of threshold voltage temperature effect, effective substrate bias voltage, mobility at the reference temperature, mobility temperature exponent, electrical gate-oxide thickness, first order mobility degradation coefficient, second order mobility degradation coefficient, body effect of mobility degradation coefficient, saturation velocity, temperature coefficient of saturation velocity, reference temperature, and the operating temperature, respectively. KT1, KT1L, KT2, and AT are temperature independent empirical parameters while Ua, Ub, and Uc are temperature dependent [6,7]. Ua, Ub, and Uc are

Fig. 2 Fig. 3 Fig. 2: Gate overdrive variation with temperature for devices in 180nm and 65nm CMOS technologies. Fig. 3. Mobility variation with temperature for devices in 180nm and 65nm CMOS technologies. For circuits operating at the nominal supply voltage, variations in gate overdrive are smaller as compared to carrier mobility variations when the temperature fluctuates in both technologies. The MOSFET current and the circuit speed, therefore, degrade as the temperature is increased in both technologies. Propagation delay variations with temperature for the test circuits operating at the nominal supply voltage in 180nm and 65nm CMOS technologies are listed in Tables I and II, respectively. Gate overdrive variations with temperature are similar in both technologies. Alternatively, variations in carrier mobility are higher for devices in the 65nm CMOS technology as compared to variations observed in the 180nm CMOS technology. Therefore, for a die temperature spectrum of 25C to 125C, degradation of high temperature speed of the 65nm CMOS circuits is more significant than the speed degradation observed for the 180nm CMOS circuits, as listed in Tables I and II. When operating at the nominal supply voltage, the speed of circuits degrades by up to 19.6% and 54.5% as the temperature is increased from 25C to 125C in the 180nm and 65nm CMOS technologies, respectively. IV. Supply Voltage Optimization The results presented in Section 3 indicate that operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature variations.

where Ua1, Ub1, and Uc1 are the temperature coefficients of Ua, Ub, and Uc, respectively. As given by (3), (4), (5), and (6), absolute values of threshold voltage, carrier mobility, and saturation velocity degrade as the temperature is increased [5-7]. The saturation velocity is typically a weak function of temperature [3]. Threshold voltage degradation with temperature tends to enhance the drain current because of the increase in gate overdrive (VGS-Vt). Alternatively, degradation in carrier mobility tends to lower the drain current as given by (1) and (2). Effective variation of MOSFET current is, therefore, determined by the variation of the dominant device parameter when the temperature fluctuates. III. Device & Circuit Behavior under Temperature Fluctuations Influence of temperature fluctuations on the device and circuit characteristics in TSMC 180nm and Berkeley Predictive 65nm CMOS technologies are evaluated in this section. Test circuits are designed for equal low-to-high and high-to-low propagation delays at 125C. Temperature fluctuation induced gate overdrive and carrier mobility variations at the nominal supply voltage are shown in Figs. 2 and 3, respectively. The nominal

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IJECT Vol. 2, IssuE 1, MarCh 2011

TABLE 3 : Optimum supply voltages for Temperature variation insensitive Propagation Delay Characteristics in a 180NM CMOS Technology

TABLE 4 : Optimum supply voltages for Temperature variation insensitive Propagation Delay Characteristics in a 65NM CMOS Technology

delay variations in circuits operating at the nominal supply voltage for both 180nm and 65nm CMOS technologies. The MOSFET currents together with circuit switching speed degrade following the degradation of carrier mobility as the temperature is increased in both technologies. When operating at the nominal supply voltage, the propagation delay increases by up to 19.6% and 54.5% as the temperature is increased from 25C to 125C in 180nm and 65nm CMOS technologies, respectively. A new design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is presented. The supply voltages which compensate the temperature fluctuation induced variations of carrier mobility and threshold voltage are identified for circuits in two different technology generations. Circuits display a temperature variation insensitive behavior when operated at a supply voltage 45% to 53% lower than the nominal supply voltage in a 180nm CMOS technology. Similarly, the optimum supply voltages are 68% to 69% lower than the nominal supply voltage for circuits in a 65nm CMOS technology. The optimum supply voltages are similar for a diverse setof circuits in both technologies. The proposed technique of operating large scale designs at an optimum supply voltage for diminishing the performance sensitivity to temperature fluctuations is, therefore, feasible. References [1] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De, Parameter Variation and Impact on Circuits and Microarchitecture, Proceedings of the IEEE/ACM International Design Automation Conference, pp. 338342, June 2003. [2] R. Kumar, V. Kursun, Voltage Optimization for Temperature Variation Insensitive CMOS Circuits, Proceedings of the IEEE International MidwestSymposium on Circuits and Systems, August 2005. [3] Y. Cheng, K. Imai, M. C. Jeng, Z. Liu, K. Chen, C. Hu, Modeling Temperature Effects of Quarter Micrometre MOSFET in BSIM3v3 for Circuit Simulation, Semiconductor Science Technology, Vol. 12, pp. 1349-1354, November 1997. [4] Y. P. Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill, New York, 1999. [5] Y. Cao, T. Sato, D. Sylvester, M. Orshansky, C. Hu, "New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design," Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 201-204,June 2000. [6] W. Liu et al., BSIM3v3.2.2 MOSFET Model User Manual, Department of Electrical and Computer Engineering, University of California, Berkeley, 1999. [7] X. Xi et al., BSIM4.3.0 MOSFET Model User Manual, Department of Electrical and Computer Engineering, University of California, Berkeley, 2003. [8] A. Bellaouar, A. Fridi, M. J. Elmasry, K. Itoh, Supply Voltage Scaling for Temperature Insensitive CMOS Circuit Operation, IEEE Transactions on Circuits and Systems II, Vol. 45, No. 3, pp. 415-417, March 1998. [9] R. W. Johnson et al., The Changing Automotive Environment: High Temperature Electronics, IEEE Transactions on Electronics Packaging Manufacturing, Vol. 27, No. 3, pp. 164-176, July 2004.

A new design methodology based on scaling the supply voltage is proposed in this paper paper for suppressing the current variations due to temperature fluctuations. In order to compensate for the variations of carrier mobility, the sensitivity of gate overdrive to temperature fluctuations should be enhanced by lowering the supply voltage in both technologies. At the optimum supply voltage, gate overdrive variation completely compensates the variation of carrier mobility when the temperature fluctuates [2]. A transistor biased at this optimum voltage produces a temperature variation insensitive drain saturation current, as illustrated in Fig. 1. The optimum supply voltages for various test circuits in 180nm and 65nm CMOS technologies are listed in Tables III and IV, respectively. Circuits display a temperature variation insensitive behavior when operated at a supply voltage 45% to 53% lower than the nominal supply voltage in a 180nm CMOS technology. Similarly, the optimum supply voltages are 68% to 69% lower than the nominal supply voltage for circuits in a 65nm CMOS technology. The optimum supply voltages are similar for a diverse set of circuits in both technologies. The proposed technique of operating large scale designs at an optimum supply voltage for diminishing the performance sensitivity to temperature fluctuations is, therefore, feasible. Gap between the optimum and nominal supply voltages is higher in a 65nm CMOS technology due to the significantly higher mobility variations as compared to the 180nm CMOS technology. Performance variations in a speed centric design would, therefore, be more significant in a 65nm CMOS technology when temperature fluctuates. Alternatively, low power integrated circuits with deeply scaled supply voltages can be less sensitive to temperature fluctuations. V. Conclusions Temperature fluctuation induced propagation delay variations in CMOS integrated circuits are examined in this paper. Temperature dependent device parameters that cause variations in MOSFET drain current are identified. Variation of carrier mobility with temperature dominates the propagation
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IJECT Vol. 2, IssuE 1, MarCh 2011

ISSN : 2230-7109(Online) | ISSN : 2230-9543(Print)

Mrs. Nitin Sachdeva received her M-Tech. degree in VLSI Design and CAD from THAPAR INSTITUTE OF ENGG. & TECHNOLOGY (Deemed University) Patiala, Punjab, India in 2005. She is now working as Assistant Professor in Electronics Deptt.at YMCA UNIVERSITY OF SCIENCE AND TECHNOLOGY, Faridabad (Haryana) India. Her area of interest is VLSI DESIGN. She has published 15 research papers in International and National Conferences, guided several B-Tech projects, M-Tech projects & thesis. She is the coordinator of VLSI design group of post graduate program of YMCAUST,Faridabad. She is NATIONAL CHAMPION in Softball and awarded ROLL OF HONOUR by Chief Minister Punjab in year 1995-1996. Neeraj Julka is pursuing M-Tech. in ECE from Sant Longowal Institute of Engineering and Technology (Deemed to-be-University) Longowal, Sangrur (Punjab). His area of interest is Image Processing. He has published 4 research papers in International and National Conferences.

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