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VHDL BRAM / BROM

VHDL BRAM / BROM

To generate RAM and ROM using the BRAM's available in the FPGA, several methods can be used.
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For Xilinx you can use the CoreGen Program and for Actel the Libero IDE Write VHDL code which the synthesis tool can understand

The advantage of the second method is that it's target independent, but however it depends on the functionalities of the Synthesis tool.

Definition
ROM Definition
Single Port ROM with VHDL initialisation rom.vhd -- ROMs Using Block RAM Resources -- VHDL code for a ROM with one read port -library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity rom is port ( clk en addr data ); end rom;

: : : :

in in in out

std_logic; std_logic; std_logic_vector(5 downto 0); std_logic_vector(19 downto 0)

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architecture syn of rom type rom_type is array (63 downto 0) of std_logic_vector(19 downto 0); signal ROM : rom_type :=(X"0200A",X"00300",X"08101",X"04000",X"08601" ,X"0233A", X"00300",X"08602",X"02310",X"0203B",X"08300" ,X"04002", X"08201",X"00500",X"04001",X"02500",X"00340" ,X"00241", X"04002",X"08300",X"08201",X"00500",X"08101" ,X"00602", X"04003",X"0241E",X"00301",X"00102",X"02122" ,X"02021", X"00301",X"00102",X"02222",X"04001",X"00342" ,X"0232B", X"00900",X"00302",X"00102",X"04002",X"00900" ,X"08201", X"02023",X"00303",X"02433",X"00301",X"04004" ,X"00301", X"00102",X"02137",X"02036",X"00301",X"00102" ,X"02237", X"04004",X"00304",X"04040",X"02500",X"02500" ,X"02500", X"0030D",X"02341",X"08201",X"0400D"); signal raddr : std_logic_vector(5 downto 0); begin process(clk) begin if(clkevent and clk=1) then if(en=1) then raddr <= addr; end if; end if; end process; data <= ROM(conv_integer(raddr)); end syn;

Download rom.vhd Location : where you want File : rom.vhd

RAM Definition

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Dual-Port RAM with synchronous Read (Read Through) with no initialisation dp_ram_1.vhd --- Dual-Port RAM with Synchronous Read (ReadThrough) -library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dp_rams_oneclk is port( clk : in std_logic; we : in std_logic; a : in std_logic_vector(5 dpra : in std_logic_vector(5 di : in std_logic_vector(15 spo : out std_logic_vector(15 dpo : out std_logic_vector(15 end dp_rams_oneclk;

downto downto downto downto downto

0); 0); 0); 0); 0));

architecture syn of dp_rams_oneclk type ram_type is array(63 downto 0) of std_logic_vector(15 downto 0); signal RAM : ram_type; signal read_a : std_logic_vector(5 downto 0); signal read_dpra : std_logic_vector(5 downto 0); begin process(clk) begin if (clkeventandclk = 1) then if (we = 1) then RAM(conv_integer(a)) <= di; end if; read_a <= a; read_dpra <= dpra; end if; end process; spo <= RAM(conv_integer(read_a)); dpo <= RAM(conv_integer(read_dpra)); end syn;

Download dp_ram_1.vhd Location : where you want File : dp_ram_1.vhd

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Generic Dual-Port RAM (Write First) with two clocks, enables and write enables and initialisation with a binary file dp_ram_2.vhd --- Dual-Port Block Ram with two clocks -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE std.textio.all; ENTITY bramDualportWritefirst IS GENERIC( addressBitNb : positive := 8; dataBitNb : positive := 8; initFile : string := "bramInit.bin" ); PORT( clockA : in std_ulogic; enA : in std_ulogic; writeEnA : in std_ulogic; addressA : in std_ulogic_vector (addressBitNb-1 DOWNTO 0); dataInA : in std_ulogic_vector (dataBitNb-1 DOWNTO 0); dataOutA : out std_ulogic_vector (dataBitNb-1 DOWNTO 0); clockB : in std_ulogic; enB : in std_ulogic; writeEnB : in std_ulogic; addressB : in std_ulogic_vector (addressBitNb-1 DOWNTO 0); dataInB : in std_ulogic_vector (dataBitNb-1 DOWNTO 0); dataOutB : out std_ulogic_vector (dataBitNb-1 DOWNTO 0) ); END bramDualportWritefirst ; ARCHITECTURE bhv OF bramDualportWritefirst IS -- Define ramContent type type ramContentType is array(0 to (2**addressBitNb)-1) of bit_vector( dataBitNb-1 DOWNTO 0); -- Define function to create initvalue signal impure function ReadRamContentFromFile(ramContentFilenAme : in string) return ramContentType is FILE ramContentFile : text is in ramContentFileName; variable ramContentFileLine : line; variable ramContent : ramContentType; begin ramContent := (others => (others => '0')); -- check file extention if initfile'length >= 4 then -- check filename-length -- file extention = .bin if initfile(initfile'length-3 to initfile'length) = ".bin" then for i in ramContentType'range loop
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VHDL BRAM / BROM

readline(ramContentFile, ramContentFileLine); read(ramContentFileLine, ramContent(i)); end loop; return ramContent; end if; end if; end function; -- Declare ramContent signal shared variable ramContent: ramContentType := ReadRamContentFromFile( initfile); BEGIN -- Port A process(clockA) begin if clockA'event and clockA='1' then if enA = '1' then if writeEnA = '1' then dataOutA <= dataInA; ramContent(to_integer(unsigned(addressA))) := to_bitvector( dataInA,'0'); else dataOutA <= to_stdulogicvector(ramContent(to_integer(unsigned (addressA)))); end if; end if; end if; end process; -- Port B process(clockB) begin if clockB'event and clockB='1' then if enB = '1' then dataOutB <= to_stdulogicvector(ramContent(to_integer(unsigned( addressB)))); end if; end if; end process; END ARCHITECTURE bhv;

Download dp_ram_2.vhd Location : where you want File : dp_ram_2.vhd

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Initialisation
MIF-File
An ASCII text file (with the extension .mif) that specifies the initial content of a memory block (CAM, RAM, or ROM), that is, the initial values for each address. A MIF contains the initial values for each address in the memory. A separate file is required for each memory block. In a MIF, you are also required to specify the memory depth and width values. In addition, you can specify the radixes used to display and interpret addresses and data values.

HEX-File
Intel HEX is a file format for conveying binary information for applications like programming microcontrollers, EPROMs, and other kinds of chips. It is one of the oldest file formats available for this purpose, having been in use since the 1970s.

Format Start code The Start code exist only once per line at it's beginning. The Start code is : Byte count The Byte count indicates the number n of Raw Data bytes there are in the Data field. Address 16bit Address of the Data. If more Address bits are needed see Record Type 04. Record type There are six possible Record type:
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00: data record, contains data and 16-bit address. 01: End Of File record. Must occur exactly once per file in the last line of the file. The byte count is 00 and the data field is empty. Usually the address field is also 0000, in which case the complete line is ':00000001FF'. Originally the End Of File record could contain a start address for the program being loaded, e.g. :00AB2F0125 would cause a jump to address AB2F.

:00000001FF or

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VHDL BRAM / BROM

:020000010000FD
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02: Extended Segment Address Record, segment-base address (two hex digit pairs in big endian order). Used when 16 bits are not enough, identical to 8086 real mode addressing. The address specified by the data field of the most recent 02 record is multiplied by 16 (shifted 4 bits left) and added to the subsequent 00 record addresses. This allows addressing of up to a megabyte of address space. The address field of this record has to be 0000, the byte count is 02 (the segment is 16-bit). The least significant hex digit of the segment address is always 0. 03: Start Segment Address Record. For 8086 processors, it specifies the initial content of the CS:IP registers. The address field is 0000, the byte count is 04, the first two bytes are the CS value, the latter two are the IP value. 04: Extended Linear Address Record, allowing for fully 32 bit addressing (up to 4GiB). The address field is 0000, the byte count is 02. The two data bytes (two hex digit pairs in big endian order) represent the upper 16 bits of the 32 bit address for all subsequent 00 type records until the next 04 type record comes. If there is not a 04 type record, the upper 16 bits default to 0000. To get the absolute address for subsequent 00 type records, the address specified by the data field of the most recent 04 record is added to the 00 record addresses. 05: Start Linear Address Record. The address field is 0000, the byte count is 04. The 4 data bytes represent the 32-bit value loaded into the EIP register of the 80386 and higher CPU.

Data Raw Data of n bytes (n = Bytecount) at the given address in Hexadecimal format. Checksum The Checksum is two hex digits - the least significant byte of the two's complement of the sum of the values of all fields except fields 1 and 6 (Start code : byte and two hex digits of the Checksum). It is calculated by adding together the hex-encoded bytes (hex digit pairs), then leaving only the least significant byte of the result, and making a 2's complement (either by subtracting the byte from 0x100, or inverting it by XOR-ing with 0xFF and adding 0x01).

Example : : : : : 10 10 10 10 00 0100 0110 0120 0130 0000 00 00 00 00 01 214601360121470136007EFE09D21901 2146017EB7C20001FF5F160021480119 194E79234623965778239EDA3F01B2CA 3F0156702B5E712B722B732146013421 FF 40 88 A7 C7

Binary-File
An ASCII text file (with the extension .bin) that specifies the initial content of a memory block (CAM, RAM, or ROM), that is, the initial values for each address. This is the initialisation file used in the BRAM-VHDL examples. The file location has to be given in the generic called initFile. The file is witten in ASCII-binary format and one line has to be one line of the BRAM with the exact number of databits. Also each BRAM address has to be initialised in this file.
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An example of an 16 databit and 3 addressbit RAM 0000000000000000 0000000000000001 0000000000000010 0000000000000011 0000000000000100 0000000000000101 0000000000000110 0000000000000111

In VHDL
In order to initialise the BRAM you can also edit the VHDL code directly and initialise your Memory signal. Example: signal ROM : rom_type := (X"0200A",X"00300",X"08101",X"04000",X"08601",X "0233A", X"00300",X"08602",X"02310",X"0203B",X"08300",X "04002", X"08201",X"00500",X"04001",X"02500",X"00340",X "00241", X"04002",X"08300",X"08201",X"00500",X"08101",X "00602", X"04003",X"0241E",X"00301",X"00102",X"02122",X "02021", X"00301",X"00102",X"02222",X"04001",X"00342",X "0232B", X"00900",X"00302",X"00102",X"04002",X"00900",X "08201", X"02023",X"00303",X"02433",X"00301",X"04004",X "00301", X"00102",X"02137",X"02036",X"00301",X"00102",X "02237", X"04004",X"00304",X"04040",X"02500",X"02500",X "02500", X"0030D",X"02341",X"08201",X"0400D");

Restrictions
There are cetain restriction if you write BRAM's in VHDL

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VHDL BRAM / BROM

Syntesis Tool limitation

The VHDL Code for creating BRAM is read and understood by the synthesis tool. The mentioned code was tested in Xilinx XST Syntesis Tool. It has to be verified for other Synthesis tools like Simplify or Leonardo. The following limitaions are due the use of Xilinx XST.

Port limitation The BRAM's defined in VHDL can have multiple Read ports, but only ONE Write port.

Initialisation limitation The BRAM can only with the described Binary file format be initialised. The Synthesis tools doesn't support read and parsing files. Therefore a hex or mif file format can not be used. tschinz, programming, lang, vhdl, examples, bram

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