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A NOVEL HIGH SPEED DYNAMIC COMPARATOR WITH LOW POWER DISSIPATION AND LOW OFFSET
ABSTRACT
A new fully differential CMOS dynamic comparator using positive feedback suitable for pipeline A/D converters with low power dissipation, low offset, low noise and high speed is proposed. Inputs are reconfigured from typical differential pair comparator such that near equal current distribution in the input transistors can be achieved for a meta stable point of the comparator. Restricted signal swing clock for the tail current is also used to ensure constant currents in the differential pairs. Nearly 18mV offset voltage is easily achieved with the proposed structure making it favorable for flash and pipeline data conversion applications. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources, has a small power dissipation, less hysteresis band, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Test structures of the comparators, designed in GPDK 90 nm are measured to determine offset power dissipation and speed with 1.8 V are compared and the superior features of the proposed comparator are established

2. DESIGN OF A NOVEL HIGH SPEED DYNAMIC COMPARATOR WITH LOW POWER DISSIPATION FOR HIGH SPEED ADCs. ABSTRACT
A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with High Speed, low power dissipation and immune to noise than the previous reported work is proposed. Back to- back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Previous reported comparators are designed and simulated their DC response and Transient response in Cadence Virtuoso Analog Design Environment using GPDK 90nm technology. Layouts of the proposed comparator have been done in Cadence Virtuoso Layout XL Design Environment. DRC and LVS has been checked and compared with the corresponding circuits and RC extracted diagram has been generated. After that post layout simulation with 1V supply voltage has been done and compared the speed, power dissipation, Area, delay with the results before layout and the superior features of the proposed comparator are established.

3. Design and Modeling of I2C Bus Controller

ABSTRACT Design of I2C bus controller and the interface between the I2C devices i.e. microcontroller (AT89C51) and EEPROM (AT24C16). The I2C is a two wire serial protocol. Hence I2C components can be interfaced by using only two lines. First one is serial data (SDA) line and second is serial clock (SCL) line. The design architecture consists of a master controller and a slave. The master generates the START condition when SCL is HIGH and SDA is having a transition from HIGH to LOW. Master also generates STOP condition when SCL is in HIGH and SDA is having a transition from LOW to HIGH. Beside these two functions master also transfers and receives data to/from different slave devices. When master transmits data to slave receiver then it is known as WRITE mode of operation and when master receives data from slave transmitter then it is known as READ mode of operation. The microcontroller and EEPROM are interfaced through I2C bus. Data send, read and write particularly these operations are carried out and the behavior of I2C protocol is examined. In later section the I2C master controller is designed in verilg HDL. By describing the design in HDL, functional verification of the design can be done early in the design cycle. Since designers work at the high level language, they can optimize and modify the design module until it meets the desired functionality. The test bench program has to be developed to test the design module. The test bench gives the input to the design module & verifies the outputs. The test bench has to be written in such way to check the design module in all possible conditions.

4. Multilevel Power Estimation Of VLSI Circuits Using Efficient Algorithms

Abstract New and complex systems are being implemented using highly advanced Electronic Design Automation (EDA) tools. As the complexity increases day by day, the dissipation of power has emerged as one of the very important design constraints. Now low power designs are not only used in small size applications like cell phones and handheld devices but also in high-performance computing applications. Embedded memories have been used extensively in modern SOC designs. In order to estimate the power consumption of the entire design correctly, an accurate memory power model is needed. However, the memory power model commonly used in commercial EDA tools is too simple to estimate the power consumption accurately. For complex digital circuits, building their power models is a popular approach to estimate their power consumption without detailed circuit information. In the literature, most of power models are built with lookup tables. However, building the power models with lookup tables may become infeasible for large circuits because the table size would increase exponentially to meet the accuracy requirement. This thesis involves two parts. In first part it uses the Synopsys power measurement tools together with the use of synthesis and extraction tools to determine power consumed by various macros at different levels of abstraction including the Register Transfer Level (RTL), the gate and the transistor level. In general, it can be concluded that as the level of abstraction goes down the accuracy

of power measurement increases depending on the tool used. In second part a novel power modeling approach for complex circuits by using neural networks to learn the relationship between power dissipation and input/output characteristic vector during simulation has been developed. Our neural power model has very low complexity such that this power model can be used for complex circuits. Using such a simple structure, the neural power models can still have high accuracy because they can automatically consider the non-linear power distributions. Unlike the power characterization process in traditional approaches, our characterization process is very simple and straightforward. More importantly, using the neural power model for power estimation does not require any transistor-level or gatelevel description of the circuits. The experimental results have shown that the estimations are accurate and efficient for different test sequences with wide range of input distributions.

5. Phase Locked Loop Design as a Frequency Multiplier

ABSTRACT
High-performance digital systems use clocks to sequence operations and synchronize between functional units and between ICs. Clock frequencies and data rates have been increasing with each generation of processing technology and processor architecture. Phase locked-loops (PLLs) are widely used to generate well-timed on-chip clocks in high-performance digital systems. A PLL is a closed loop frequency system that locks the phase of an output signal to an input reference signal. PLLs are widely used in computer, radio, and telecommunications systems where it is necessary to stabilize a generated signal or to detect signals. The term lock refers to a constant or zero phase difference between two signals. The signal from the feedback path D f is compared to the input reference signal, IN f until the two signals are locked. If the phase is unmatched, this is called the unlocked state, and the signal is sent to each component in the loop to correct the phase difference. These components consist of the Phase Frequency Detector (PFD), the charge pump (CP), the low pass filter (LPF), the voltage controlled oscillator (VCO) and divide by counter. The PFD detects any phase differences in D f and IN f and then generates an error signal. According to that error signal the CP either increases or decreases the amount of charge to the LPF. This amount of charge either speeds up or slows down the VCO. The loop continues in this process until the phase difference between D f and IN f is zero or constantthis is the locked mode. After the loop has attained a locked status, the loop still continues in the process but the output of each component is constant. The output signal D f has the same phase and/or frequency as IN f .A divider can be used in the feedback path to synthesize a frequency different than that of the reference signal. The application I chose in designing the PLL was a frequency synthesizer. A frequency synthesizer generates a frequency that can have a different frequency from the original reference signal.

6. PHYSICAL DESIGN OF LOWPOWER OPERATIONAL AMPLIFIER

ABSTRACT
A CMOS single output two stage operational amplifier is presented which operates at 3 V power supply at 0.18 micron (i.e., 180 nm) technology. It is designed to meet a set of provided specifications. The unique behavior of the MOS transistors in sub- threshold region not only allows a designer to work at low input bias current but also at low voltage. This op-amp has very low standby power consumption with a high driving capability and operates at low voltage so that the circuit operates at low power. The op-amp provides a gain of 20.4dB and a -3db bandwidth of 202 kHz and a unity gain bandwidth of 2.15MHz for a load of 5 pF capacitor. This op-amp has a PSRR (+) of 85.0 dB and a PSRR (-) of 60.0 dB. It has a CMRR (dc) of -64.4 dB, and an output slew rate of 12.465 v/s. The power consumption for the op-amp is 1.18mW. The presented op-amp has a Input Common Mode Range(ICMR) of -1V to 2.4V. The op-amp is designed in the 180 nm technology using the umc 180 nm technology library. The layout for the above op-amp had been designed and the post layout simulations are compared with the schematic simulations. The proposed op-amp is a simple two stage single ended op-amp. The input stage of the op-amp is a differential amplifier with an NMOS pair. The second stage of the op-amp is a simple PMOS common source amplifier. The second stage is used to increase the voltage swing at the output. The op-amp uses a -3v Vdd and a -3v Vss and consumes a power of around 0.6mW (as per post layout simulations).

7. Power Grid Analysis in VLSI Designs

Abstract
Power has become an important design closure parameter in todays ultra low submicron digital designs. The impact of the increase in power is multi-discipline to researchers ranging from power supply design, power converters or voltage regulators design, system, board and package thermal analysis, power grid design and signal integrity analysis to minimizing power itself. This work focuses on challenges arising due to increase in power to power grid design and analysis. Challenges arising due to lower geometries and higher power are very well researched topics and there is still lot of scope to continue work. Traditionally, designs go through average IR drop analysis. Average IR drop analysis is highly dependent on current dissipation estimation. This work proposes a vector less probabilistic toggle estimation which is extension of one of the approaches proposed in literature. We have further used toggles computed using this approach to estimate power of ISCAS89 benchmark circuits. This provides insight into quality of toggles being generated. Power Estimation work is further extended to comprehend with various state of the art methodologies available i.e. spice based power estimation, logic simulation based power estimation, commercially available tool comparisons etc. We finally arrived at optimum flow recommendation which can be used as per design need and schedule. Todays design complexity high frequencies, high logic densities and multiple level clock and power gating - has forced design community to look beyond average IR drop. High rate of switching activities induce power supply fluctuations to cells in design which is known as instantaneous IR drop. However, there is no good analysis methodology in place to analyze this phenomenon. Ad

hoc decoupling planning and on chip intrinsic decoupling capacitance helps to contain this noise but there is no guarantee. This work also applies average toggle computation approach to compute instantaneous IR drop analysis for designs. Instantaneous IR drop is also known as dynamic IR drop or power supply noise. We are proposing cell characterization methodology for standard cells. This data is used to build power grid model of the design. Finally, the power network is solved to compute instantaneous IR drop. Leakage Power Minimization has forced design teams to do complex power gating multi level MTCMOS usage in Power Grid. This puts additonal analysis challenge for Power Grid in terms of ON/OFF sequencing and noise injection due to it. This work explains the state of art here and highlights some of the issues and trade offs using MTCMOS logic. It further suggests a simple approach to quickly access the impact of MTCMOS gates in Power Grid in terms of peak currents and IR drop. Alternatively, the approach suggested also helps in MTCMOS gate optimization. Early leakage optimization overhead can be computed using this approach.

8. Theory and Applications of Nonlinear Cellular Automata In VLSI Design Abstract

In recent years, Cellular Automata (CA) have been found as an attractive modeling tool for various applications, such as, pattern recognition, image processing, data compression, encryption and specially V LSI design & test. However, for all such applications, a special class of CA, called as linear/additive CA, has been utilized. Since linear CA limit the search space, we may not reach to the best result while searching for the solution to a problem. Nonlinear CA can be an alternative to linear/additive CA for achieving desired solutions in different applications. However, the nonlinear CA are yet to be characterized to _t the design for modeling an application. This thesis targets characterization of the nonlinear CA and utilizes the huge search space of nonlinear CA in developing applications in V LSI design. The interconnection among the CA cells (CA rules) are completely classified for efficient synthesis of reversible cellular automata. An analytical framework is developed to explore the properties of CA rules for 3-neighborhood 1-dimensional CA. It is found that in two-state 3-neighborhood CA, the CA rules fall into 6 groups depending on their potential to form reversible CA. The proposed classification of CA rules enables synthesis of reversible CA in linear time. An efficient design of Pseudo-Random Pattern Generators (PRPGs), based on the nonlinear reversible CA, has also been reported. The performance of the PRPG is evaluated with the battery of diehard tests. It is found that the proposed PRPG is the best among state-of-the-art designs in terms of its randomness quality. The structure of the proposed nonlinear CA based PRPG is utilized to design a cost optimal Test Pattern Generator (TPG) for a CUT (Circuit Under Test). The TPG can avoid patterns prohibited to the CUT and can ensure better fault e_ciency compared to existing designs. Further, we exploit the scalable structure of the nonlinear CA in designing TPGs for multiple cores without investing the disparate hardware for the different TPGs. The thesis reports a new BIST (Built-In Self-Test) structure, referred to as the

UBIST (Universal BIST). UBIST can generate any one of the four kinds of test patterns { (i) pseudo-random, (ii) pseudo-exhaustive, (iii) pseudo-random without PPS (Prohibited Pattern Set), and (iv) deterministic. Finally, the nonlinear CA theory is employed to address the issue of data services in cellular mobile network. CA act as an efficient query processor, resulting a hardwired solution to data service. The CA based query processor is found to be twice faster than the state-of-the-art designs with soft computation.

9. VHDL IMPLEMENTATION OF REED-SOLOMON CODING

ABSTRACT
Forward Error Correction technique depending on the properties of the system or on the application in which the error correcting is to be introduced. Error control coding techniques are based on the addition of redundancy to the information message according to a prescribed rule thereby providing data a higher bit rate. This redundancy is exploited by decoder at the receiver end to decide which message bit actually transmitted. Reed-Solomon codes are an important sub class of non binary Bose-Chaudhuri-Hocquenghem (BCH) codes. In digital communication, Reed-Solomon (RS) codes refer to as a part of channel coding that had becoming very significant to better withstand the effects of various channel impairments such as noise, interference and fading. This signal processing technique is designed to improve communication performance and can be deliberate as medium for accomplishing desirable system trade-offs. Galois field arithmetic is used for encoding and decoding of Reed Solomon codes. Galois field multipliers are used for encoding the information block. The encoder attaches parity symbols to the data using a predetermined algorithm before transmission. At the decoder, the syndrome of the received codeword is calculated. VHDL implementation creates a flexible, fast method and high degree of parallelism for implementing the Reed Solomon codes. The purpose of this thesis is to evaluate the performance of RS coding system using M-ary modulation over Additive White Gaussian Noise AWGN channel and implementation of RS encoder in VHDL. Computer simulation tool and MATLAB will be used to create and run extensively the entire simulation model for performance evaluation and VHDL is used to implemented the design of RS encoder.

10. Vlsi Implementation of Pipelined

Quadratic Function
ABSTRACT
Arithmetic circuits form an important class of circuits in digital systems. In particular, Multiplication is especially relevant since other arithmetic operators such as division or exponentiation, usually utilizes multiplier as building blocks. As the need for faster computation increases, the need for exploring ways to both quickly and accurately performing the multiplication also increases. So, here we go for Booths ordering than Booths multiplication. It provides high performance than other multiplication algorithms. Very often quadratic and cubic functions are used specifically in the field of cryptography, it is quite relevant at present to implement the pipelined quadratic function and therefore, it has been implemented.