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2004 Sergio Franco Ch.

3 - MOSFETs Page 1 of
MOS FIELD-EFFECT TRANSISTORS
2004 Sergio Franco
San Francisco State University
(Updated February 9, 2005)
No part of these notes may be reproduced, stored, transmitted, or distributed in any form or by any means, electronic
or in photocopy form, without the prior written permission by the author. 2004 Sergio Franco.
1. Device Structure
2. The Threshold Voltage
3. The Channels Characteristics
4. The i-v Characteristics of MOSFETs
The age of semiconductor electronics begun when the triode function (a controlled current source) was
implemented on a piece of semiconductor material. This occurred in 1947 with the invention of the
bipolar junction transistor (BJT), the first working realization of the semiconductor triode concept.
However, neither is the BJT the only transistor type possible, nor was it the first transistor to be
conceived. In fact, as early as 1925, Julius Lilienfeld patented a device of the type nowadays known as
the field-effect transistor (FET). However, because of fabrication difficulties at the time, he could never
get it to work. It took another 35 years or so before Dawon Kahng and John Atalla of Bell Laboratories
demonstrated, in 1960, the first FET of the so called metal-oxide-semiconductor (MOS) type, or
MOSFET for short.
The closest MOSFET counterpart of the vacuum-tube triode is what is nowadays known as the n-
channel depletion-type MOSFET (n-channel DMOSFET). Briefly stated, a DMOSFET consists of a thin
layer of n-type material called the channel, which forms a parallel-plate capacitor with an electrode called
the gate. One end of the channel, called the source, acts as a copious source of free electrons, which are
designed to flow to the opposite end of the channel, aptly called the drain. The roles of source and drain
are similar to those of emitter and collector in the BJT, or cathode and plate in the triode. The role of the
gate, similar to that of the base in the BJT or the grid in the triode, is to modulate the channels conduct-
ivity and thus control the current flow from source to drain. Specifically, driving the gate voltage
negative will induce a positive charge in the channel, at the expense of a reduction in the concentration of
free electrons there. For a sufficiently negative gate voltage, the channel will be depleted of free electrons
and current flow will cease altogether. By a hydraulic analogy, FET behavior can be likened to a garden
hose being squeezed for the purpose of controlling water flow, or even shutting it off completely.
Following the successful demonstration of the first MOSFET, the new technology was put to use
especially in those applications in which the advantages of smaller size and lower power consumption of
the MOSFET made it competitive with its BJT counterpart. The first battery-powered electronic
calculators and wristwatches made use precisely of this new technology. Also, a new digital integrated-
circuit (IC) family known as complementary MOS (or CMOS for short) was introduced by RCA as a low-
power alternative to the existing IC bipolar families of the TTL and ECL types. In 1971 Intel used MOS
technology to develop the first microprocessor. Since then, IC electronics has advanced exponentially
and has penetrated virtually every aspect of modern life. This impressive growth has been governed by
Moores law, roughly stating that thanks to continued advances in IC fabrication, the number of devices
that can be integrated on a given chip area doubles every approximately 18 months. Originally
2004 Sergio Franco Ch. 3 - MOSFETs Page 2 of
formulated in 1965, this law still holds to this day, though it has been observed that technology is bound
to approach physical limits that will eventually lead to the demise of this law.
Over the years, the MOSFET has overtaken its BJT predecessor especially in high-density ICs
electronics, thanks to the aforementioned MOSFET advantages of smaller size and lower power
consumption. Nonetheless, there are applications such as high-performance analog electronics, in which
the BJT continues to be the preferred transistor type. To exploit the advantages of both BJTs and
MOSFETs, the two device types are sometimes fabricated simultaneously on the same chip. The
resulting technology, aptly called biCMOS technology, provides even greater design opportunities than
the all-BJT or all-MOSFET technologies individually. Also, contemporary ICs often combine digital as
well as analog functions on the same chip, this being the reason for the name mixed-signal or also mixed-
mode ICs.
There is no question that microelectronics is one of the most exciting, challenging, and rapidly
evolving fields of human endeavor. The beginner may feel overwhelmed by all this, and rightly so. But,
as we embark upon the study of todays dominant processes and devices, we will try to focus on general
principles that transcend the particular technological milieu of the moment and that we can apply to
understand new processes and devices as they become available and commercially mature. Focus on
general principles, combined with continuing education, is a necessity for the young engineer aiming at
establishing and maintaining a satisfying career in a seemingly ever-changing field.
This chapter begins with a study of the physical structure of the MOSFET, the underlying
semiconductor principles, and the devices electrical characteristics. The devices under scrutiny are of the
so-called long-channel type (channel lengths > 1 m). Their behavior conforms fairly well to theoretical
prediction, so they are easier to model and the beginner will find them easier to grasp. However, the
devices available in todays ever shrinking IC processes are of the short-channel type (channel lengths of
fractions of 1 m). At such smaller sizes, a number of higher-order effects arise, particularly carrier
velocity saturation, which may cause significant departure from long-channel behavior. Aptly called
short-channel effects, they require more complex formalism and sophisticated models as the price for
providing more realistic results. These advanced models, while realizable in computer simulation, are too
complicated for hand analysis. We shall nevertheless continue to rely on the formalism and models of
long-channel devices to gain a quick if only approximate feel for device behavior, and then turn to
computer simulation for more accurate results.
Next, we investigate the FET in its two most important applications, namely, as an amplifier in
analog electronics, and as a switch in digital electronics. Basic single-transistor amplifier configurations
are covered in detail, along with a variety of circuit examples. The amplifiers investigated are of the so-
called discrete type, because they can be built using discrete transistors, resistors, and capacitors. (In this
respect, a very convenient device to experiment with in the lab is the CD4007 CMOS Transistor Array.)
Though nowadays MOSFET amplifiers are implemented in IC form, the motivation for studying discrete
designs is primarily pedagogical as discrete circuits are somewhat easier to grasp, and yet they reveal
important aspects that apply to IC implementations as well. Once we master the basics of discrete design,
we will be in a better position to tackle the more sophisticated techniques of IC amplifier design as we
proceed.
The chapter concludes with a detailed analysis of the CMOS inverter/amplifier as a simple yet
important IC building block that demonstrates the unique advantages of CMOS technology both in the
analog and digital domains. Basic CMOS logic gates are also addressed.
2004 Sergio Franco Ch. 3 - MOSFETs Page 3 of
1. Device Structure
Figure 1 shows, in simplified form, the structure of the n-channel, metal-oxide-semiconductor (MOS)
field-effect transistor (FET), or nMOSFET for short. The device is fabricated through a complex
sequence of steps involving pattern definition, oxidation, diffusion, ion implantation, material deposition
and material removal, on a wafer of lightly-doped p-type silicon (p

) called the body or also the bulk of


the nMOSFET. The wafer is also called the substrate because it provides physical support for the device
under consideration as well as all other devices of the same integrated circuit (IC).
Starting out with a polished wafer, the fabrication of an nMOSFET consists of the following
principal steps:
The first step is the thermal growth of a thin (t
ox
) insulating layer of silicon oxide (SiO
2
) on the
surface of the substrate.
Next, the gate electrode is created by growing over the oxide a layer of heavily-doped n-type silicon
(n
+
). Being extremely rich in free electrons, this electrode acts for all practical purposes like a metal.
The resulting metal-oxide-semiconductor (MOS) structure is the reason for the name of the device.
Next, ion implantation is used to create two heavily-doped n-type regions (n
+
) at each side of the gate.
Finally, two metal depositions form the source and drain electrodes.
The region of the body just below the oxide is called the channel region. Its length and width are
denoted as L and W, respectively. In current VLSI technology, L and W can be as small as fractions of a
micrometer (1 m = 10
6
m = 10
4
cm), while the oxide thickness t
ox
can be as low as ten nanometers (1
nm = 10
9
m = 10
7
cm = 10 ). We identify two basic ingredients in a MOSFET:
The channel region extending between the source and drain regions, and
The parallel-plate capacitor formed by the gate and the channel region.
Briefly stated, the principle at the basis of the MOSFET is to utilize this gate-body capacitance to control
the channel-region conductance. Since the path extending from the source to the drain regions includes
two back-to-back pn junctions (the body-source and the body-drain junctions), this path normally exhibits
very high resistance to current flow (typically ~10
12
). However, by raising potential of the gate
electrode to a suitable value, we can create favorable conditions for free electrons to exist in the channel
region, and thus form a continuous conductive path, or channel, from source to drain, along which
electrons can flow and produce current. To investigate device behavior, we need to address two issues:
What is the threshold voltage V
t
to which we need to raise the gate potential relative to the bulk to
form a channel and thus turn on the device?
Once the device has been turned on, what are the i-v characteristics of its channel?
Fig. 1 Basic physical structure of the nMOSFET.
2004 Sergio Franco Ch. 3 - MOSFETs Page 4 of
Both issues will be addressed further down.
Complementary MOSFETs
The dominant IC technology today utilizes the nMOSFET as well as its dual (or complementary) device,
the pMOSFET. Aptly called complementary MOS (or CMOS) technology, it requires that both device
types be fabricated on the same substrate. A pMOSFET is obtained by negating the doping types of the
body, source, and drain regions of an nMOSFET, so that the body is now n

, and the source and drain


regions are p
+
. To allow for the coexistence of the two devices on a common substrate, the pMOSFET is
placed inside a local lightly doped n-type (n

) substrate, also called well or tub, which is formed by a


separate diffusion into the existing p

wafer prior to the fabrication of the transistors themselves.


The structure is depicted in cross-sectional form in Fig. 2, where subscripts n and p identify the
terminals of the nMOSFET and the pMOSFET, respectively. The nMOSFET, located left of center, is
similar to that of Fig. 1, except that the connection to its body (B
n
) is not at the bottom, as shown in the
simplified rendition of Fig. 1, but at the top. This is mandated by the planar-IC requirement that all
interconnections be made at the top of the wafer. The pMOSFET, located right of center, is placed inside
its own well (n

), and connection to the well (B


p
) is at the top, right. To ensure good-quality ohmic
contacts, the metal connections to the bulks are implemented thorough heavily doped regions, as shown.
Figure 2 illustrates also another important aspect of ICs, namely, the need for adjacent devices to
be electrically isolated from each other. This constraint is met by growing, prior to fabrication of the
actual transistors, a ring of SiO
2
insulator material, also called field oxide, around each transistors
intended site. Indeed, each transistor must be kept electrically isolated not only from its neighboring
devices, but also from its own body! The p-type body of the nMOSFET forms pn junctions with the
n-type source and drain regions, so in this case body isolation is achieved by anchoring B
n
to the most
negative voltage (MNV) in the circuit. This will keep both junctions reverse biased, and therefore in
cutoff, under all possible circuit conditions. Likewise, the n-type well of the pMOSFET forms np
junctions with the p-type source and drain regions, so anchoring B
p
to the most positive voltage (MPV) in
the circuit will keep both junctions in cutoff under all possible circuit conditions. For instance, in the case
of a digital CMOS circuit powered between 5 V and ground, B
n
is connected to ground, and B
p
is
connected to +5 V. These connections are made internally to the IC by the manufacturer.
Fig. 2 Cross-sectional view of CMOS transistors.
2004 Sergio Franco Ch. 3 - MOSFETs Page 5 of
2. The Threshold Voltage
To investigate the process of channel formation in an nMOSFET, we focus on its gate-oxide-bulk
structure, which forms a parallel-plate capacitor, albeit one with plates of different materials. Though in
earlier MOSFETs the gate electrode was made of metal, such as aluminum, nowadays the gate is
fabricated using n
+
silicon, this being the reason why modern processes is also referred to as silicon-gate
processes. Since the n
+
silicon film is grown over amorphous oxide, it consists of sub-micrometer-sized
crystallites, rather than a single crystal, and it is thus referred to a polysilicon. Regardless, n
+
polysilicon
is very rich in free electrons, just like a metal, and is used not only to create the gate electrode, but also to
interconnect different devices in an IC. The reason for making the gate electrode of polysilicon is that the
subsequent ion implantation creating the source and drain regions will inherently guarantee a high degree
of alignment among the different regions. In particular, as the ions diffuse downward into the body, they
also diffuse sideways a bit, resulting in a small amount of overlap between the edges of the gate and those
of the source and drain regions. As we proceed, we shall appreciate how this slight overlap, clearly
shown in both pictures above, is critical to the proper functioning of the MOSFET.
We now wish to investigate the effect of an external bias upon the type of charges as well as their
distributions in the body region just below the oxide layer. Since no current flows through the insulating
oxide layer, the only means for the gate to effect the properties of the channel region is via the electric
field inside the oxide. Hence, the designation field-effect transistor (FET).
The Gate-Body Capacitor
Figure 3 shows a section of the gate-oxide-body structure of Fig. 1, but rotated counterclockwise by 90.
As mentioned in connection with Fig. 2, the function of the p
+
region is to ensure a good-quality ohmic
contact between the p

bulk and the metal connection, so it will play no role in our analysis. The well-
known formula for parallel-plate capacitance gives, in the present case, C =
ox
(WL)/t
ox
, where W and L
are the channel-regions width and length depicted in Fig. 1,
ox
is the permittivity of the oxide layer, and
t
ox
is its thickness. To make analysis independent of the particular device size, it is convenient to work
with the capacitance per unit area,
ox
ox
ox
C
t

= (1)
(a) (b)
Fig. 3 - Gate-body capacitor (a) at 0-V bias, and (b) biased at
0
to eliminate the space-charge layers.
2004 Sergio Franco Ch. 3 - MOSFETs Page 6 of
Given that silicon oxide has
ox
= 345 fF/cm, a fabrication process with, say, t
ox
= 10 nm gives C
ox
= 345
nF/cm
2
, or 3.45 fF/(m)
2
, as it is frequently expressed.
The gate-oxide-bulk structure is reminiscent of the familiar pn junction, except that the n and p
materials are now separated by an insulator layer that prevents direct current flow. However, if an
external conducting path is established, for instance by shorting G and B with a wire as in Fig. 3a,
electrons will diffuse from the electron-rich n
+
gate, through the wire, to the electron-starved p

bulk,
leaving behind a layer of immobile positive donor ions in the gate. Once in the bulk, these electrons
recombine with holes there, leading in turn to the formation of a layer of immobile negative acceptor ions
in the bulk. Being attracted to each other, the two layers will be concentrated near the gate-oxide and
silicon-oxide interfaces, respectively. Just as in the case of the pn junction, the creation of these space-
charge layers results in an electric field from the gate, through the oxide, to the bulk, and an equilibrium
condition is reached whereby this field will oppose any further diffusion of electrons. Associated with
this field is a built-in potential
0
across the gate-bulk structure,
0
=
n

p
, where
ln
i
p T
A
n
V
N
= (2a)
is the equilibrium electrostatic potential, also called Fermi potential, of the bulk, and
ln
D
n T
i
N
V
n
= (2b)
is the equilibrium electrostatic potential, or Fermi potential of the gate. Here, V
T
= kT/q is the thermal
voltage (V
T
26 mV at T = 300 K), N
A
and N
D
are the doping densities in the bulk and gate materials, and
n
i
is the intrinsic electron-hole concentration of silicon (n
i
1.4510
10
/cm
3
). Since both N
A
and N
D
are
greater than n
i
, we have
p
< 0 and
n
> 0. Moreover, since N
A
and N
D
appear in the argument of the
logarithmic function,
p
and
n
are not overy sensitive to variations in the doping doses.
An ordinary capacitance with its plates shorted together will be in the discharged state. However,
if the plates are of dissimilar materials, as in the present case, we have Q 0 even though V
GB
= 0! If we
want to drive Q to zero, we need to apply a voltage V
GB
of equal magnitude but opposite polarity as
0
, or
V
GB
=
0
=
p

n
< 0 (see Fig. 3b). This value of V
GB
is also called the flatband voltage because of its
effect on the energy bands of the bulk material. We shall use this voltage as the reference voltage for our
analysis to follow.

Example 1
Assuming N
A
= 10
16
/cm
3
and N
D
= 10
20
/cm
3
, find the electrostatic potentials as well as the value of V
GB
needed to eliminate the space-charge layers.
Solution
From Eq. (2),
10
16
1.45 10
0.026ln
10
p


= = 0.35 V
20
10
10
0.026ln
1.45 10
n
= =

+0.59 V
To achieve charge neutrality in the gate and bulk, the gate must be biased more negative than the body by
V
GB
=
0
= 0.35 0.59 = 0.94 V.
Remark
Were the gate-bulk a regular np junction, with V
GB
= 0.94 V it would be forward-biased quite heavily,
2004 Sergio Franco Ch. 3 - MOSFETs Page 7 of
thus conducting a large forward current from the p-bulk to the n-gate. In the present case, however, no
current flows because of the oxide insulator separating the two, giving further credence to the name FET.

Inversion
Let us now gradually increase V
GB
, starting at V
GB
=
0
(or V
GB
= 0.94 V in our example). The effect of
this increase is to re-establish space charge-layers on both sides of the oxide, uncovering positive charge
in the gate and negative charge in the bulk. We are particularly interested in the situation in the bulk, so
we will ignore that in the gate, keeping in mind that the charge in the gate is always of equal magnitude
but opposite polarity as the charge in the bulk. The situation in the bulk is depicted in Fig. 4, where we
have chosen the origin of the x-axis to coincide with the oxide-bulk interface, a surface that will play an
important role in our analysis. Initially, the negative charge in the bulk results from the negative acceptor
ions there: the holes are simply pushed away from the oxide-bulk interface, leaving behind the bound
ions. The resulting space-charge layer is also referred to as a depletion layer because it is devoid of holes.
However, as we increase V
GB
from
0
, not only does the depletion layer in the bulk widen, but also the
surface potential (0) increases. When (0) changes from negative to positive, the bulk near the surface
Fig. 4 The situation in an nMOSFET
just before the onset of strong inversion.
2004 Sergio Franco Ch. 3 - MOSFETs Page 8 of
is said to undergo inversion because it turns from p-type to n-type, at least electrostatically speaking. For
this reason, the bulk region near the surface is called inversion layer.
With reference to Fig. 4, we observe that the formation of the space-charge layers results in the
creation of an electric field E(x). The field strength as a function of x is readily visualized by counting the
field lines, each of which starts on a positive ion in the gate and ends on a negative ion in the bulk. We
are interested in the lines in the bulk, which is maximum at the oxide-bulk interface (x = 0), and decreases
linearly with x to finally drop to zero at the edge of the depletion layer (x = x
p
). We can readily find a
relationship between the maximum strength E
m
and the layers width x
p
using Gauss theorem. In a one-
dimensional case such as ours, this theorem is expressed as dE/dx = /
si
, where is the charge density in
the depletion layer ( = qN
A
), and
si
is silicons permittivity (
si
= 1.04 pF/cm). By inspection, we have
dE/dx = E
m
/x
p
= qN
A
/
si
, so
A p
m
si
qN x
E

= (3)
Electric field and potential are in turn related as E = d/dx. Rewriting as d = Edx and integrating
both sides from x = 0 to x = x
p
, we get

0 0
( )
p p
x x
d E x dx =

The term on the left is simply the difference
p
(0), while the term on the right is the just area of the
triangle under the E curve, or (x
p
E
m
), so
(0)
2
m p
p
E x
=
Using Eq. (3) to eliminate E
m
, we obtain an expression for the depletion-layer width as a function of the
surface potential (0),
2
(0)
si
p p
A
x
qN

( =

Onset of Strong Inversion
We are interested in the situation at which the surface potential attains the value (0) =
p
(or
+0.35 V in our example), for then the electron concentration n in the inversion layer becomes equal to the
hole concentration p in the bulk, or n = N
A
(= 10
16
/cm
3
in our example). This situation is said to mark the
onset of strong inversion. Using subscript 0 to mark this onset, we now wish to find the gate-body bias
V
GB0
required to bring about this onset itself. To this end, we first substitute (0) =
p
to find the
depletion-layer width at the onset of strong inversion
0
2
2( )
si
p p
A
x
qN

= (4)
Next, we observe that the unit-area charge in the bulk depletion-layer is Q
b0
= qN
A
x
p0
. Using Eq. (4),
0
2 2( )
b A si p
Q qN = (5)
2004 Sergio Franco Ch. 3 - MOSFETs Page 9 of
This negative bulk charge is matched by a positive charge of equal magnitude in the gate. By the
capacitance law, the voltage required to sustain this charge situation is V
ox
= Q
b0
/C
ox
. Finally, the gate-
to-body voltage drop required to bring about the onset of strong inversion is, by KVL, V
GB0
=
0
+ 2(
p
)
+ V
ox
, or
0
0 0
2
b
GB p
ox
Q
V
C
= (6)
In words: to bring about the onset of strong inversion, we need to increase V
GB
, starting from the
reference level
0
, first by the term 2(
p
) to raise the surface potential (0) from
p
, through zero, to

p
, and then by the term Q
b0
/C
ox
to sustain the unit-area charge Q
b0
in the bulk depletion-layer.

Example 2
Assuming the doping densities of Example 1, along with t
ox
= 25 nm, find the values of all relevant
physical quantities at the onset of strong inversion.
Solution
The unit-area capacitance is
Fig. 5 Situation at the onset of strong inversion.
2004 Sergio Franco Ch. 3 - MOSFETs Page 10 of
15
6
345 10
138
2.5 10
ox
C

= =

nF/cm
2
At the onset of strong inversion, the depletion-layer width is
12
0 19 16
2 1.04 10
2(0.35) 301
1.602 10 10
p
x


= =

nm
The corresponding electric field intensity is
19 16 6
0 12
1.602 10 10 30.1 10
46.4
1.04 10
m
E


= =

kV/cm
The unit-area charge in the bulk depletion-layer is
19 16 12
0
4 1.602 10 10 1.04 10 (0.35) 48.3
b
Q

= = nC/cm
2
Finally, the required gate-body voltage drop is, by Eq. (6),
0
48.3
0.94 2( 0.35)
138
GB
V

= = 0.94 + 0.70 + 0.35 = +0.11 V

Once strong inversion is reached, the surface potential (0) and, hence, the depletion-layer width
x
p
, will change very little with the applied voltage V
GB
because (0) depends on V
GB
only logarithmically.
Any increase V
GB
above V
GB0
will essentially be accompanied by an increase Q
n
C
ox
V
GB
in the
electron charge of the inversion layer. These electrons are supplied by the n
+
source region (hence the
reason for its name), where they exist in abundant supply. In fact, in order for these electrons to be
enticed into the inversion layer, the gate must slightly overlap the source region to allow for the fringe
electric field to attract electrons from the source to the channel. As mentioned, the advantage of the
silicon-gate process is that it is a self-aligning process.

Example 3
Assuming the data of Example 2, find the change Q
n
brought about by a 1-V increase V
GB
in strong
inversion. Compare with the depletion-layer charge Q
b0
.
Solution
We have Q
n
C
ox
V
GB
= (138 nF/cm
2
)(1 V) = 138 nC/cm
2
, indicating that the inversion-
layer charge (Q
n
( can be significantly greater than the depletion-layer charge (Q
b0
( (= 48.3 nC/cm
2
in our example), even though the inversion layer is much thinner than the depletion layer.

The Threshold Voltage V


t0
We now wish to apply the above findings to the full-fledged MOSFET, starting from the situation at the
onset of strong inversion depicted in Fig. 6 for both MOSFET types. Note the presence of the inversion
layer immediately below the oxide-bulk surface, along with the depletion layer extending not only below
the inversion layer, but also around the source and drain regions, as they form pn junctions with the body.
The threshold voltage V
t
is defined as the gate-source voltage v
GS
needed to bring about the onset of
strong inversion in the channel region. For the case of an nMOSFET with body and source at the same
potential (ground, in Fig. 6), the threshold voltage takes on the general form
2004 Sergio Franco Ch. 3 - MOSFETs Page 11 of
0
0 0
2
b ox i
t p
ox ox ox
Q Q Q
V
C C C
= (7)
The first three terms are simply those of Eq. (6). The next term, involving the unit-area charge Q
ox
,
accounts for the presence of dangling bonds in the bulk right at the interface, as well as positive ions that
get trapped in the oxide right near the oxide-bulk interface during fabrication. The first four terms form
what is known as the native threshold of the nMOSFET. The last term, involving the unit-area charge Q
i
,
accounts for impurities that the manufacturer introduces deliberately in the bulk, right at the oxide-bulk
interface, to adjust V
t0
to the desired value. For p-type impurities, we have Q
i
< 0, and for n-type impur-
ities, we have Q
i
> 0. For obvious reasons, the native threshold is also called the undoped threshold.

Example 4
Assuming the data of Example 2, along with a surface state density N
ox
= 210
11
positive ions/cm
2
,
(a) Find the native threshold of the nMOSFET.
(b) Find the implant type and dosage N
i
needed for V
t0
= +1.0 V.
(c) Find the implant type and dosage N
i
needed for V
t0
= 1.0 V.
Solution
(a) We have Q
ox
= qN
ox
= 1.60210
-19
210
11
= 32 nC/cm
2
. So, using the result of Example 2,
0
32
0.11
138
t
V = = 0.122 V
(b) To raise V
t0
= from its native value of 0.122 V to +1.0 V, we need a p-type implant, such as
boron, which will contribute negative ions in the bulk near the surface. Imposing
19
9
1.602 10
1.0 0.122 0.122 0.122
138 10
i i i
ox ox
Q qN N
C C


+ = = = +

gives N
i
= 9.6610
11
p-type ions/cm
2
.
(c) To lower V
t0
from its native value of 0.122 V to 1.0 V, we need an n-type implant, such as
phosphorus, which will contribute positive ions in the bulk near the surface. Imposing
(a) (b)
Fig. 6 - The onset of strong inversion in (a) the nMOSFET and (b) the pMOSFET.
2004 Sergio Franco Ch. 3 - MOSFETs Page 12 of
19
9
1.602 10
1.0 0.122 0.122 0.122
138 10
i i i
ox ox
Q qN N
C C

= = =

gives N
i
= 7.5610
11
n-type ions/cm
2
.

We now make some important observations about nMOSFETs and pMOSFETs:


An nMOSFET with V
t0
> 0 is said to be normally off because with v
GS
= 0 there is no channel. We
need to raise V
GS
above V
t0
in order to create a channel or, equivalently, to enhance the channel-region
conductivity. This type of device is also referred to as enhancement nMOSFET. The higher the (p-
type) implant dosage, the more positive the value of V
t0
. The circuit symbol for this device, shown in
Fig. 7a, uses a broken line to signify a normally nonconductive channel.
An nMOSFET with V
t0
< 0 is said to be normally on because with v
GS
= 0 there is already a channel
present. We need to lower v
GS
below V
t0
in order to eliminate the channel or, equivalently, to deplete
the channel region of electrons. This type of device is also referred to as depletion nMOSFET. The
higher the (n-type) implant dosage, the more negative the value of V
t0
. The circuit symbol for this
device, shown in Fig. 7b, uses a continuous line to signify a normally conductive channel.
A pMOSFET with V
t0
< 0 is said to be normally off because with v
GS
= 0 there is no channel. We
need to lower v
GS
below V
t0
in order to create a channel. The circuit symbol of this device, also called
enhancement pMOSFET, is shown in Fig. 7c.
A pMOSFET with V
t0
> 0 is said to be normally on because with v
GS
= 0 there is already a channel,
and if we want to deplete it of holes, we need to raise v
GS
above V
t0
. The circuit symbol of this
device, also called depletion pMOSFET, is shown in Fig 7d.
The preferred mode of operation of a MOSFET is with the body tied to the source, resulting in a
three-terminal device. This is the case, for instance, of discrete devices. Figure 8 shows the simplified
MOSFET symbols most commonly used for this type of connection. To avoid the awkward broken lines,
the enhancement-types are given solid lines. To signify that the channels of the depletion types are
already present, thicker lines are used.
The Body Effect and the Threshold Voltage V
t
When multiple devices share the same substrate, the common body of nMOSFETs must be tied to the
most negative voltage (MNV) to avoid inadvertently turning on any of the body-source or body-drain pn
(a) (b) (c) (d)
Fig. 7 Full-fledged circuit symbols for the four MOSFET types.
2004 Sergio Franco Ch. 3 - MOSFETs Page 13 of
junctions. Likewise, the common body of pMOSFETs must be tied to the most positive voltage (MPV).
It is therefore possible for the source of an nMOSFET to find itself at a higher voltage than the body, or
V
S
> V
B
. Likewise, we can have V
S
< V
B
for a pMOSFET. We wish to investigate the effect of body-bias
on the threshold voltage of an nMOSFET.
Denoting the source-body voltage of an nMOSFET as V
SB
(V
SB
0), we can simply recycle our
previous findings by replacing [2(
p
)] with [2(
p
) + V
SB
] in Eq. (5). The result is
2 ( 2 )
b A si SB p
Q qN V = +
where we are using the absolute value of
p
(
p
, < 0) to reduce the possibility of confusion. Clearly, the
increase in the depletion-region charge Q
b
comes at the expense of a simultaneous decrease in the
inversion-layer charge Q
n
. To return the channel to its former state, v
GS
will have to be suitably increased.
To find out by how much, we rewrite Eq. (7) as
0 0 0
0 0 0
2 2
b ox i b ox i b b b b
t p p t
ox ox ox ox ox ox ox ox
Q Q Q Q Q Q Q Q Q Q
V V
C C C C C C C C


= = =
We can concisely express the threshold voltage in the insightful form
0
2 2
t t SB p p
V V V
(
= + +
(

(8)
where V
t0
is the zero-body-bias value of V
t
as given in Eq. (7), and
2
A si
ox
qN
C

= (9)
Fig. 8 Simplified circuit symbols for the four MOSFET types.
2004 Sergio Franco Ch. 3 - MOSFETs Page 14 of
is called the body-effect parameter. Its value, in V
1/2
, is typically on the order of a fraction of 1 V
1/2
.

Example 5
(a) For the enhancement nMOSFET of Example 4(b), find V
t
at V
SB
= 1 V, and at V
SB
= 5 V.
(b) For the depletion nMOSFET of Example 4(c), find V
t
at V
SB
= 1 V, and at V
SB
= 5 V.
Solution
19 16 12
9
2 1.602 10 10 1.04 10
0.418
138 10


= =

V
1/2
(a) For the enhancement nMOSFET we have
V
t
(V
SB
= 1 V) =
( )
1.0 0.418 1 0.7 0.7 1.0 0.195 1.195 + + = + = V.
V
t
(V
SB
= 5 V) =
( )
1.0 0.418 5 0.7 0.7 1.0 0.648 1.648 + + = + = V.
(b) For the depletion nMOSFET we have
V
t
(V
SB
= 1 V) =
( )
1.0 0.418 1 0.7 0.7 1.0 0.195 0.805 + + = + = V.
V
t
(V
SB
= 5 V) =
( )
1.0 0.418 5 0.7 0.7 1.0 0.648 0.352 + + = + = V.

The example indicates that the effect of body bias is to shift the threshold voltage of an
nMOSFET in the positive direction, regardless of whether it is a depletion or enhancement type. For a
pMOSFET, the shift is in the negative direction. The dependence of V
t
upon the body bias is referred to
as the body effect, and the body itself is sometimes referred to as back gate because it influences the
inversion layer like the gate, if in the opposite direction.

Exercise 1
Show that for a polysilicon-gate technology, the first two terms in the threshold voltage of an nMOSFET
can be expressed concisely as (
0
2
p
) = V
T
ln (N
A
/N
D
).

2004 Sergio Franco Ch. 3 - MOSFETs Page 15 of


3. The Channels Characteristics
We are now ready to investigate the i-v characteristics of the n-channel, anticipating that our understand-
ing of the p-channel will follow easily once we have mastered the n-channel. Figure 9 shows the
sequence of situations an n-channel goes through as we gradually increase v
DS
starting out with v
DS
0.
Once the MOSFET is biased in strong inversion, its channel can be viewed as a resistor of length L, width
W, and thickness proportional to the overdrive voltage, which is defined as the amount by which the gate-
source voltage exceeds the threshold voltage,
V
OV
= V
GS
V
t
(10)
For instance, in the device of Example 3, every volt of overdrive induces an electron charge of 138
nC/cm
2
in the channel, so the greater the overdrive, the more conductive the channel will be. If we now
apply a voltage v
DS
> 0 to the drain, electrons will drift from the source, through the channel, to the drain,
like in an ordinary resistor (hence the designation ohmic for this region of operation), thus producing
current. But, electrons are negative, so the current i
D
at the drain terminal will flow into the device, as
shown. The source and drain designations reflect the fact that mobile charges (electrons in nMOSFETS,
holes in pMOSFETs) are sourced to the channel at one end, and drained from the channel at the other.
The Triode Region
If we now increase v
DS
further, an interesting effect occurs, namely, the channel becomes tapered, as
depicted in Fig. 9b. This stems from the fact that while the overdrive voltage is V
GS
V
t
at the source
end, it reduces to (V
GS
v
DS
) V
t
at the drain end, indicating a thinner channel there. For instance, let V
t
= 1 V, V
GS
= 5 V, and v
DS
= 2 V. Then, the overdrive at the source end is 5 1 = 4V, but that at the drain
end is only (5 2) 1 = 2 V. In this example, the channel at the drain end is only half as thick as at the
source end. With a reduction in channel thickness, we expect an increase in the channels dynamic
resistance.
To investigate quantitatively, refer to Fig. 10, where we imagine that we have sliced the channel
like a loaf of bread, and we focus on the slice of width dy located at a distance y from the source. The
voltage at each slice varies from 0 V at the leftmost slice to v
DS
at the rightmost slice, so the voltage v(y)
at our particular slice will lie somewhere in between, or 0 v(y) v
DS
. Now, the gate strip immediately
above our slice forms a capacitance dC = C
ox
Wdy with the channel itself, so the charge packet dQ
n
induced in the channel is, by the capacitance law,
dQ
n
= dC[V
GS
v(y) V
t
] = C
ox
Wdy[V
GS
v(y) V
t
]
(This charge is negative because it consists of electrons.) The voltage drop v
DS
across the channel
produces an electric field E inside the channel, oriented from drain to source. This field, in turn, causes
the negative charge packet dQ
n
to drift toward the drain, thus producing the current i
D
. By definition,
[ ( ) ]
n
D ox GS t
dQ dy
i C W V v y V
dt dt
= =
where dy/dt represents the velocity with which dQ
n
drifts toward the drain. This velocity is proportional
to the electric field, or dy/dt =
n
E(y), where
n
is the electron mobility. (The negative sign stems from
the fact that electrons drift against the electric field.) But, electric field and potential are related as E(y) =
dv(y)dy, so dy/dt =
n
dv(y)/dy. Substituting in the above equations gives
2004 Sergio Franco Ch. 3 - MOSFETs Page 16 of
Fig. 9 Illustrating the different regions of operation of an nMOSFET.
(a) Ohmic region
(b) Triode region
(c) Pinchoff (EOS)
(d) Saturation region
2004 Sergio Franco Ch. 3 - MOSFETs Page 17 of
( )
[ ( ) ]
D n ox GS t
dv y
i C W V v y V
dy
=
Multiplying both sides by dy and integrating from y = 0, where v(y) = 0, to y = L, where v(y) = v
DS
, we get

0 0
[ ( ) ] ( )
DS
L v
D n ox GS t
i dy C W V v y V dv y =

The left side integrates to i
D
L, and the right side integrates to
2
1
2
( )
GS t DS DS
v V v v . This allows us to
express i
D
in the following insightful form
2
1
( )
2
D GS t DS DS
i k V V v v
(
=
(

(11)
where the quantity
'
W
k k
L
= (12)
is called the device transconductance parameter. This is simply a scale factor, in A/V
2
, indicating how
much current a device will draw for a given set of V
GS
, V
t
, ans v
DS
values. The designer can tailor the
value of k to meet given needs by suitably specifying the devices dimensions W and L; hence, the reason
for using the qualifier device. The quantity
'
n ox
n ox
ox
k C
t

= = (13)
is called the process transconductance parameter, in A/V
2
. Being common to all devices, it is unique of
the particular fabrication process; hence, the reason for using the qualifier process. Figure 11 shows the
the plot of i
D
versus v
DS
for a given overdrive voltage V
OV
.
Fig. 10 Detailed illustration of the triode-region operation.
2004 Sergio Franco Ch. 3 - MOSFETs Page 18 of
We observe that near the origin, where v
DS
is small enough to render the quadratic term negligible
in Eq. (11), the i
D
v
DS
characteristic approaches, for a given gate-source drive V
GS
, a straight line, or
( )
D GS t DS
i k V V v (14a)
For this reason, the region corresponding to small values of v
DS
is called the linear region. Rewriting Eq.
(14a) in the form of Ohms law as
1
D DS
DS
i v
r
= (14b)
confirms that the channel acts as a resistor, this being the reason why this region is also referred to as the
ohmic region. The channel resistance r
DS
is controlled by the overdrive V
OV
as
1 1
( )
'
DS
GS t
OV
r
W
k V V
k V
L
= =

(15)
This resistance depends also on the W/L ratio, also called the aspect ratio, indicating that by proper choice
of this ratio, the IC designer can set this resistance to virtually any value for a given overdrive V
OV
.

Example 6
Assuming
n
= 600 cm
2
/Vs, C
ox
= 83 nF/cm
2
, and V
t
= 1.0 V,
(a) Specify the W/L ratio so that r
DS
= 1 k for V
GS
= 5 V.
(b) Calculate r
DS
for V
GS
= 4 V, 3 V, 2 V, 1 V, 0 V.
Solution
(a) By Eq. (13),
9
' 600 83 10 50 k

= A/V
2
. Using Eq. (15) to impose
3
6
1
10
50 10 ( / )(5 1) W L

=

we get W/L = 5. Consequently, k = (50 A/V
2
)5 = 250 A/V
2
.
Fig. 11 The complete i
D
v
DS
characteristic for a given overdrive voltage V
OV
= V
GS
V
t
> 0. Note that
V
DS(EOS)
= V
OV
2004 Sergio Franco Ch. 3 - MOSFETs Page 19 of
(b) By Eq. (15), for V
GS
= 4 V, we get
r
DS
=
6
1
250 10 (4 1)


= 1.333 k.
Likewise, for V
GS
= 3 V we find r
DS
= 2 k, and for V
GS
= 3 V, we find r
DS
= = 4 k. For V
GS
1 V, the
MOSFET is in cutoff, and r
DS
= .

As we keep increasing v
DS
, the channel becomes progressively thinner at the drain end, and the
quadratic term becomes more and more significant in Eq. (11). Consequently, the slope of the curve
decreases, indicating a corresponding increase in the dynamic resistance of the channel. This region of
operation is called the triode region by analogy with vacuum tubes, which exhibit similar characteristics.
We also observe in Fig. 8 that the depletion layer associated with the body-drain junction widens as we
keep increasing v
DS
.
The Pinchoff Point
Once v
DS
achieves the special value
V
DS(EOS)
= V
GS
V
t
= V
OV
(16)
the channel thickness at the drain end reduces to zero, as depicted in Fig. 8c, and the corresponding point
on the i
D
v
DS
curve is referred to as the pinchoff point. The current at this point is readily found by
substituting v
DS
= V
GS
V
t
in Eq. (11). The result gives
2
(EOS)
( )
2
D GS t
k
I V V = (17)
This can also be expressed as
2 2
(EOS) (EOS)
( / 2) ( / 2)
D OV
I k V k V = = . As we shall see next, this point marks the
beginning, or edge, of the saturation region (EOS).
The Saturation Region
If we raise v
DS
above the critical value V
DS(EOS)
, the voltage at the pinchoff point continues to remain at
V
DS(EOS)
, and the excess difference v
DS
V
DS(EOS)
is dropped across a narrow depletion layer of width L
between the pinchoff point and the edge of the drain. As depicted in Fig. 8d, the pinchoff point moves
slightly away from the drain, in effect shortening the channel by a small amount L. This effect, aptly
referred to as channel-length modulation, is investigated by replacing L with L L in Eq. (12),
'
W
k k
L L
=


This can be rewritten as
( ) ' ' 1 ' 1
(1 / )
DS
W W L W
k k k k v
L L L L L L

| |
= + +
|

\ .
(18)
where we have conformed to the established practice in the literature to assume that the fractional change
L/L (L/L << 1) be linearly proportional to v
DS
. The proportionality constant , in V
-1
, is called the
2004 Sergio Franco Ch. 3 - MOSFETs Page 20 of
channel-length modulation parameter. Typically, it is on the order of 0.01 to 0.1 V
-1
, and for simplicity it
is usually ignored in the course of DC hand calculations. Substitution of Eq. (18) into Eq. (17) gives the
i
D
v
DS
characteristic in the saturation region, so called because i
D
increases with v
DS
only slightly there, in
effect saturating,
2
( ) (1 )
2
D GS t DS
k
i V V v = + (19)
The slope in saturation is the reciprocal of a resistance r
o
called the output resistance of the
MOSFET. Differentiating Eq. (19), we obtain
(EOS)
1
D
D
o DS
i
I
r v

= =

The output resistance is usually expressed in the form


1
o
D
r
I
= (20)
where I
D
is the current at the actual saturation-region operating point (I
D
I
D(EOS)
.) In general, r
o
is fairly
large relative to other resistances in a MOSFET circuit. Indeed, the smaller the value of , the higher the
value of r
o
. In the limit 0, a MOSFET operating in saturation would approach ideal current-source
behavior, or, more precisely, it would act as an ideal voltage-controlled current-source (ideal VCCS), with
v
GS
as the control voltage. As such, the MOSFET finds application as an amplifier.
Remark
In order to ensure the continuity between Eqs. (11) and (19) at the EOS, the right-hand side of Eq. (11)
must, strictly speaking, be multiplied by the term (1 + v
DS
). In practice, to simplify the calculations, this
term is usually ignored in Eq. (11) due to the fact that v
DS
is small in the triode region.
2004 Sergio Franco Ch. 3 - MOSFETs Page 21 of
4. The i-v Characteristics of MOSFETs
The two most important MOSFET characteristics are the plot of i
D
versus v
GS
in saturation, and the plot of
i
D
versus v
DS
for different values of V
GS
. These curves can be displayed either in the lab, via a an
oscilloscope equipped with a suitable curve-tracer module, or on a computer monitor via PSpice.
Diode-Mode Operation
In the Pspice circuit of Fig. 12 the gate and drain terminals have been tied together (v
DS
= v
GS
), turning the
MOSFET into a two-terminal device. For V
GS
< V
t
the device is in cutoff. For V
GS
> V
t
, the device is on
and in saturation, because v
DS
= v
GS
implies v
DS
> V
GS
V
t
, the condition for an nMOSFETs operation in
saturation. Consequently, when on, the device is governed by Eq. (19), but with v
DS
= v
GS
. The result is
the curve of Fig. 13, which reveals a tendency by a diode-connected MOSFET to favor current flow in
one direction (drain-to-source for an nMOSFET, source-to-drain for a pMOSFET) while inhibiting it in
the opposite direction. Hence the name for this mode of operation.
At this juncture it must be pointed out that the MOSFETs transition from off to on at the
threshold V
t
is not abrupt, but rather a gradual process. In fact, the channel already starts to conduct for a
range of v
GS
values less than, if close to, V
t
. Over this range, aptly called the subthreshold region, it turns
out that i
D
increases exponentially with v
GS
. The choice of V
t
as the value of v
GS
responsible for the onset
of strong inversion is primarily a matter of mathematical convenience and mental bookkeeping.
The slope of the curve at a particular point V
GS
is denoted as g
m
and is called the transconductance
GS
V
GS
D
m
v
i
g

= (21)
Its units are A/V, or more likely A/V in micropower devices. Differentiating Eq. (19) but with = 0 for
simplicity, and suitably manipulating, we find three different forms for calculating transconductance,
2
m D
g kI = (22a)
( )
m GS t OV
g k V V kV = = (22b)
2
0.5( )
D D
m
GS t OV
I I
g
V V V
= =

(22c)
Though the three forms are equivalent, each provides different insight. The first form indicates that g
m
V
t
= 1.0 V
W = 2 m
L = 1 m
k = 50 A/V
2
= 0.05V
-1
Fig. 12 - Diode-connected enhancement nMOSFET.
2004 Sergio Franco Ch. 3 - MOSFETs Page 22 of
increases with the square root of I
D
. By contrast, in a bipolar junction transistor (BJT), g
m
is linearly
proportional to the collector current I
C
, or g
m
= I
C
/V
T
, where V
T
= 26 mV is the thermal voltage. Also, the
second form indicates that g
m
is proportional to the overdrive voltage V
OV
= V
GS
V
t
.

Example 7
Assuming the nMOSFET data of Fig. 12, but with = 0 to simplify the calculations,
(a) Find V
GS
for I
D
= 1 mA. Compare with Fig. 13, and comment.
(b) Find g
m
at that point, and compare with the g
m
of a bipolar junction transistor (BJT) operating
at the same current level.
(c) Find W/L to raise the g
m
of the FET to the same value as that of the BJT.
Solution
By Eq. (12), k = 5010
-6
(2/1) = 100 A/V
2
.
(a) Using Eq. (19) with = 0, we get 110
-3
= (10010
-6
)(V
GS
1.0)
2
, or V
GS
= 5.472 V.
This is higher than the value (5 V) predicted by Fig. 13 because we have assumed = 0. This gives an
idea about the error incurred by ignoring .
(b) By Eq. (22a),
6 3
2 2 100 10 10 0.447
m D
g kI

= = = mA/V. By contrast, at 1 mA a BJT
gives g
m
1/26 = 38.5 mA/V.
(c) Since g
m
is linearly proportional to k , and thus to / W L , we impose a simple proportion,
/ / 2/1 38.5/ 0.447 W L =
which gives W/L 14,800, an outlandish number. This example illustrates a notorious feature of
MOSFETs compared to BJTs, namely, their generally much lower g
m
values. Indeed, if we use Eq. (22c),
we get g
m
= I
D
/[(5.472 1)/2] = I
D
/(2,236 mV), which compares quite unfavorably with the BJT relation
g
m
= I
C
/(26 mV).

The Complete i-v Characteristics


In Fig. 10 we have illustrated the behavior of the channel as we walk it through the different situations of
Fig. 8, but for only a single fixed value of V
GS
(V
GS
> V
t
). To get the complete picture, we need to display
the characteristics for different values of V
GS
. The PSpice circuit of Fig. 14 displays the i
D
-v
DS
character-
istics with v
GS
stepped in 0.5-V increments. The result is the family of curves of Fig. 15, with respect to
Fig. 13- i-v Characteristic of a diode-
connected enhancement nMOSFET.
2004 Sergio Franco Ch. 3 - MOSFETs Page 23 of
which we make the following observations:
For V
GS
< V
t
(V
GS
< 1.0 V in our example), the device gives i
D
= 0 and is thus in cutoff (CO). Its
terminals draw only leakage currents, which are negligible in most practical situations.
For V
GS
> V
t
, the device is on, either in the triode region if v
DS
< (V
GS
V
t
), or in the saturation region
if v
DS
> (V
GS
V
t
). Either region requires a separate equation for finding i
D
, namely,
v
DS
< (V
GS
V
t
) Triode region
2
1
( )
2
D GS t DS DS
i k V V v v
(
=
(

v
DS
> (V
GS
V
t
) Satur.n region
2
( ) (1 )
2
D GS t DS
k
i V V v = +
The locus of points for which v
DS
= V
GS
V
t
= V
OV
provides the borderline between the two regions
Since the abscissas are spaced evenly while the ordinates are spaced quadratically, this locus is a
parabola. In fact, one can readily see that this locus is simply the i-v curve of Fig. 13, but shifted
Fig. 15 Complete i-v characteristics of an enhancement nMOSFET, and its regions of operation.
Fig. 14 PSpice circuit to display the complete i-v characteristics of an nMOSFET.
V
t
= 1.0 V
W = 2 m
L = 1 m
k = 50 A/V
2
= 0.05V
-1
2004 Sergio Franco Ch. 3 - MOSFETs Page 24 of
to the left by V
t
.
The saturation-region curves, when extrapolated towards the left, converge to a common point located
at 1/ on the v
DS
axis. This is shown in the compressed rendition of Fig. 16. Also called the Early
voltage V
A
by analogy with a similar behavior on the part of BJTs, where this term is used, this
voltage is simply V
A
= 1/. Typically, V
A
is on the order of 10 to 100 V. In our example, V
A
= 1/0.05
= 20 V, so the intercept is located at v
DS
= V
A
= 20 V. As a rule, the shorter the channel, the lower
the value of V
A
. This is expressed by saying that V
A
scales with L.
The Depletion nMOSFET
The i-v characteristics of the depletion-type nMOSFET are similar to those of its enhancement-type
counterpart, except that the depletion device is already on for v
GS
= 0 V. This is depicted in Fig. 17,
whose curves were obtained with the PSpice circuits of Figs. 12 and 14, but with V
t
changed to 1.0 V.
The curve of Fig. 17a is similar to that of Fig. 13, except that it is shifted to the left because V
t
is now
negative. We can either turn the device further on by raising v
GS
above 0 V, or turn it gradually off by
lowering v
GS
below 0 V, until it shuts off completely once v
GS
reaches V
t
(1.0 V in our example). The
effect of sweeping v
GS
can be appreciated also from Fig. 17b, where we note that the curve correspond-
Fig. 17 The i-v curves of the depletion nMOSFET.
Fig. 16 Effect of channel-length modulation on the i-v chacteristics.
2004 Sergio Franco Ch. 3 - MOSFETs Page 25 of
ing to v
GS
= 0 V is somewhere in the middle. The locus of the pinchoff points is still v
DS
= V
GS
V
t
(= V
GS
+ 1.0 V in our example.)
A particularly interesting application arises when the gate and source of a depletion-type
nMOSFET are tied together as in Fig. 18a, thus resulting in a two-terminal device with V
GS
= 0. The
corresponding curve in Fig. 18b indicates current-source behavior, at least as long as the device is
operated in saturation. Such a device can be used to bias other devices.

Example 8
Assuming the data of Fig. 12 but with V
t
= 1.0 V for the MOSFET of Fig. 18a, find:
(a) The range of voltages over which it exhibits current-source behavior
(b) The current at the edge of saturation.
(c) The output resistance r
o
.
(d) The value of W/L needed to raise the current at the edge of saturation to 0.5 mA.
Solution
(a) The saturation region occurs for v > V
(EOS)
= V
OV
= 0 V
t
= 0 (1.0) = 1.0 V.
(b) I
(EOS)
= (k/2)(0 V
t
)
2
(1 + V
(EOS)
) = (100/2)(1)(1 + 0.051) = 52.5 A.
(c) r
o
= 1/I = 1/(0.0552.510
-6
) = 381 k.
(d) W/L = (2/1)(500/52.5) 19.

The pMOSFET and Comparison with the nMOSFET.


The voltage-current relationships developed for the nMOSFET can be extended to the pMOSFET,
provided we reverse all current directions and all voltage polarities. The two devices are compared in
Fig. 19, where voltage is likened to height, so higher voltages are at the top and lower voltages at the
bottom. Following is a summary of similarities and differences between the two devices. (When
necessary, subscript n and p are used to distinguish between the devices.)
The current i
D
flows into the drain of the nMOSFET, but out of the drain of a pMOSFET.
In a p-channel, i
D
consists of holes flowing from higher potential (source) to lower potential (drain).
In an n-channel, i
D
consists of electrons flowing from lower potential (source) to higher potential
(drain).
In both devices, the source and drain regions are interchangeable. The source will always be the
(a) (b)
Fig. 18 The depletion nMOSFET as a current source.
2004 Sergio Franco Ch. 3 - MOSFETs Page 26 of
region at lower potential in an nMOSFET, and that at higher potential in a pMOSFET.
To turn on an n channel, the gate voltage v
G
must be raised above the source voltage v
S
by at least V
tn
,
or v
GS
> V
tn
. The overdrive voltage is V
OV
= V
GS
V
tn
.
To turn on a p channel, the gate voltage v
G
must be lowered below the source voltage v
S
by at least
V
tp
. In the case of enhancement-types, which are more popular than depletion types, the turn-on
condition is less confusingly expressed as v
SG
> (V
tp
. The overdrive voltage is V
OV
= V
SG
(V
tp
.
If v
DS
is large enough to satisfy v
DS
> V
OV
, then the n channel is operating in saturation,
2
( ) (1 )
2
n
D GS tn n DS
k
i V V v = + for v
DS
> V
OV
(23a)
If v
SD
is large enough to satisfy v
SD
> V
OV
, then the p channel is operating in saturation,
2
( ) (1 )
2
p
D SG tp p SD
k
i V V v = + for v
SD
> V
OV
(23b)
If v
DS
is small enough to satisfy v
DS
< V
OV
, then the n channel is operating in the triode region,
2
1
( )
2
D n GS tn DS DS
i k V V v v
(
=
(

for v
DS
< V
OV
(24a)
If v
SD
is small enough to satisfy v
SD
< V
OV
, then the p channel is operating in the triode region,
2
1
( )
2
D p SG tp SD SD
i k V V v v
(
=
(

for v
SD
< V
OV
(24b)
The device transconducance parameters for the nMOSFET and the pMOSFET are, respectively,
n
n n
n
W
k k
L
= (25a)
Fig. 19 Comparing voltage polarities, current directions, voltage levels, and voltage ranges for the
enhancement nMOSFETS and pMOSFETs.
2004 Sergio Franco Ch. 3 - MOSFETs Page 27 of
p
p p
p
W
k k
L
= (25b)
The process transconducance parameters for the nMOSFET and the pMOSFET are, respectively,
n ox
n
ox
k
t

= (26a)
p ox
p
ox
k
t

= (26b)
To avoid the inadvertent turn-on of the internal pn junctions, the bodies must be biased so that V
SB
> 0
for the nMOSFET, and V
BS
> 0 for the pMOSFET.
Body bias in the nMOSFET shifts V
tn
in the positive direction as
0
2 2
tn tn n SB p p
V V V
(
= + +
(

(27a)
Body bias in the pMOSFET shifts V
tp
in the negative direction as
0
2 2
tp tp p BS n n
V V V
(
= +

(27b)
In general, the parameters V
tn0
, V
tp0
,
n
,
p
,
n
, and
p
are found experimentally via suitable measurements.
As we know, the transconductance parameters of Eqs. (26) are proportional to the mobilities (
n
or
p
) of the charges intervening in the main current in the device. This is not surprising, as MOSFET
current is of the drift type. When studying BJTs, in the previous chapter, we have encountered a similar
parameter, namely, the saturation current I
s
, which instead is proportional to the diffusivity (D
n
or D
p
) of
the charges responsible for the main current in the device. This is so because BJT current is of the
diffusion type. For a given doping density, electron mobility and diffusivity are two to three times higher
than hole mobility and diffusivity, respectively. For these reasons, n-channel FETS are preferred over p-
channel types, and npn BJTs are preferred over pnp types.
Large-Signal Circuit Models in the Saturation Region
Figures 20 and 21 show the circuit models of the nMOSFET and the pMOSFET operating in saturation.
Also called large-signal models (to distinguish them from the small-signal models to be introduced later,)
they are used primarily in dc calculations. Since the gate is the plate of a capacitor, the G-S (or input)
port appears as an open circuit, at least at dc. Consequently, at dc we have i
G
= 0, indicating that i
S
= i
D
.
Fig. 20 Large-signal model for the saturated nMOSFET.
2004 Sergio Franco Ch. 3 - MOSFETs Page 28 of
The D-S (or output) port is modeled with its Norton equivalent consisting of a dependent current source
calculated at the edge of saturation, and an output resistance to model the slight increase of i
D
with v
DS
(or
v
SD
).
To simplify our hand calculations in the course of dc analysis, we shall often ignore the output
resistance, which is equivalent to assuming = 0. Also, for the enhancement pMOSFET, we shall
express the dependent-source value in the form (k
p
/2)(V
SG
|V
tp
|)
2
, more closely resembling that of the
nMOSFET.
Fig. 21 Large-signal model for the saturated pMOSFET.