3  MOSFETs Page 1 of
MOS FIELDEFFECT TRANSISTORS
2004 Sergio Franco
San Francisco State University
(Updated February 9, 2005)
No part of these notes may be reproduced, stored, transmitted, or distributed in any form or by any means, electronic
or in photocopy form, without the prior written permission by the author. 2004 Sergio Franco.
1. Device Structure
2. The Threshold Voltage
3. The Channels Characteristics
4. The iv Characteristics of MOSFETs
The age of semiconductor electronics begun when the triode function (a controlled current source) was
implemented on a piece of semiconductor material. This occurred in 1947 with the invention of the
bipolar junction transistor (BJT), the first working realization of the semiconductor triode concept.
However, neither is the BJT the only transistor type possible, nor was it the first transistor to be
conceived. In fact, as early as 1925, Julius Lilienfeld patented a device of the type nowadays known as
the fieldeffect transistor (FET). However, because of fabrication difficulties at the time, he could never
get it to work. It took another 35 years or so before Dawon Kahng and John Atalla of Bell Laboratories
demonstrated, in 1960, the first FET of the so called metaloxidesemiconductor (MOS) type, or
MOSFET for short.
The closest MOSFET counterpart of the vacuumtube triode is what is nowadays known as the n
channel depletiontype MOSFET (nchannel DMOSFET). Briefly stated, a DMOSFET consists of a thin
layer of ntype material called the channel, which forms a parallelplate capacitor with an electrode called
the gate. One end of the channel, called the source, acts as a copious source of free electrons, which are
designed to flow to the opposite end of the channel, aptly called the drain. The roles of source and drain
are similar to those of emitter and collector in the BJT, or cathode and plate in the triode. The role of the
gate, similar to that of the base in the BJT or the grid in the triode, is to modulate the channels conduct
ivity and thus control the current flow from source to drain. Specifically, driving the gate voltage
negative will induce a positive charge in the channel, at the expense of a reduction in the concentration of
free electrons there. For a sufficiently negative gate voltage, the channel will be depleted of free electrons
and current flow will cease altogether. By a hydraulic analogy, FET behavior can be likened to a garden
hose being squeezed for the purpose of controlling water flow, or even shutting it off completely.
Following the successful demonstration of the first MOSFET, the new technology was put to use
especially in those applications in which the advantages of smaller size and lower power consumption of
the MOSFET made it competitive with its BJT counterpart. The first batterypowered electronic
calculators and wristwatches made use precisely of this new technology. Also, a new digital integrated
circuit (IC) family known as complementary MOS (or CMOS for short) was introduced by RCA as a low
power alternative to the existing IC bipolar families of the TTL and ECL types. In 1971 Intel used MOS
technology to develop the first microprocessor. Since then, IC electronics has advanced exponentially
and has penetrated virtually every aspect of modern life. This impressive growth has been governed by
Moores law, roughly stating that thanks to continued advances in IC fabrication, the number of devices
that can be integrated on a given chip area doubles every approximately 18 months. Originally
2004 Sergio Franco Ch. 3  MOSFETs Page 2 of
formulated in 1965, this law still holds to this day, though it has been observed that technology is bound
to approach physical limits that will eventually lead to the demise of this law.
Over the years, the MOSFET has overtaken its BJT predecessor especially in highdensity ICs
electronics, thanks to the aforementioned MOSFET advantages of smaller size and lower power
consumption. Nonetheless, there are applications such as highperformance analog electronics, in which
the BJT continues to be the preferred transistor type. To exploit the advantages of both BJTs and
MOSFETs, the two device types are sometimes fabricated simultaneously on the same chip. The
resulting technology, aptly called biCMOS technology, provides even greater design opportunities than
the allBJT or allMOSFET technologies individually. Also, contemporary ICs often combine digital as
well as analog functions on the same chip, this being the reason for the name mixedsignal or also mixed
mode ICs.
There is no question that microelectronics is one of the most exciting, challenging, and rapidly
evolving fields of human endeavor. The beginner may feel overwhelmed by all this, and rightly so. But,
as we embark upon the study of todays dominant processes and devices, we will try to focus on general
principles that transcend the particular technological milieu of the moment and that we can apply to
understand new processes and devices as they become available and commercially mature. Focus on
general principles, combined with continuing education, is a necessity for the young engineer aiming at
establishing and maintaining a satisfying career in a seemingly everchanging field.
This chapter begins with a study of the physical structure of the MOSFET, the underlying
semiconductor principles, and the devices electrical characteristics. The devices under scrutiny are of the
socalled longchannel type (channel lengths > 1 m). Their behavior conforms fairly well to theoretical
prediction, so they are easier to model and the beginner will find them easier to grasp. However, the
devices available in todays ever shrinking IC processes are of the shortchannel type (channel lengths of
fractions of 1 m). At such smaller sizes, a number of higherorder effects arise, particularly carrier
velocity saturation, which may cause significant departure from longchannel behavior. Aptly called
shortchannel effects, they require more complex formalism and sophisticated models as the price for
providing more realistic results. These advanced models, while realizable in computer simulation, are too
complicated for hand analysis. We shall nevertheless continue to rely on the formalism and models of
longchannel devices to gain a quick if only approximate feel for device behavior, and then turn to
computer simulation for more accurate results.
Next, we investigate the FET in its two most important applications, namely, as an amplifier in
analog electronics, and as a switch in digital electronics. Basic singletransistor amplifier configurations
are covered in detail, along with a variety of circuit examples. The amplifiers investigated are of the so
called discrete type, because they can be built using discrete transistors, resistors, and capacitors. (In this
respect, a very convenient device to experiment with in the lab is the CD4007 CMOS Transistor Array.)
Though nowadays MOSFET amplifiers are implemented in IC form, the motivation for studying discrete
designs is primarily pedagogical as discrete circuits are somewhat easier to grasp, and yet they reveal
important aspects that apply to IC implementations as well. Once we master the basics of discrete design,
we will be in a better position to tackle the more sophisticated techniques of IC amplifier design as we
proceed.
The chapter concludes with a detailed analysis of the CMOS inverter/amplifier as a simple yet
important IC building block that demonstrates the unique advantages of CMOS technology both in the
analog and digital domains. Basic CMOS logic gates are also addressed.
2004 Sergio Franco Ch. 3  MOSFETs Page 3 of
1. Device Structure
Figure 1 shows, in simplified form, the structure of the nchannel, metaloxidesemiconductor (MOS)
fieldeffect transistor (FET), or nMOSFET for short. The device is fabricated through a complex
sequence of steps involving pattern definition, oxidation, diffusion, ion implantation, material deposition
and material removal, on a wafer of lightlydoped ptype silicon (p
bulk and the metal connection, so it will play no role in our analysis. The well
known formula for parallelplate capacitance gives, in the present case, C =
ox
(WL)/t
ox
, where W and L
are the channelregions width and length depicted in Fig. 1,
ox
is the permittivity of the oxide layer, and
t
ox
is its thickness. To make analysis independent of the particular device size, it is convenient to work
with the capacitance per unit area,
ox
ox
ox
C
t
= (1)
(a) (b)
Fig. 3  Gatebody capacitor (a) at 0V bias, and (b) biased at
0
to eliminate the spacecharge layers.
2004 Sergio Franco Ch. 3  MOSFETs Page 6 of
Given that silicon oxide has
ox
= 345 fF/cm, a fabrication process with, say, t
ox
= 10 nm gives C
ox
= 345
nF/cm
2
, or 3.45 fF/(m)
2
, as it is frequently expressed.
The gateoxidebulk structure is reminiscent of the familiar pn junction, except that the n and p
materials are now separated by an insulator layer that prevents direct current flow. However, if an
external conducting path is established, for instance by shorting G and B with a wire as in Fig. 3a,
electrons will diffuse from the electronrich n
+
gate, through the wire, to the electronstarved p
bulk,
leaving behind a layer of immobile positive donor ions in the gate. Once in the bulk, these electrons
recombine with holes there, leading in turn to the formation of a layer of immobile negative acceptor ions
in the bulk. Being attracted to each other, the two layers will be concentrated near the gateoxide and
siliconoxide interfaces, respectively. Just as in the case of the pn junction, the creation of these space
charge layers results in an electric field from the gate, through the oxide, to the bulk, and an equilibrium
condition is reached whereby this field will oppose any further diffusion of electrons. Associated with
this field is a builtin potential
0
across the gatebulk structure,
0
=
n
p
, where
ln
i
p T
A
n
V
N
= (2a)
is the equilibrium electrostatic potential, also called Fermi potential, of the bulk, and
ln
D
n T
i
N
V
n
= (2b)
is the equilibrium electrostatic potential, or Fermi potential of the gate. Here, V
T
= kT/q is the thermal
voltage (V
T
26 mV at T = 300 K), N
A
and N
D
are the doping densities in the bulk and gate materials, and
n
i
is the intrinsic electronhole concentration of silicon (n
i
1.4510
10
/cm
3
). Since both N
A
and N
D
are
greater than n
i
, we have
p
< 0 and
n
> 0. Moreover, since N
A
and N
D
appear in the argument of the
logarithmic function,
p
and
n
are not overy sensitive to variations in the doping doses.
An ordinary capacitance with its plates shorted together will be in the discharged state. However,
if the plates are of dissimilar materials, as in the present case, we have Q 0 even though V
GB
= 0! If we
want to drive Q to zero, we need to apply a voltage V
GB
of equal magnitude but opposite polarity as
0
, or
V
GB
=
0
=
p
n
< 0 (see Fig. 3b). This value of V
GB
is also called the flatband voltage because of its
effect on the energy bands of the bulk material. We shall use this voltage as the reference voltage for our
analysis to follow.
Example 1
Assuming N
A
= 10
16
/cm
3
and N
D
= 10
20
/cm
3
, find the electrostatic potentials as well as the value of V
GB
needed to eliminate the spacecharge layers.
Solution
From Eq. (2),
10
16
1.45 10
0.026ln
10
p
= = 0.35 V
20
10
10
0.026ln
1.45 10
n
= =
+0.59 V
To achieve charge neutrality in the gate and bulk, the gate must be biased more negative than the body by
V
GB
=
0
= 0.35 0.59 = 0.94 V.
Remark
Were the gatebulk a regular np junction, with V
GB
= 0.94 V it would be forwardbiased quite heavily,
2004 Sergio Franco Ch. 3  MOSFETs Page 7 of
thus conducting a large forward current from the pbulk to the ngate. In the present case, however, no
current flows because of the oxide insulator separating the two, giving further credence to the name FET.
Inversion
Let us now gradually increase V
GB
, starting at V
GB
=
0
(or V
GB
= 0.94 V in our example). The effect of
this increase is to reestablish space chargelayers on both sides of the oxide, uncovering positive charge
in the gate and negative charge in the bulk. We are particularly interested in the situation in the bulk, so
we will ignore that in the gate, keeping in mind that the charge in the gate is always of equal magnitude
but opposite polarity as the charge in the bulk. The situation in the bulk is depicted in Fig. 4, where we
have chosen the origin of the xaxis to coincide with the oxidebulk interface, a surface that will play an
important role in our analysis. Initially, the negative charge in the bulk results from the negative acceptor
ions there: the holes are simply pushed away from the oxidebulk interface, leaving behind the bound
ions. The resulting spacecharge layer is also referred to as a depletion layer because it is devoid of holes.
However, as we increase V
GB
from
0
, not only does the depletion layer in the bulk widen, but also the
surface potential (0) increases. When (0) changes from negative to positive, the bulk near the surface
Fig. 4 The situation in an nMOSFET
just before the onset of strong inversion.
2004 Sergio Franco Ch. 3  MOSFETs Page 8 of
is said to undergo inversion because it turns from ptype to ntype, at least electrostatically speaking. For
this reason, the bulk region near the surface is called inversion layer.
With reference to Fig. 4, we observe that the formation of the spacecharge layers results in the
creation of an electric field E(x). The field strength as a function of x is readily visualized by counting the
field lines, each of which starts on a positive ion in the gate and ends on a negative ion in the bulk. We
are interested in the lines in the bulk, which is maximum at the oxidebulk interface (x = 0), and decreases
linearly with x to finally drop to zero at the edge of the depletion layer (x = x
p
). We can readily find a
relationship between the maximum strength E
m
and the layers width x
p
using Gauss theorem. In a one
dimensional case such as ours, this theorem is expressed as dE/dx = /
si
, where is the charge density in
the depletion layer ( = qN
A
), and
si
is silicons permittivity (
si
= 1.04 pF/cm). By inspection, we have
dE/dx = E
m
/x
p
= qN
A
/
si
, so
A p
m
si
qN x
E
= (3)
Electric field and potential are in turn related as E = d/dx. Rewriting as d = Edx and integrating
both sides from x = 0 to x = x
p
, we get
0 0
( )
p p
x x
d E x dx =
The term on the left is simply the difference
p
(0), while the term on the right is the just area of the
triangle under the E curve, or (x
p
E
m
), so
(0)
2
m p
p
E x
=
Using Eq. (3) to eliminate E
m
, we obtain an expression for the depletionlayer width as a function of the
surface potential (0),
2
(0)
si
p p
A
x
qN
( =
Onset of Strong Inversion
We are interested in the situation at which the surface potential attains the value (0) =
p
(or
+0.35 V in our example), for then the electron concentration n in the inversion layer becomes equal to the
hole concentration p in the bulk, or n = N
A
(= 10
16
/cm
3
in our example). This situation is said to mark the
onset of strong inversion. Using subscript 0 to mark this onset, we now wish to find the gatebody bias
V
GB0
required to bring about this onset itself. To this end, we first substitute (0) =
p
to find the
depletionlayer width at the onset of strong inversion
0
2
2( )
si
p p
A
x
qN
= (4)
Next, we observe that the unitarea charge in the bulk depletionlayer is Q
b0
= qN
A
x
p0
. Using Eq. (4),
0
2 2( )
b A si p
Q qN = (5)
2004 Sergio Franco Ch. 3  MOSFETs Page 9 of
This negative bulk charge is matched by a positive charge of equal magnitude in the gate. By the
capacitance law, the voltage required to sustain this charge situation is V
ox
= Q
b0
/C
ox
. Finally, the gate
tobody voltage drop required to bring about the onset of strong inversion is, by KVL, V
GB0
=
0
+ 2(
p
)
+ V
ox
, or
0
0 0
2
b
GB p
ox
Q
V
C
= (6)
In words: to bring about the onset of strong inversion, we need to increase V
GB
, starting from the
reference level
0
, first by the term 2(
p
) to raise the surface potential (0) from
p
, through zero, to
p
, and then by the term Q
b0
/C
ox
to sustain the unitarea charge Q
b0
in the bulk depletionlayer.
Example 2
Assuming the doping densities of Example 1, along with t
ox
= 25 nm, find the values of all relevant
physical quantities at the onset of strong inversion.
Solution
The unitarea capacitance is
Fig. 5 Situation at the onset of strong inversion.
2004 Sergio Franco Ch. 3  MOSFETs Page 10 of
15
6
345 10
138
2.5 10
ox
C
= =
nF/cm
2
At the onset of strong inversion, the depletionlayer width is
12
0 19 16
2 1.04 10
2(0.35) 301
1.602 10 10
p
x
= =
nm
The corresponding electric field intensity is
19 16 6
0 12
1.602 10 10 30.1 10
46.4
1.04 10
m
E
= =
kV/cm
The unitarea charge in the bulk depletionlayer is
19 16 12
0
4 1.602 10 10 1.04 10 (0.35) 48.3
b
Q
= = nC/cm
2
Finally, the required gatebody voltage drop is, by Eq. (6),
0
48.3
0.94 2( 0.35)
138
GB
V
= = 0.94 + 0.70 + 0.35 = +0.11 V
Once strong inversion is reached, the surface potential (0) and, hence, the depletionlayer width
x
p
, will change very little with the applied voltage V
GB
because (0) depends on V
GB
only logarithmically.
Any increase V
GB
above V
GB0
will essentially be accompanied by an increase Q
n
C
ox
V
GB
in the
electron charge of the inversion layer. These electrons are supplied by the n
+
source region (hence the
reason for its name), where they exist in abundant supply. In fact, in order for these electrons to be
enticed into the inversion layer, the gate must slightly overlap the source region to allow for the fringe
electric field to attract electrons from the source to the channel. As mentioned, the advantage of the
silicongate process is that it is a selfaligning process.
Example 3
Assuming the data of Example 2, find the change Q
n
brought about by a 1V increase V
GB
in strong
inversion. Compare with the depletionlayer charge Q
b0
.
Solution
We have Q
n
C
ox
V
GB
= (138 nF/cm
2
)(1 V) = 138 nC/cm
2
, indicating that the inversion
layer charge (Q
n
( can be significantly greater than the depletionlayer charge (Q
b0
( (= 48.3 nC/cm
2
in our example), even though the inversion layer is much thinner than the depletion layer.
Example 4
Assuming the data of Example 2, along with a surface state density N
ox
= 210
11
positive ions/cm
2
,
(a) Find the native threshold of the nMOSFET.
(b) Find the implant type and dosage N
i
needed for V
t0
= +1.0 V.
(c) Find the implant type and dosage N
i
needed for V
t0
= 1.0 V.
Solution
(a) We have Q
ox
= qN
ox
= 1.60210
19
210
11
= 32 nC/cm
2
. So, using the result of Example 2,
0
32
0.11
138
t
V = = 0.122 V
(b) To raise V
t0
= from its native value of 0.122 V to +1.0 V, we need a ptype implant, such as
boron, which will contribute negative ions in the bulk near the surface. Imposing
19
9
1.602 10
1.0 0.122 0.122 0.122
138 10
i i i
ox ox
Q qN N
C C
+ = = = +
gives N
i
= 9.6610
11
ptype ions/cm
2
.
(c) To lower V
t0
from its native value of 0.122 V to 1.0 V, we need an ntype implant, such as
phosphorus, which will contribute positive ions in the bulk near the surface. Imposing
(a) (b)
Fig. 6  The onset of strong inversion in (a) the nMOSFET and (b) the pMOSFET.
2004 Sergio Franco Ch. 3  MOSFETs Page 12 of
19
9
1.602 10
1.0 0.122 0.122 0.122
138 10
i i i
ox ox
Q qN N
C C
= = =
gives N
i
= 7.5610
11
ntype ions/cm
2
.
Example 5
(a) For the enhancement nMOSFET of Example 4(b), find V
t
at V
SB
= 1 V, and at V
SB
= 5 V.
(b) For the depletion nMOSFET of Example 4(c), find V
t
at V
SB
= 1 V, and at V
SB
= 5 V.
Solution
19 16 12
9
2 1.602 10 10 1.04 10
0.418
138 10
= =
V
1/2
(a) For the enhancement nMOSFET we have
V
t
(V
SB
= 1 V) =
( )
1.0 0.418 1 0.7 0.7 1.0 0.195 1.195 + + = + = V.
V
t
(V
SB
= 5 V) =
( )
1.0 0.418 5 0.7 0.7 1.0 0.648 1.648 + + = + = V.
(b) For the depletion nMOSFET we have
V
t
(V
SB
= 1 V) =
( )
1.0 0.418 1 0.7 0.7 1.0 0.195 0.805 + + = + = V.
V
t
(V
SB
= 5 V) =
( )
1.0 0.418 5 0.7 0.7 1.0 0.648 0.352 + + = + = V.
The example indicates that the effect of body bias is to shift the threshold voltage of an
nMOSFET in the positive direction, regardless of whether it is a depletion or enhancement type. For a
pMOSFET, the shift is in the negative direction. The dependence of V
t
upon the body bias is referred to
as the body effect, and the body itself is sometimes referred to as back gate because it influences the
inversion layer like the gate, if in the opposite direction.
Exercise 1
Show that for a polysilicongate technology, the first two terms in the threshold voltage of an nMOSFET
can be expressed concisely as (
0
2
p
) = V
T
ln (N
A
/N
D
).
(15)
This resistance depends also on the W/L ratio, also called the aspect ratio, indicating that by proper choice
of this ratio, the IC designer can set this resistance to virtually any value for a given overdrive V
OV
.
Example 6
Assuming
n
= 600 cm
2
/Vs, C
ox
= 83 nF/cm
2
, and V
t
= 1.0 V,
(a) Specify the W/L ratio so that r
DS
= 1 k for V
GS
= 5 V.
(b) Calculate r
DS
for V
GS
= 4 V, 3 V, 2 V, 1 V, 0 V.
Solution
(a) By Eq. (13),
9
' 600 83 10 50 k
= A/V
2
. Using Eq. (15) to impose
3
6
1
10
50 10 ( / )(5 1) W L
=
we get W/L = 5. Consequently, k = (50 A/V
2
)5 = 250 A/V
2
.
Fig. 11 The complete i
D
v
DS
characteristic for a given overdrive voltage V
OV
= V
GS
V
t
> 0. Note that
V
DS(EOS)
= V
OV
2004 Sergio Franco Ch. 3  MOSFETs Page 19 of
(b) By Eq. (15), for V
GS
= 4 V, we get
r
DS
=
6
1
250 10 (4 1)
= 1.333 k.
Likewise, for V
GS
= 3 V we find r
DS
= 2 k, and for V
GS
= 3 V, we find r
DS
= = 4 k. For V
GS
1 V, the
MOSFET is in cutoff, and r
DS
= .
As we keep increasing v
DS
, the channel becomes progressively thinner at the drain end, and the
quadratic term becomes more and more significant in Eq. (11). Consequently, the slope of the curve
decreases, indicating a corresponding increase in the dynamic resistance of the channel. This region of
operation is called the triode region by analogy with vacuum tubes, which exhibit similar characteristics.
We also observe in Fig. 8 that the depletion layer associated with the bodydrain junction widens as we
keep increasing v
DS
.
The Pinchoff Point
Once v
DS
achieves the special value
V
DS(EOS)
= V
GS
V
t
= V
OV
(16)
the channel thickness at the drain end reduces to zero, as depicted in Fig. 8c, and the corresponding point
on the i
D
v
DS
curve is referred to as the pinchoff point. The current at this point is readily found by
substituting v
DS
= V
GS
V
t
in Eq. (11). The result gives
2
(EOS)
( )
2
D GS t
k
I V V = (17)
This can also be expressed as
2 2
(EOS) (EOS)
( / 2) ( / 2)
D OV
I k V k V = = . As we shall see next, this point marks the
beginning, or edge, of the saturation region (EOS).
The Saturation Region
If we raise v
DS
above the critical value V
DS(EOS)
, the voltage at the pinchoff point continues to remain at
V
DS(EOS)
, and the excess difference v
DS
V
DS(EOS)
is dropped across a narrow depletion layer of width L
between the pinchoff point and the edge of the drain. As depicted in Fig. 8d, the pinchoff point moves
slightly away from the drain, in effect shortening the channel by a small amount L. This effect, aptly
referred to as channellength modulation, is investigated by replacing L with L L in Eq. (12),
'
W
k k
L L
=
This can be rewritten as
( ) ' ' 1 ' 1
(1 / )
DS
W W L W
k k k k v
L L L L L L
 
= + +

\ .
(18)
where we have conformed to the established practice in the literature to assume that the fractional change
L/L (L/L << 1) be linearly proportional to v
DS
. The proportionality constant , in V
1
, is called the
2004 Sergio Franco Ch. 3  MOSFETs Page 20 of
channellength modulation parameter. Typically, it is on the order of 0.01 to 0.1 V
1
, and for simplicity it
is usually ignored in the course of DC hand calculations. Substitution of Eq. (18) into Eq. (17) gives the
i
D
v
DS
characteristic in the saturation region, so called because i
D
increases with v
DS
only slightly there, in
effect saturating,
2
( ) (1 )
2
D GS t DS
k
i V V v = + (19)
The slope in saturation is the reciprocal of a resistance r
o
called the output resistance of the
MOSFET. Differentiating Eq. (19), we obtain
(EOS)
1
D
D
o DS
i
I
r v
= =
= (21)
Its units are A/V, or more likely A/V in micropower devices. Differentiating Eq. (19) but with = 0 for
simplicity, and suitably manipulating, we find three different forms for calculating transconductance,
2
m D
g kI = (22a)
( )
m GS t OV
g k V V kV = = (22b)
2
0.5( )
D D
m
GS t OV
I I
g
V V V
= =
(22c)
Though the three forms are equivalent, each provides different insight. The first form indicates that g
m
V
t
= 1.0 V
W = 2 m
L = 1 m
k = 50 A/V
2
= 0.05V
1
Fig. 12  Diodeconnected enhancement nMOSFET.
2004 Sergio Franco Ch. 3  MOSFETs Page 22 of
increases with the square root of I
D
. By contrast, in a bipolar junction transistor (BJT), g
m
is linearly
proportional to the collector current I
C
, or g
m
= I
C
/V
T
, where V
T
= 26 mV is the thermal voltage. Also, the
second form indicates that g
m
is proportional to the overdrive voltage V
OV
= V
GS
V
t
.
Example 7
Assuming the nMOSFET data of Fig. 12, but with = 0 to simplify the calculations,
(a) Find V
GS
for I
D
= 1 mA. Compare with Fig. 13, and comment.
(b) Find g
m
at that point, and compare with the g
m
of a bipolar junction transistor (BJT) operating
at the same current level.
(c) Find W/L to raise the g
m
of the FET to the same value as that of the BJT.
Solution
By Eq. (12), k = 5010
6
(2/1) = 100 A/V
2
.
(a) Using Eq. (19) with = 0, we get 110
3
= (10010
6
)(V
GS
1.0)
2
, or V
GS
= 5.472 V.
This is higher than the value (5 V) predicted by Fig. 13 because we have assumed = 0. This gives an
idea about the error incurred by ignoring .
(b) By Eq. (22a),
6 3
2 2 100 10 10 0.447
m D
g kI
= = = mA/V. By contrast, at 1 mA a BJT
gives g
m
1/26 = 38.5 mA/V.
(c) Since g
m
is linearly proportional to k , and thus to / W L , we impose a simple proportion,
/ / 2/1 38.5/ 0.447 W L =
which gives W/L 14,800, an outlandish number. This example illustrates a notorious feature of
MOSFETs compared to BJTs, namely, their generally much lower g
m
values. Indeed, if we use Eq. (22c),
we get g
m
= I
D
/[(5.472 1)/2] = I
D
/(2,236 mV), which compares quite unfavorably with the BJT relation
g
m
= I
C
/(26 mV).
Example 8
Assuming the data of Fig. 12 but with V
t
= 1.0 V for the MOSFET of Fig. 18a, find:
(a) The range of voltages over which it exhibits currentsource behavior
(b) The current at the edge of saturation.
(c) The output resistance r
o
.
(d) The value of W/L needed to raise the current at the edge of saturation to 0.5 mA.
Solution
(a) The saturation region occurs for v > V
(EOS)
= V
OV
= 0 V
t
= 0 (1.0) = 1.0 V.
(b) I
(EOS)
= (k/2)(0 V
t
)
2
(1 + V
(EOS)
) = (100/2)(1)(1 + 0.051) = 52.5 A.
(c) r
o
= 1/I = 1/(0.0552.510
6
) = 381 k.
(d) W/L = (2/1)(500/52.5) 19.