ARJUN ASHOK.

Sayoojyam

Thulichery, Civil Station P.O, Kannur, Kerala, India 670002 E-mail: arjunashok619@gmail.com Phone: +91-7204555341

CAREER OBJECTIVE RESEARCH INTERESTS CURRENT STATUS COMPUTER SKILLS

To pursue challenging research activities in VLSI frontend field which will provide me the platform to use my technical knowhow and abilities, to contribute innovative creations and solutions to the world. Low-power VLSI, Computer Architecture, Universal Serial Bus. Intern at WhizChip Design Technologies Pvt. Ltd, Bangalore. Working at AMD, Bangalore in self-test diagnosis. Tools VCS, Design Compiler, NC-Verilog, Conformal, ModelSim, Xilinx-ISE Languages - Verilog, System Verilog, C, C++, PERL, UNIX
MANIPAL CENTRE FOR INFORMATION SCIENCE, Manipal, India Master of Science (MS) in VLSI CAD. (Currently pursuing) Secured a Cumulative Grade Point Average (CGPA) of 9.3/10 so far. AMRITA SCHOOL OF ENGINEERING, AMRITA VISHWA VIDYAPEETHAM, Amritapuri Campus, India

EDUCATION

Bachelor of Technology in Electronics and Communication Engineering Secured distinction with a Cumulative Grade Point Average (CGPA) of 8.72/10 SREE NARAYANA VIDYA MANDIR, Talap, Kannur, Kerala, India Central Board of Secondary Education, 12th Standard, June 2006 Secured an aggregate of 85% in Science Stream. Central Board of Secondary Education, 10th Standard, June 2004 Secured an aggregate of 81%.

ACHEIVEMENTS

Third best project award at Intel Embedded Challenge 2010. Project also won a Gold medal as it was chosen as the best project by the Intel techies. First prize for technical paper presentation contest held in conjunction with Xplore10, tech-fest at Government College of Engineering, Kannur. Third prize for technical quiz contest held in conjunction with SRISHTI 2008, techfest at PSG College of technology, Coimbatore. Power-Efficient Cache Design Using Dual-Edge Clocking Scheme in Sun OpenSPARC T1 and Alpha AXP Processors (BAIP 2010) Highly power efficient, uncompromised performance cache design using dual-edged clock. (ICCSIT 2009) Study of variation in process parameters and supply voltage in various CMOS technologies. (SCOReD 2008) Chief coordinator of PIC EXEL10, National level PIC Microcontroller workshop at Amrita School of Engineering, Kollam Campus. Teaching assistant for PIC EXEL08 and PICTRIS09, PIC Microcontroller workshops at Amrita School of Engineering, Kollam Campus.

PUBLICATIONS

ACTIVITIES

Xplan test-plan development of Protocol Layer in USB 3.0 (Currently working) Development of test-plan for verification of USB 3.0 protocol layer and implementation using the tool Xplan from Whizchip. Guidance: Mr. Pranip (Project Mentor, Whizchip Design Technologies) Verification of Protocol Layer of USB 2.0 protocol designed (March 2011) Performed functional verification on USB 2.0 protocol layer architecture using System Verilog test-bench architecture and rectified the bugs found. Guidance: Mr. Sreenu Yerabolu (Project Manager, VLSI Design, WhizChip Design Technologies Pvt Ltd) and Mr. Sundaresan C(Senior grade Lecturer, MCIS, Manipal) Design of Arbiter (January 2011) The project was specified by Whizchip. The design was about arbitration of communication between 8 masters and 4 slaves through a single bus based on a protocol. Guidance: Mr. Sreenu Yerabolu (Project Manager, VLSI Design, WhizChip Design Technologies Pvt Ltd) and Mr. Sundaresan C(Senior grade Lecturer, MCIS, Manipal) Design of Protocol Layer of USB 2.0 protocol (September 2010) Designed the protocol layer of USB 2.0 architecture in Verilog HDL and performed simulation in Synopsys. Guidance: Mr. Sundaresan C(Senior grade Lecturer, MCIS, Manipal) Gesture based wheel chair control (May 2010) Developed a robust, real-time, vision based hand recognition engine reliable enough for steering controls application, especially of wheelchairs for the quadriplegics. This project won third prize in Intel Embedded Challenge10. Guidance: Mr. Rajesh Kannan(Senior Lecturer, Amrita School of Engineering) Low power cache design (March 2009) Designed a low power cache model in verilog, which has achieved a 40% power reduction from the conventional design. Concept was implemented in Open SPARC T1 processor and attained a power reduction of 20%. Research paper got published in IEEE Xplore, IEEE Computer Society and Springer LNCS-CCIS. Guidance: Mr. Rajesh Kannan(Senior Lecturer, Amrita School of Engineering) Intel Embedded Challenge 2010: An Embedded design contest for students, interested individuals & entrepreneurs from all over India. ICCSIT 2009: International Conference on Computer Science and Information Technology at Beijing, China organized by IACSIT. (8th 12th of August 2009). SCORED 2008: International conference organized by IEEE at University Teknologi, Johor Bahru, Malaysia. (26th, 27th of November 2008). It was a REGION 10 (South Asia), IEEE conference where papers from only two colleges in India were selected. Undergone training in VLSI front end design and verification at the institution VEDA IIT, Hyderabad as part of the internship at WhizChip Design Technologies. Training covered Advanced Digital Design, C, C++, PERL, Verilog, System Verilog, Assertions, Formal Verification and Synthesis.

PROJECTS

CONFERENCES, WORKSHOPS & CONTESTS

INPLANT TRAINING