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A Design Perspective
Bassam Mohd Saed Abed
Implementation Strategies
Transistor/Staff Month
58%/Yr. compound Complexity growth rate
2.5m
10 1
1981 1985 1987
1989
1983
Productivity (Trans./Staff-Month)
10,000,000
Logic Transistors/Chip
100,000,000
INPUT/OUTPUT
CONTROL
(FSM: Reg+Logic)
DATAPATH (computations)
10-100
Configurable/Parameterizable
Hardwired custom
1-10
0.1-1
None
Somewhat flexible
Fully flexible
Programmability provides flexibility but comes with overhead (less efficient design)
Implementation Choices
Digital Circuit Implementation Approaches
Custom
Semicustom
Cell-based
Array-based
Macro Cells
Pre-wired (FPGA's)
Intel 4004
Cell-based design can be partitioned into number of classes: Standard cell Compiled cells Macro cells
8
Compiled Cells
The standard cell library has several disadvantages. It requires reruns every time the technology changes. It limits the designer to selected cells.
The compiled cell approach converts cell netlist drawn by designer to efficient layout.
10
Macro Cells
Macro cell is much more complex than a standard cell. Examples: memory arrays, multipliers, adders, ect. Two types: Hard macro contains the physical design of the module. The design is optimized for speed, area and power. But it is hard to port from one technology to another. Soft macro does not contain the physical design (only synthesized gates). They are easily ported from one technology to another. 11
HDL
Design Iteration
Pre-Layout Simulation
Structural
Logic Synthesis
Tape-out
12
Array-based implementation
Array-based approach generate the final product quicker and with less cost. However, it has lower integration and performance, higher power.
Array-based
Pre-wired (FPGA's)
13
Prediffused Arrays
Wafers are manufactured ahead of time. Wafers contain primitive cells. The desired interconnect (wiring) is added later by extra manufacturing steps. There are two approaches Gate array: places cells in rows separated by channels Sea of gates: gates are placed anywhere. There are no routing channels (channel-less.)
Uncommited Cell
In 1 In 2
In 3 In4
routing channel
15
NMOS
NMOS NMOS
Using oxide-isolation
Using gate-isolation
16
All the implementation (programming) is done in the field. However, the design are less efficient in the speed, power and design density. Classification of prewired arrays:
Based on Programming Technique
Fuse-based (program-once) Non-volatile EPROM (flash) based RAM based
PLA
PROM
Indicates programmable connection Indicates fixed connection
PAL
18
Programming a PROM
1 X2 X1 X0
: programmed node NA NA f 1 f 0
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From Smith97
B
0 X Y Y 0 0 1 0 0 1
S
0 1 1 X Y X X X Y 1
F=
0 X Y XY XY XY X1 Y X Y 1
A
B
0
F 1
21
Memory
Out 00 1
1 0
Interconnect Point
Programmed interconnection
Input/output pin
Cell
Horizontal
tracks
Vertical tracks
23
Connect Box
Interconnect Point
24
25
Use overlayed mesh to support longer connections Reduced fanout and reduced resistance
26