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2nd
Devices
Digital Integrated
Circuits
A Design Perspective
The Devices
Dr. Bassam Jamil
Digital Integrated Circuits
2nd
Devices
Goal of this chapter
Present intuitive understanding of CMOS
device operation
basic device equations
Introduction of models for manual analysis
SPICE simulation
Analysis of secondary and deep-sub-micron
effects
Future trends
Diodes: Self-reading
Digital Integrated Circuits
2nd
Devices
What is a Transistor?
V
GS
> V
T
R
on
S
D
A Switch!
|V
GS
|
An MOS Transistor
Digital Integrated Circuits
2nd
Devices
MOS Transistors -
Types and Symbols
D
S
G
G
S
D
D
S
G
NMOS
Enhancement
PMOS Enhancement
B
NMOS with
Bulk Contact
Digital Integrated Circuits
2nd
Devices
NMOS Device Structure
n+ n+
p-substrate
D S
G
B
V
GS
+
-
Depletion
Region
n-channel
Four Terminals
Source (S)
Drain (D)
Gate (G)
Substrate/Bulk (B)
Channel (length=L, width=W )
Terminal Voltages
V
GS
V
DS
V
SB
Digital Integrated Circuits
2nd
Devices
MOS transistor operation (1)
The principle: control the current
conduction between the source and
drain using the electric field generated
by the gate voltage as a control
variable.
The current flow depends also on the
drain-to-source voltage and substrate
voltage
Digital Integrated Circuits
2nd
Devices
MOS transistor operation (2)
V
GS
= 0
Drain and source are separated by back-
to-back reversed biased pn-junctions.
High resistance between source and drain.
0 < V
GS
< V
T
Depletion Region
Holes under the gate are repelled. No carrier
flow is observed.
Negative charge accumulate under the gate.
Depletion region is formed below the gate.
Digital Integrated Circuits
2nd
Devices
MOS transistor operation (3)
V
GS
>= V
T
Strong Inversion Region
As V
GS
increases, large number of electrons
are attracted to the surface.
The surface is inverted to n-type and
conducting channel is formed.
This occurs at twice of the fermi potential.
The value of V
GS
where the strong inversion
occurs is called V
T
.
The flow of current is influenced by V
DS
Digital Integrated Circuits
2nd
Devices
MOS transistor operation (4)
V
GS
>= V
T
The flow of source-to-drain current is
influenced by V
DS
For small V
DS
: The current is proportional
to V
DS
Linear region: voltage controlled resistor.
V
DS
= V
DSAT
As drain voltage increases, channel depth at
the drain decreases until it is pinch-off point.
Saturation region: Voltage-control current
source. The current is proportional to V
DS.
Digital Integrated Circuits
2nd
Devices
MOS transistor operation (5)
V
GS
>= V
T
V
DS
> V
DSAT
Depleted surface region forms adjacent to the
drain and grows to the source with increasing
drain voltage. The effective channel length is
reduced.
This is saturation mode.
Electrons arriving from the source towards the
drain are injected into the drain-depletion
region and are accelerated towards the drain in
the high electric field.
Digital Integrated Circuits
2nd
Devices
The Threshold Voltage
V
T
= V
T0
+ (\|-2|
F
+ V
SB
| - \|-2|
F
|)
where
V
T0
is the threshold voltage at V
SB
= 0 and is mostly a function of the
manufacturing process
Difference in work-function between gate and substrate material,
oxide thickness, Fermi voltage, charge of impurities trapped at the
surface, dosage of implanted ions, etc.
V
SB
is the source-bulk voltage
|
F
= -|
T
ln(N
A
/n
i
) is the Fermi potential
(|
T
= thermal_voltage = kT/q = 26mV at 300K is the thermal voltage; N
A
is
the acceptor ion concentration; n
i
~ 1.5x10
10
cm
-3
at 300K is the intrinsic
carrier concentration in pure silicon)
= \(2qc
si
N
A
)/C
ox
is the body-effect coefficient (impact of changes in
V
SB
) (c
si
=1.053x10
-10
F/m is the permittivity of silicon; C
ox
= c
ox
/t
ox
is the
gate oxide capacitance with c
ox
=3.5x10
-11
F/m; q=1.6x10
-19
is the electron
charge.)
11
The Body Effect: increases V
T
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
-2.5 -2 -1.5 -1 -0.5 0
V
BS
(V)
V
SB
is the substrate
bias voltage (normally
positive for n-channel
devices with the body
tied to ground)
A negative bias
causes V
T
to increase
from 0.45V to 0.85V
12
Digital Integrated Circuits
2nd
Devices
Transistor Operation
n
+
n
+
p-substrate
D
S
G
B
V
GS
x
L
V(x)
+
V
DS
I
D
MOS transistor and its bias conditions
n+ n+
S
G
V
GS
D
V
DS
> V
GS
- V
T
V
GS
- V
T
+
-
Linear Region
Saturation Region
Digital Integrated Circuits
2nd
Devices
Voltage-Current Relation: Linear Mode
For long-channel devices (L > 0.25 micron)
When V
DS
s V
GS
V
T
I
D
= k
n
W/L [(V
GS
V
T
)V
DS
V
DS
2
/2]
where
k
n
=
n
C
ox
=
n
c
ox
/t
ox
= is the process
transconductance parameter (
n
is the carrier mobility
(m
2
/Vsec))
k
n
= k
n
W/L is the gain factor of the device
For small V
DS
, there is a linear dependence between V
DS
and I
D
, hence the name resistive or linear region
14
Digital Integrated Circuits
2nd
Devices
Voltage-Current Relation: Saturation Mode
For long channel devices
When V
DS
> V
GS
V
T
I
D
= k
n
/2 W/L [(V
GS
V
T
)
2
]
since the voltage difference over the induced
channel (from the pinch-off point to the source)
remains fixed at V
GS
V
T
However, the effective length of the conductive
channel is modulated by the applied V
DS
, so
I
D
= I
D
(1 + V
DS
)
where is the channel-length modulation (varies
with the inverse of the channel length)
15
Digital Integrated Circuits
2nd
Devices
Current Determinates
For a fixed V
DS
and V
GS
(> V
T
), I
DS
is a function
of
the distance between the source and drain L
the channel width W
the threshold voltage V
T
the thickness of the SiO
2
t
ox
the dielectric of the gate insulator (SiO
2
) c
ox
the carrier mobility
for nfets:
n
= 500 cm
2
/V-sec
for pfets:
p
= 180 cm
2
/V-sec
16
Long Channel I-V Plot (NMOS)
0
1
2
3
4
5
6
0 0.5 1 1.5 2 2.5
V
DS
(V)
X 10
-4
V
GS
= 1.0V
V
GS
= 1.5V
V
GS
= 2.0V
V
GS
= 2.5V
Linear Saturation
V
DS
= V
GS
- V
T
NMOS transistor, 0.25um, L
d
= 10um, W/L = 1.5, V
DD
= 2.5V, V
T
= 0.4V
cut-off
17
Digital Integrated Circuits
2nd
Devices
A unified model for manual analysis
S
D
G
B
Digital Integrated Circuits
2nd
Devices
Simple Model versus SPICE
0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
x 10
-4
V
DS
(V)
I
D
(
A
)
Velocity
Saturated
Linear
Saturated
V
DSAT
=V
GT
V
DS
=V
DSAT
V
DS
=V
GT
Digital Integrated Circuits
2nd
Devices
The MOS Current-Source Model
V
T0
(V) (V
0.5
) V
DSAT
(V) k(A/V
2
) (V
-1
)
NMOS 0.43 0.4 0.63 115 x 10
-6
0.06
PMOS -0.4 -0.4 -1 -30 x 10
-6
-0.1
S D
G
B
I
D
I
D
= 0 for V
GS
V
T
s 0
I
D
= k W/L [(V
GS
V
T
)V
min
V
min
2
/2](1+V
DS
)
for V
GS
V
T
> 0
with V
min
= min(V
GS
V
T
, V
DS
, V
DSAT
)
and V
GT
= V
GS
- V
T
Determined by the voltages at the four terminals and
a set of five device parameters
20
The Transistor Modeled as a Switch
0
1
2
3
4
5
6
7
0.5 1 1.5 2 2.5
V
DD
(V)
x10
5
S
D
R
on
V
GS
> V
T
V
DD
(V) 1 1.5 2 2.5
NMOS(kO) 35 19 15 13
PMOS (kO) 115 55 38 31
(for V
GS
= V
DD
,
V
DS
= V
DD
V
DD
/2)
Modeled as a switch with
infinite off resistance and a
finite on resistance, R
on
Resistance inversely
proportional to W/L (doubling
W halves R
on
)
For V
DD
>>V
T
+V
DSAT
/2, R
on
independent of V
DD
Once V
DD
approaches V
T
,
R
on
increases dramatically
R
on
(for W/L = 1)
For larger devices
divide R
eq
by W/L
21
Digital Integrated Circuits
2nd
Devices
Advanced Topics
Velocity Saturation
Subthreashold conduction
Gate capacitance
22
Velocity Saturation
0
10
0 1.5 3
Electrical Field = (V/m)
For an NMOS device with L of .25m, only a couple of volts
difference between D and S are needed to reach velocity
saturation
c
=
Behavior of short channel deviates from
linear/saturation model mainly due to velocity saturation.
The velocity of the
carriers saturates due
to scattering (collisions
suffered by the
carriers)
c
= critical electrical
field = 2u
sat
/
n
5
23
Digital Integrated Circuits
2nd
Devices
Voltage-Current Relation: Velocity Saturation
For short channel devices
Linear: When V
DS
s V
GS
V
T
I
D
= k(V
DS
) k
n
W/L [(V
GS
V
T
)V
DS
V
DS
2
/2]
where
k(V) = 1/(1 + (V/
c
L)) is a measure of the degree
of velocity saturation.
c
is critical electrical field.
Saturation: When V
DS
= V
DSAT
> V
GS
V
T
I
DSat
= k(V
DSAT
) k
n
W/L [(V
GS
V
T
)V
DSAT
V
DSAT
2
/2]
24
Velocity Saturation Effects
0
10
V
DSAT
< V
GS
V
T
so
the device enters
saturation before V
DS
reaches V
GS
V
T
and
operates more often in
saturation
For short channel devices
and large enough V
GS
V
T
I
DSAT
has a linear dependence wrt V
GS
so a reduced
amount of current is delivered for a given control
voltage
25
MOS I
D
-V
GS
Characteristics
0
1
2
3
4
5
6
0 0.5 1 1.5 2 2.5
V
GS
(V)
Linear (short-channel)
versus quadratic (long-
channel) dependence of
I
D
on V
GS
in saturation
Velocity-saturation
causes the short-
channel device to
saturate at substantially
smaller values of V
DS
resulting in a substantial
drop in current drive
(for V
DS
= 2.5V, W/L = 1.5)
X 10
-4
26
Digital Integrated Circuits
2nd
Devices
I
D
versus V
GS
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
-4
V
GS
(V)
I
D
(
A
)
0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
x 10
-4
V
GS
(V)
I
D
(
A
)
quadratic
quadratic
linear
Long Channel Short Channel
Short Channel I-V Plot (PMOS)
-1
-0.8
-0.6
-0.4
-0.2
0
0 -1 -2
V
DS
(V)
X 10
-4
V
GS
= -1.0V
V
GS
= -1.5V
V
GS
= -2.0V
V
GS
= -2.5V
PMOS transistor, 0.25um, L
d
= 0.25um, W/L = 1.5, V
DD
= 2.5V, V
T
= -0.4V
All polarities of all voltages and currents are reversed
28
Digital Integrated Circuits
2nd
Devices
Sub-Threshold Conduction
0 0.5 1 1.5 2 2.5
10
-12
10
-10
10
-8
10
-6
10
-4
10
-2
V
GS
(V)
I
D
(
A
)
V
T
Linear
Exponential
Quadratic
Typical values for S:
60 .. 100 mV/decade
The Slope Factor
ox
D
nkT
qV
D
C
C
n e I I
GS
+ =1 , ~
0
S is AV
GS
for I
D2
/I
D1
=10
Digital Integrated Circuits
2nd
Devices
Dynamic Behavior of MOS Transistor
D
S
G
B
C
GD
C
GS
C
SB
C
DB
C
GB
C
G
= Gate Capacitance
C
channel
= Gate-to-Channel Cap
C
overlap
= Overlap Cap
C
G
= C
overlap
+ C
channel
C
overlap
= C
GDO
+ C
GSO
C
GSO
= C
GDO
= C
ox
x
d
W = C
o
W
C
channel
= C
GCB
+ C
GCS
+ C
GCD
C
GS
= C
GCS
+ C
GSO
C
GD
= C
GCD
+ C
GDO
C
GB
= C
GCB
C
diff
: Diffusion Capacitance
C
SB
= C
Sdiff
C
DB
= C
Ddiff
Recall: C
ox
=c
ox
/t
ox
Digital Integrated Circuits
2nd
Devices
Dynamic Behavior of MOS Transistor
Digital Integrated Circuits
2nd
Devices
The Gate Capacitance
t
ox
n
+
n
+
Cross section
L
Gate oxide
x
d
x
d
L
d
Polysilicon gate
Top view
Gate-bulk
overlap
Source
n
+
Drain
n
+
W
Digital Integrated Circuits
2nd
Devices
Gate-Channel Capacitance
S
D
G
C
GC
S
D
G
C
GC
S
D
G
C
GC
Cut-off
Resistive Saturation
Recall:
CG = C
GC
+ C
overlap
= (C
GCB
+ C
GCS
+ C
GCD
) +
2C
o
W
C
GCB
C
GCS
C
GCD
Digital Integrated Circuits
2nd
Devices
Gate Capacitance
WLC
ox
WLC
ox
2
2WLC
o
x
3
C
GC
C
GCS
V
DS
/(V
GS
-V
T
)
C
GCD
0 1
C
GC
C
GCS
= C
GCD
C
GCB
WLC
ox
WLC
ox
2
V
GS
Capacitance as a function of VGS
(with VDS = 0)
Capacitance as a function of the
degree of saturation
Digital Integrated Circuits
2nd
Devices
Diffusion Capacitance
Bottom
Side wall
Side wall
Channel
Source
N
D
Channel-stop implant
N
A
1
Substrate N
A
W
x
j
L
S
Digital Integrated Circuits
2nd
Devices
Capacitances in 0.25 m CMOS
process
Digital Integrated Circuits
2nd
Devices
The Sub-Micron MOS Transistor
Threshold Variations
Subthreshold Conduction
Parasitic Resistances
Digital Integrated Circuits
2nd
Devices
Threshold Variations (1)
L
Long-channel threshold
Threshold as a function of
the length (for low V
DS
)
V
T
For short-channel devices, part
of the channel is under the
drain is already depleted.
Hence smaller threshold is
needed for strong inversion.
Digital Integrated Circuits
2nd
Devices
Parasitic Resistances
W
L
D
Drain
Drain
contact
Polysilicon gate
D S
G
R
S
R
D
V
GS,eff
R
S,D
= (L
S,D
/W )* Resistivity + R
c
To reduce parasitic resistance:
- silicidation
- increase W
Digital Integrated Circuits
2nd
Devices
Threshold Variations (2)
V
T
Low V
DS
threshold
Drain-induced barrier lowering
(for low L )
V
DS
As Vds voltage increase,
the width of drain-junction
depletion region increases, which
decreases V
T
. This is called
drain-induced barrier lowering
(DIBL).
Punch-through: at high Vds,
the source and drain regions
can be shortened resulting in punch-
through condition.
Narrow channel: depletion region of
the channel extends under field
oxide. The gate voltage must support
this extra depletion. As a result increases
V
T
.
Digital Integrated Circuits
2nd
Devices
Hot-Carrier Effect
In short channel transistor, high electrical field
causes an increasing velocity of electrons, which
can leave silicon and tunnel into gate oxide upon
reaching a sufficiently high energy.
Electrons trapped in gate oxide alters V
T
Increases V
T
in nMOS
Decreases V
T
in PMOS
This causes V
T
in to drift over time.
Leads to long term reliability issues
Circuit might degrade or fail after sometime.
41
Digital Integrated Circuits
2nd
Devices
Subthreshold Current
Small I
D
current around V
GS
= V
T
Subthreshold current increases with
temperature.
As temperature increases, V
T
decreases
When V
T
decrease, I
D
increases.
Problems of this current
It contributes to leakage power
It discharges charged nodes
42
Digital Integrated Circuits
2nd
Devices
Sub-Threshold Conduction
0 0.5 1 1.5 2 2.5
10
-12
10
-10
10
-8
10
-6
10
-4
10
-2
V
GS
(V)
I
D
(
A
)
V
T
Linear
Exponential
Quadratic
Typical values for S:
60 .. 100 mV/decade
The Slope Factor
ox
D
nkT
qV
D
C
C
n e I I
GS
+ =1 , ~
0
S is AV
GS
for I
D2
/I
D1
=10
Digital Integrated Circuits
2nd
Devices
Sub-Threshold I
D
vs V
GS
V
DS
from 0 to 0.5V
|
|
.
|
\
|
=
kT
qV
nkT
qV
D
DS GS
e e I I 1
0
Digital Integrated Circuits
2nd
Devices
Latch-up
Results in shorting Vdd to Vss, which can results in destroying
the transistor or cause system failure.
To minimize latch-up,
Reduce R
nwell
and R
psubs
: add well and substrate contacts placed to the source
of NMOS/PMOS.
Guard rings.
Digital Integrated Circuits
2nd
Devices
Technology Scaling
Minimum size feature (e.g. L
min
)
reduced 13% per year (halving
every 5 years)
Scaling variables
Physical dimension: L, W, t
ox
, x
j
(junction
depth)
Voltages: V
DD
, V
T
Scaling factor is S >1
Depending on how to scale the
above variables, there are several
scaling methods.
Digital Integrated Circuits
2nd
Devices
Technology Scaling Methods
Full scaling: scale dimensions and voltages
(+) constant electrical field
(+) Great reduction in delay, area and power
( -) Changing voltages is not desirable from standard point of view
Fixed voltage scaling: scale dimensions, but not voltages
(+) Allows Vdd to be compatible for several process generations
( -) Suffers from power issues (e.g. high power density)
General scaling: scale dimensions by S, scale voltages by U
1 < U < S
(+) Allows voltage to scale slower than transistor dimensions.
Digital Integrated Circuits
2nd
Devices
Technology Scaling: scaling analysis
Note: S>U>1
Digital Integrated Circuits
2nd
Devices
Scaling Example
Example:
A micro controller chip manufactured using 65-nm technology. The
power supply for the chip is 1.25V. The chip runs at 1GHz and
consumes 5W.
What is the expected speed and power if the chip is manufactured
using 45-nm and the power supply voltage is scaled down to 1V.
Speed
45
= (65/45) * Speed
65
= 1.4 GHz
Power
45
= (1/1.25)
2
* Power
65
= 3.2 W
Digital Integrated Circuits
2nd
Devices
Example
Determine the required width of the transistor (for L = 0.25m) such that X equals 1.5V.
Neglect short channel effects and assume that
p
= 0.
PMOS: k'
p
= 30A/V2, VT0 = 0.4 V
Vds = -Vx
Vgs = -Vx = -1.5 transistor is ON.
And, Vds Vgs transistor is in Saturation.
I
ds
= (2.5 1.5) / 20K = 50 A
I
ds
= k'
p
(W/L) (Vgs- Vt )
2
/2
50 = 30 (W/0.25) ( -1.5 + 0.4)
2
/2
W = 0.688