Low-Noise Amplifier Design

Mohamed Abdelhalim
AbstractThis paper analyzes the designs of the low noise amplifier in the cascode ones in CMOS. These four types are classical noise matching, synchronous noise input matching, power constrained noise optimization and power constrained simultaneous noise and input matching. It will also discuss in detail their ways for decreasing noise in details and their advantages and disadvantages of every single technique. This will give a clear understanding of how to the LNA has made a progress through time and these modifications and updates will be the new trend for the future so we can get the maximum benefit from this device. Index Terms CNM, low noise amplifier, PCNIM, PCNO, SNIM

I. INTRODUCTION beginning I would like to say that there has been a great demand for the low noise amplifier in the past. This demand leads to make scientists exert a great effort in order to come up with this innovation. They also kept searching for many ways to improve or update it. The question is why did they need the low noise amplifier and what makes scientists kept searching for its modifications? This question can be simply answered that many devices especially the wireless ones were unable to differentiate between and the low power coming signal and the noise added to it which enables their addition to be amplified which results in errors in the output. Noise is present in all electronic circuits. It is produced due to the random movement of electrons in any resistive material by the random grouping of holes and electrons in a semiconductor, and when holes and electrons spread through any potential barrier. This noise can be classified into 4 types which are Thermal noise, Shot noise, Flicker noise and Burst noise. Thermal noise is generated when thermal energy causes free electrons to move randomly in a resistive material. It was discovered by Schottky on 1928 which is directly affected by the temperature, resistance and the bandwidth. Shot noise is generated when a current flows across a potential barrier which is considered a white noise. It is also affected by the electronic charge, the DC current flowing in the wires and the frequency band. Flicker noise is the imperfect contact between two conducting materials causes the conductivity to

N the

fluctuate in the presence of a dc current. Burst noise is caused by a metallic impurity in a p-n junction which can be obvious in loudspeakers since it can cause the corn popping sound. Because of these noises which can affect any device this problem can occasionally occur in the receivers. This is considered a crucial problem since the output will not be correct because of the noise added which can lead to drastic problems especially with low signal receivers. For this reason the low noise amplifier is used to solve this problem of noise it plays an important role in amplifying the low signals without any noise (distortions) or interference added. Not only this but also it helps in maintaining the required the Signal to Noise Ratio of the system with minimum power. Moreover, it is required to get high Gain, input output matching and stability at low current level. It assists in getting linearity which are considered independent on each other but all of these requirements should be met due to their equal importance however, they are not always in favor for each other. That is why tradeoffs can occur due to the various requirements and how to choose between them according to the users needs. Therefore, the understanding of the design of the low noise amplifier is an essential issue in order to be able to switch between the tradeoffs in any project. There are two types of ways to design the low noise amplifier which are the Common Gate amplifier and the Cascode amplifier. Common Gate amplifier has wide input matching however; it is not used in most applications as it is less sensitive to parasitic and it has high noise figure and lower quality in the resonant network. That is why Cascode amplifier is used in the majority of applications especially when the noise figure is vital. Thus, the main question in this paper is how to design the low noise amplifier and analyze the different ways and techniques based on the given data for noise parameters. It will also discuss the limitations that face these designs and how every technique involves many tradeoffs which differentiate between the advantages and the disadvantages between them. We will discuss also in Section II-A, summarizes the reported analytic details of the CNM technique based on the noise parameter the noise parameter ,in Section II-B the expressions for the SNIM technique, Section II-C discusses the PCNO technique and its capabilities and in

Section II-D, the PCSNIM technique which is newly launched, and the LNA design principles and what are its practical boundaries. Finally Section II is the conclusion of this paper with recommendations.

In the equation 1 defines the squared mean channel thermal noise ( ) is proportional to the drain source conductance at 0 drain source voltage and K is Boltzmann constant, T is the temperature absolute and (delta F) is the band width. In this case of zero VDS =0 this makes is unity and 2/3 in the saturation mode and the value of it increased as the increase of VGS and VDS. Due to the channel noise it leads to the occurrence of the noisy gate current which is defined as:

II. NOISE OPTIMIZATION TECHNIQUES A. CNM Technique This technique was designed in order to get the least amount of noise frequency by getting the optimum impedance to this amplifier which can be done by connecting the source to the input through a certain matching circuit. This will guarantee that the noise frequency of the transistor to be minimal. But due to the mismatch between the Impedance optimum and the input impedance complex conjugate of the amplifier it can lead to gain mismatch of the input. This can cause the occurrence of the tradeoff between the gain and the noise performance. In this fig 1)a) it is the low noise amplifier in its most popular way because of its bandwidth and high gain and to make it easier in analysis the drain-gate capacitance is neglected. While in the fig (1) (b) shows the analysis of the small signal equivalent circuit

In equation 2 , is constant= 4/3 in a long channel and it varies as channel gets short and as VGS and VDS increase and Cgs is the capacitance of the transistor between source and gate. Since the gate induced noise current has a relation with the channel noise current, coefficient relating those 2 can be defined as

Theoretically this c can be estimated as j0.395 as it resembles the capacitive coupling between the channel and gate induced current but it has to be in long channels. Therefore after many derivations to define the parameters of the noise in the cascode amplifier can be defined as:

Where Rn represents the noise resistance, Y opt is the optimum noise admittance, and Fmin is the minimum noise factor. In equation 7 the cut off frequency is equal to, and is unity for long-channel devices and decreases as channel length scales down. In equations (5), (6) and (7), the superscripted zero is adopted as a from Fig. 1(b), the input admittance is purely capacitive since Yin=jwCgs so By comparing the complex conjugate of Yin with equation (6), the optimum source admittance for input matching is different from that of the noise matching in real and imaginary parts. Thus, one cannot obtain (in example) both input matching and minimum NF

simultaneously. This is the main limitation of the CNM technique when applied to the LNA topology shown in Fig. 1(a). Therefore, there is a fundamental limitation in achieving broad-band noise matching. II. NOISE OPTIMIZATION TECHNIQUES B. SNIM Technique In this strategy we will depend on the feedback techniques in the low noise amplifier design so that we can be able to shift the Zopt to the required point Parallel or series feedback can be used but parallel is used for wide band and better I/O matching. However series feedback is preferred to obtain the SNIM without any effect in NF. These series feedback are used for narrow band functions. Fig. 2(a) and (b) shows a cascode LNA with inductive source degeneration and the simplified small-signal equivalent circuit. In Fig. 2(b), the same simplifications are applied as in Fig. 1(b).The ways to obtain the noise parameter expressions of a MOSFET with series feedback: noise transformation formula using noise parameters, using the noise matrix or Kirchoffs current law/Kirchoffs voltage law with noise current sources. In this study we assume that the inductors are lossless and to make it easier in this way we implement a matching inductor in the circuit. This makes the impedance Zs=Rs. Therefore, the noise parameters are defined as:

It can be noticeable that there is no change in Rn and Fmin. Also Zin can be defined as

This shows that there is no real part in Zin while there is in Zopt which makes Ls vital to decrease the difference in them and due to the change in imaginary part in Zin it is changed in Zopt

smaller in order to work in small dissipation power therefore the optimum transistor size can reach

The constant m for the typical device parameters of long channel MOSFET is estimated to be 0.6. With technology scaling / stays nearly constant at 2.c =0.5 with 0.25 m technology. From (13) & (14) the inductive source aids in getting the closest Zopt to the optimum source impedance. Thus

Then the minimum noise frequency in this case is defined as

Therefore to satisfy this equation and the matching Zs from eq. 9-10-11-13 it has to satisfy this:

This FminP is higher than Fmin because of the mismatch between Zs and Zopt and the increase of the value of Ls that raises the Fmin value as discussed. Fig. 3 shows the NF of a cascoded low noise amplifier with inductive deterioration as a function of power consumption and transistor size

But eq. 17 and 18 are the same from eq. 13&14 Now then, from (9)(13) the design parameters that can satisfy (16), (17), and (19) are VGS, the transistor size W and Ls. Minimum gate length is assumed to maximize the transistor cut off frequency T. . Therefore, for the given value of Zs, (16), (17) and (19) can be solved since three effective equations are provided with three unknowns. Consequently applying (10), (12) and (16) for Zs we can choose the transistor size (Cgs) to satisfies (16). Also we can adjust Ls size to satisfy eq. (17). VGS can be adjusted to make eq. 19 met. It is obvious that the transistor can meet all these equations and get the minimum noise at large transistors. The problems can really take place when it is getting smaller because it will use low frequencies to operate which means high Re [Zopt] which cant be cured by increasing Ls in order to keep Fmin not increased. Moreover, the increase of Ls will not make the Cgd will not be neglect able. Therefore SNIM cant be applied for small amount of power dissipation it has to keep Fmin and not higher than this level. II. NOISE OPTIMIZATION TECHNIQUES C. PCNO Technique With a constrained amount of power dissipation, the simultaneous gain and noise matching approach can still be useful. At any given amount of power dissipation, (18) and (19) can be satisfied by the proper selection of for the given with the help of the matching circuit shown in Fig 2 it is used to keep Fmin and on the other way it keep the transistor size

This shows that PCNO can congregate with SNIM as the transistors size decreases as its dissipation power increased. II. NOISE OPTIMIZATION TECHNIQUES D. PCSNIM Technique As we see the main problem in SNIM and PCNO is the low power dissipation at low frequencies which can be used in radios so we will implement the same model with an extra capacitor Cex.

And the noise parameters can be expressed as:

Due to this equations we have to say that by adjusting Ls this equation can be met Im[Zin] = Im[Zs]. The parameters that should be adjusted to meet the equations 28, 29&31 are VGS, W, Ls, Cex. This can guarantee the SNIM technique in any level of power dissipation. Therefore by making the assumption that Ls is not large then

This means that Ls is a function of Ct and T which are a function of VGS which can lead to another equation As it obvious here that Cex doesnt affect noise parameters Rn and Fmin. In Fig 4 we can find that

It can now be seen that the (24)(27) are similar to (9)(11) and (13). Also (24)(26) are valid for rather small values of Ls. As with the LNA topology shown in Fig. 2(a), for the SNIM of the circuit shown in Fig. 4(a), (15) now needs to be satisfied, and that means that the conditions shown in (16)(19) should be satisfied. From (25) and (27), (16)(19) can be reexpressed as follows:

So by comparing 32 and 33 then we can say that in this way as Cgs is small Ls can be reduced due to the interference of Cex. Therefore the PCSNIM technique design should identify the dc bias of VGS, decide the transistor size W which is related to power constraint and add the extra capacitor Cex to compromise between Ls and the power gain. Finally if there is any mismatch between Zs and Zin a matching impedance can be added. The limitation of the PCSIM technique is the high value of noise resistance Rn. From equation (24), the noise resistance of the proposed way is not affected by the addition of Cex, but depends only on the value of gm.

In fig (5) it shows that due to huge Rn the NF of the low noise amplifier greatly increases away from optimum point

Fig (5) III. CONCLUSION In conclusion the LNA designs can differentiate in these four techniques which are the tradeoffs that any designer should be able to fabricate any of them according to the application. The differences between those techniques can be summarized in the following table.

Although it seems that there is no problem with the PCSNIM, none of the measurements have been reported which is not the case in the other ways. In my opinion, PCSNIM will be the trend for the future analysis in order to make use of all of its advantages. This will greatly help in the noise reduction in applications. REFERENCES
[1] B. Razavi, CMOS technology characterization for analog and RF design,IEEE J. Solid-State Circuits, vol. 34, pp. 268276, Mar. 1999. [2]Trung-Kien Nguyen; Chung-Hwan Kim; Gook-Ju Ihm; MoonSu Yang; Sang-Gug Lee; , "CMOS low-noise amplifier design optimization techniques," Microwave Theory and Techniques, IEEE Transactions on , vol.52, no.5, pp. 1433- 1442, May 2004 [3] The Design of CMOS Radio Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998.