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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Design representations
Behavioral
Represents functionality but not implementation
Structural
Represents connectivity but not dimensionality
Physical
Represents dimensionality but not functionality
Introduction
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Levels of abstraction
Levels
Behavioral forms Differential eq., currentvoltage diagrams Boolean equations, finitestate machines Algorithms, flowcharts, instruction sets, generalized FSM Executable spec., programs
Structural components Transistors, resistors, capacitors Gates, flipflops Adders, comparators, registers, counters, register files, queues Processors, controllers, memories, ASICs
Physical objects
Transistor
Analog and digital cells Modules, units Microchips, ASICs PCBs, MCMs
Gate
Register
Processor
Introduction
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Design methodologies
Capture-and-simulate
Schematic capture Simulation
Describe-and-synthesize
Hardware description language Behavioral synthesis Logic synthesis
Specify-explore-rene
Executable specication Software and hardware partitioning Estimation and exploration Specication renement
Introduction
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Motivation
Executable specification System implementation
Processor
Memory
if (x = 0) then y=a*b/2
Video accelerator
ASIC
I/O
Models Languages
Introduction
5 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Outline
Introduction Design models and architectures System-design languages An example Translation Partitioning Estimation Renement Methodology and environments
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
Outline
6 of 214
UC Irvine
Specification + Constraints
Design process
Implementation
Architectures (Implementation)
Models are conceptual views of the systems functionality Architectures are abstract views of the systems implementation
7 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Model: a set of functional objects and rules for composing these objects Architecture: a set of implementation components and their connections
8 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
loop if (req_floor = curr_floor) then direction := idle; elsif (req_floor < curr_floor) then direction := down; elsif (req_floor > curr_floor) then direction := up; end if; end loop; (b) Algorithmic model
Down
Idle
Up
(req_floor < curr_floor) / direction := up (req_floor < curr_floor) / direction := down (c) Statemachine model
9 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Combinational logic
Processor Bus
Memory
10 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Models
State-oriented models
Finite-state machine (FSM), Petri net, Hierarchical concurrent FSM
Activity-oriented models
Dataow graph, Flowchart
Structure-oriented models
Block diagram, RT netlist, Gate netlist
Data-oriented models
Entity-relationship diagram, Jacksons diagram
Heterogeneous models
Control/dataow graph, Structure chart, Programming language paradigm, Object-oriented paradigm, Program-state machine, Queueing model
11 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
r2/n S2
r3 /u2
r1/ d2
S3 r3/n S = { s1, s2, s3} I = {r1, r2, r3} O = {d2, d1, n, u1, u2} f: S x I > S h: S x I > O
12 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
r3/
UC Irvine
r1 r1 r1
r3
start
S11/d2
r2 r1 r1
S21/d1
r2 r2 r3 r3
r2 r2
S31 /n
r3
S /d1 12
r1 r2 r1
r1
S22 /n
S32 /u1
r3
r2
r3
r2
S /n 13
r1
r2
S23 /u1
r3 r3 r3
S33 /u2
13 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
start
S 1
(curr_floor = req_floor) / output := 0
14 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Finite-state machines
Merits:
represent systems temporal behavior explicitly suitable for control-dominated system
Demerits:
lack of hierarchy and concurrency resulting in state or arc explosion when representing complex systems
15 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
p2 t4
p1
t1
p5
t2
p4
p3 Net = (P, T, I, O, u) P = {p1, p2, p3, p4, p5} T = {t1, t2, t3, t4} I: I(t1) = {p1} I(t2) = {p2,p3,p5} I(t3) = {p3} I(t4) = {p4} O: O(t1) = {p5} O(t2) = {p3,p5} O(t3) = {p4} O(t4) = {p2,p3}
t3
16 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Petri nets
t1
t2
t1
t2
t1
(a) Sequence
(b) Branch
(c) Synchronization
t1
t2
t1
t2
t3
t4
(e) Concurrency
17 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Petri nets
Merits:
good at modeling and analyzing concurrent systems
Demerits:
at model that is incomprehensible when system complexity increases
18 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Y A D
E u
a(P)/c b
r F s a G
19 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Merits:
support both hierarchy and concurrency good for representing complex systems
Demerits:
concentrate only on modeling control aspects and not data and activities
20 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
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A2.1
A2.2
Input X
A2.3
Output Y
V File
21 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Dataow graphs
Merits:
support hierarchy suitable for specifying complex transformational systems represent problem-inherent data dependencies
Demerits:
do not express temporal behaviors or control sequencing weak for modeling embedded systems
22 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
start
J=1 MAX = 0 J = J+1 No J>N Yes No MEM(J) > MAX Yes MAX = MEM(J)
end
23 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Flowcharts
Merits:
useful to represent tasks governed by control ow can impose a order to supersede natural data dependencies
Characteristics:
used only when the systems computation is well known
24 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Right bus
Register file
Processor
I/O coprocessor
ALU
(b) RT netlist
25 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Component-connectivity diagrams
Merits:
good at representing systems structure
Characteristics:
often used in the later phases of design process
26 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Availability
Supplier
P.O. instance
Product
Customer
Request
Order
27 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Entity-relationship diagrams
Merits:
provide a good view of the data in the system, also suitable for expressing complex relations among various kinds of data
Demerits:
do not describe any functional or temporal behavior of the system.
28 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Circle
Rectangle AND
Radius
Width
Height
29 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Jacksons diagrams
Merits:
suitable for representing data having a complex composite structure.
Demerits:
do not describe any functional or temporal behavior of the system.
30 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
+
Control flow graph
Write A
start
X
1
C 2
Const 3 E
Read X
S 0
start / enable A1 , enable A2
A1
+
X := X + 2 A := X + 5 A := X + 3 A := X + W Write A
disable S 1
W = 10 / disable A1 , enable A3
enable
A2
Z
Read X
Const 2
+
disable enable A3
Const 5
S 2 Control
+
Write X Write A
31 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Control/dataow graphs
Merits:
correct the inability of DFG in representing the control of a system correct the inability of CFG to represent data dependencies
32 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
control Data
A,B A,B
Main
C A,B A,B C,D
Get
Branch
Transform
A B
Compute
Out_C
B A B
Get_A
Get_B
Change_A
Change_B
Do_Loop1
Do_Loop2
Iteration
33 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Structure charts
Merits:
represent both data and control
Characteristics:
used in the preliminary stages of program design
34 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
35 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Programming languages
Merits:
model data, activity, and control
Demerits:
do not explicitly model the systems states
36 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Transformation function
37 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Object-oriented paradigms
Merits:
support information hiding, inheritance, natural concurrency
Demerits:
not suitable for systems with complicated transformation functions
38 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Y A
D variable i, max: integer ; B max = 0; for i = 1 to 20 do if ( A[i] > max ) then max = A[i] ; end if; end for
e1
e2
e3
39 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Program-state machines
Merits:
represent systems states, data, control and activities in a single model overcome the limitations of programming languages and HCFSM models
40 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Arriving requests
Queue Server
Arriving requests
41 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Queueing model
Characteristics:
used for analyzing systems performance, and can nd utilization, queueing length, throughput
42 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Architectures
Application-specic architectures
Controller architecture, Datapath architecture, Finite-state machine with datapath (FSMD).
General-purpose processors
Complex instruction set computer (CISC) Reduced instruction set computer (RISC) Vector machine Very long instruction word computer (VLIW)
Parallel processors
43 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Controller architecture
State register
Nextstate function
Output function
Outputs
Inputs
44 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Datapath architecture
x(i) b(0) x(i1) b(1) x(i2) b(2) x(i3) b(3)
* +
* +
Pipeline stages
+
y(i) (a) Three stage pipeline
x(i) b(0)
x(i1) b(1)
x(i2) b(2)
x(i3) b(3)
* +
* +
* +
y(i)
45 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
FSMD
Datapath inputs
State register
Nextstate function
Output function
Control
Datapath
Datapath outputs
46 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
CISC architecture
Control
Microprogram memory
Datapath PC
47 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
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RISC architecture
Control
ALU
State register
Status
Data cache
Instr. cache
Memory
48 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Vector machines
Interleaved memory
Memory pipes
Memory pipes
Vector registers
Scalar registers
49 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
VLIW architecture
Memory
Register file
50 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
PE 1 Proc. 1
PE N1 Proc. N1
Mem. 0
Mem. 1
Mem. N1
Proc. 0
Proc. 1
Proc. N1
Interconnection network
Mem. 0
Mem. N1
51 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Conclusion
Different models focus on different aspects Proper model needs to represent systems features Models are implemented in architectures Smooth transformation of models to architectures increases productivity
52 of 214 Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
System specication
For every design, there exists a conceptual view Conceptual view depends on application
Computation : conceptualized as a program Controller : conceptualized as a state-machine
Ideal language
1-to-1 mapping between conceptual model & language constructs
53 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Outline
Requirements for embedded system specication Evaluate HDLs with respect to embedded systems
VHDL, Verilog, Esterel, CSP, Statecharts, SDL, SpecCharts
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Concurrency
System often conceptualized as set of concurrent behaviors Concurrency can exist at different abstraction levels:
Job-level Task-level Statement-level Operation-level Bit-level
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Data-driven concurrency
Operations execute when input data is available Execution order determined by data dependencies
add 1: Q = A + B 2: Y = X + P 3: P = (C D) * Q
subtract
multiply
add Q P Y
UC Irvine
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
Control-driven concurrency
Control thread : set of operations executed sequentially Concurrency represented by multiple control threads
Q
Fork-join statement
sequential behavior X begin Q(); fork A(); B(); C(); join; R(); end behavior X;
concurrent behavior X begin process A(); process B(); process C(); end behavior X;
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
State-transitions
start
finish
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Hierarchy
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Structural hierarchy
System represented as set of interconnected components Interconnections between components represent wires Several levels: systems, chips, RT-components, gates
System Processor
Control Logic Datapath data bus
Memory
control lines
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Behavioral hierarchy
Concurrent decomposition
Fork-join Process
R
R1 e8
Sequential decomposition
Procedure State-machine
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Programming constructs
Some behaviors easily conceptualized as sequential algorithms Wide variety of constructs available
Assignment, branching, iteration, subprograms, recursion, complex data types (records, lists)
type buffer_type is array (1 to 10) of integer; variable buf : buffer_type; variable i, j : integer; for i = 1 to 10 for j = i to i if (buf(i) > buf(j)) then SWAP(buf(i), buf(j)); end if; end for; end for;
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Behavioral completion
Y Y1
e3
start
X3 X2
e2 e4
Y2
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Communication
shared memory
Message-passing model
Data sent over abstract channels Unidirectional / bidirectional Point-to-point / multiway Blocking / non-blocking
process P
begin variable x .... send (x); .... end
process Q
begin variable y .... receive (y); .... end
channel C
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Synchronization
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Control-dependent synchronization
Fork-join
behavior X begin Q(); fork A(); B(); C(); join; R(); end behavior X;
C
synchronization point
Reset
A
ABC B C
AB A A1 A2 B B1 B2
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Data-dependent synchronization
AB B B1
e
A B A1
B B1
(x=1)
A A1
e
B1
entered A2
x:=0 e
A2
B2
A2
B2
A2
x:=1
B2
System specication
67 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Exception handling
Occurrence of event terminates current computation Control transferred to appropriate next mode Example of exceptions: interrupts, resets
P
P1 P2
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Timing
Required to represent real world implementations Functional timing: affects simulation of system specication
wait for 200 ns; A <= A + 1 after 100 ns;
OUT time
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
P
v
Q
w
R
join
System specication
70 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
VHDL
IEEE standard, intended for documentation and exchange of designs [IEE88] Characteristics supported
Behavioral hierarchy : single level of processes Structural hierarchy : nested blocks and component instantiations Concurrency : task-level (process), statement-level (signal assignment) Programming constructs Communication : shared-memory using global signals Synchronization : wait on and wait until statements Timing : wait for statement, after clause in assignments
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Verilog [TM91] developed as proprietary language for specication, simulation Esterel [Hal93] developed for specication of reactive systems Characteristics supported:
Behavioral hierarchy : fork-join Structural hierarchy : hierarchy of interconnected modules Programming constructs Communication : shared registers (Verilog) and broadcasting (Esterel) Synchronization : wait for an event on a signal Timing : modeling of gate, net, assignment delays in Verilog Exceptions : disable (Verilog), watching, do-upto, trap statements (Esterel)
System specication
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UC Irvine
channel
channel
block channel
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
SpecCharts
Developed for embedded system specication [NVG92] PSM (program-state machine) model + VHDL Characteristics supported
Behavioral hierarchy : sequential/concurrent behaviors State transitions: TOC (transition on completion) arcs Communication : shared memory, message passing Exceptions : TI (transition immediately) arcs
port P, Q : in integer;
B
type INTARRAY is array (natural range <>) of integer; signal A : INTARRY (15 downto 0);
Y
X1 variable MAX : integer ; MAX := 0; for J in 0 to 15 loop if ( A(J) > MAX ) then max := A(J) ; end if; end loop
e1 X2
e2
e3
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
start
u v w
behavior MAIN type sequential subbehaviors is begin P : (TOC, u, Q) ; Q : (TOC, v, P), (TOC, w, R); R : (TOC, x, Q); behavior P ..... behavior Q ..... behavior R ..... end MAIN;
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
P
fork behavior P ..... .....
behavior MAIN type sequential subbehaviors is begin P : (TOC, true, Q_R); Q_R : (TOC, true, S); S:;
Q
join
behavior Q_R type concurrent subbehavior is begin Q : (TOC, true, halt); R : (TOC, true, halt); behavior Q ..... behavior R ..... end Q_R; behavior S..... end MAIN;
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
SpecCharts : exceptions
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Summary
Embedded System Features Language
State Transitions Behavioral Hierarchy Concurrency Program Constructs Exceptions Behavioral Completion
System specication
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Specication example
80 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Outline
Point out the benets of a good language/model match Highlight experiments that demonstrate those benets
Specication example
81 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Announcement unit
Tape unit
Line circuitry
ann_done
tape_play
tape_rew
tape_fwd
ann_play
tape_rec
tape_cnt
ann_rec
hangup
offhook
tollsaver power
beep
tone
ring
messages
rec ann Controller hear ann on/off memo play msgs mic stop rew play fwd light
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
SystemOn
phone line Announcement unit Tape unit Line circuitry
ann_done
tape_play
tape_rew
ann_play
tape_fwd
tape_rec
tape_cnt
ann_rec
hangup
offhook
tollsaver power
beep
tone
ring
messages
rec ann Controller hear ann on/off memo play msgs mic stop rew play fwd light
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
SystemOn
System usually responds to the line Pressing any machine button gets immediate response
phone line Tape unit Line circuitry
Announcement unit
ann_done
tape_play
tape_rew
ann_play
tape_fwd
tape_rec
tape_cnt
ann_rec
hangup
offhook
tollsaver power
beep
tone
ring
messages
rec ann Controller hear ann on/off memo play msgs mic stop rew play fwd light
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
RespondToMachineButton behavior RespondToMachineButton type code is begin if (play=1) then HandlePlay; elsif (fwd=1) then HandleFwd; elsif (rew=1) then HandleRew; elsif (memo=1) then HandleMemo; elsif (stop=1) then HandleStop; elsif (hear_ann=1) then HandleHearAnn; elsif (rec_ann=1) then HandleRecAnn; elsif (play_msgs=1) then HandlePlayMsgs; end if; end;
messages
HandlePlay play=1 HandleFwd fwd=1 HandleRew rew=1 HandleMemo memo=1 HandleStop stop=1 HandleHearAnn hear_ann=1 HandleRecAnn rec_ann=1 HandlePlayMsgs play_msgs=1
phone line
Announcement unit
Tape unit
Line circuitry
ann_done
tape_play
tape_rew
ann_play
tape_fwd
tape_rec
tape_cnt
ann_rec
hangup
offhook
tollsaver power
rec ann Controller hear ann on/off memo play msgs mic stop rew play fwd light
beep
tone
ring
(a)
(b)
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Responds to exceptions
Hangup Machine turned off
phone line Announcement unit Tape unit Line circuitry
ann_done
tape_play
tape_rew
ann_play
tape_fwd
tape_rec
tape_cnt
ann_rec
hangup
offhook
tollsaver power
beep
tone
ring
messages
rec ann Controller hear ann on/off memo play msgs mic stop rew play fwd light
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
MaintainRingsToWait loop rings_to_wait <= DetermineRingsToWait; wait on tollsaver, machine_on; end loop;
Announcement unit
CountRings variable I : integer range 0 to 20; i := 0; while (i < rings_to_wait) loop wait on rings_to_wait, ring; if (rising(ring)) then i := i + 1; end if; end loop;
ann_done
tape_play
tape_rew
ann_play
tape_fwd
tape_rec
tape_cnt
ann_rec
hangup
offhook
tollsaver power
beep
tone
ring
messages
rec ann Controller hear ann on/off memo play msgs mic stop rew play fwd light
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
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Answer rising(hangup) PlayAnnouncement button="0001" RecordMsg button="0001" RemoteOperation (a) behavior RecordMsg type code is begin ProduceBeep(1 s); if (hangup = 0) then tape_rec <= 1; wait until hangup=1 for 100 s; ProduceBeep(1 s); num_msgs <= num_msgs + 1; tape_rec <= 0; end if; end; (c) Hangup
behavior PlayAnnouncement type code is begin ann_play <= 1; wait until ann_done = 1; ann_play <= 0; end;
(b)
phone line Announcement unit Tape unit Line circuitry
ann_done
tape_play
tape_rew
ann_play
tape_fwd
tape_rec
tape_cnt
ann_rec
hangup
offhook
tollsaver power
beep
tone
ring
messages
rec ann Controller hear ann on/off memo play msgs mic stop rew play fwd light
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Owner can operate machine remotely by phone Owner identies himself by four button ID
hangup=1 behavior CheckUserCode type code is begin code_ok <= true; for (i in 1 to 4) loop wait until tone /= "1111" and toneevent; if (tone /= user_code(i)) then code_ok <= false; end if; end loop; end; (b)
RespondToCmds (a)
phone line Announcement unit Tape unit Line circuitry
ann_done
tape_play
tape_rew
ann_play
tape_fwd
tape_rec
tape_cnt
ann_rec
hangup
offhook
tollsaver power
beep
tone
ring
messages
rec ann Controller hear ann on/off memo play msgs mic stop rew play fwd light
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
phone line
SystemOn
power=1
power=0
Announcement unit
InitializeSystem
RespondToMachineButton
Tape unit
Line circuitry
rising(any_button_pushed)
ann_done
tape_play
tape_rew
ann_play
tape_fwd
RespondToLine
tape_cnt hangup offhook beep tone ring
tape_rec
ann_rec
Monitor
rising(hangup)
falling(machine_on)
tollsaver power
messages
Answer
rising(hangup)
PlayAnnouncement
tone="0001"
RecordMsg
Hangup
rec ann Controller hear ann on/off memo play msgs mic stop rew play fwd light
RemoteOperation
hangup=1
CheckUserCode
code_ok not code_ok
RespondToCmds
tone="0010"
HearMsgsCmds
hangup=1
MiscCmds
other
ResetTape
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Precision
Readability/precision compete in a natural language Executable specication encourages precision Designer asks questions, specication answers them
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
VHDL modelers required 2.5 times longer Two VHDL specications possessed control errors SpecCharts were effective for state-transitions and exceptions
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Statecharts 80 135 0 X
Programstates Arcs Control signals Lines/leaf Lines Words No sequential program constructs No hierarchy
42 40
X X
X X X
Shortcomings
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Design attribute Control transistors Datapath transistors Total transistors Total pins
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Summary
Executable languages encourage precision and automation The language should support an appropriate model
Makes specication easy
Specication example
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Translation
Model often unsupported by a standard language (1) Use a standard language anyway
Many tools available But, captures model unnaturally
96 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Outline
Front-end language in VHDL environment State machine translation Fork-join translation Exception translation
Translation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
VHDL
SpecCharts
Translator
VHDL
Tool output
Translation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
type state_type is (P, Q, R); variable state : state_type := P; start loop case (state) is when P => <actions for P> if (u) then state := Q; else if (not u) then state := R; end if; when Q => <actions for Q> state := P; when R => <actions for R> state := Q; end case; end loop; (b)
not u
(a)
Translation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Fork-join translation
signal fork, P1_done, P2_done : boolean; Main: process begin statement1; parallel { P1; P2; } statement2; ... (a) Main : process begin statement1; fork <= true; wait until P1_done and P2_done; statement2; ... (b) P1_process : process begin wait until fork; P1; P1_done <= true; wait until not fork; P1_done <= false; end;
Translation
100 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Exception translation
T statement1; if (e) goto S_start; statement2; if (e) goto S_start; statement3; S_start: S statement4; statement5; (b)
T T_loop : loop statement; if (e) exit T_loop; statement2; if (e) exit T_loop; statement3; exit T_loop; end loop; S statement4; statement5; (c)
Translation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Summary
The perfect standard language may never exist No standard language supports all models Using a front-end language solves the problem
Natural capture Large base of tools and expertise
Translation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
System partitioning
Constraints
Cost, performance, size, power
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Outline
Structural vs. functional partitioning Natural vs. executable language specications Basic partitioning issues and algorithms Functional partitioning techniques for hardware Hardware/software partitioning Functional partitioning techniques for software Exploring tradeoffs with functional partitioning
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Structural: Implement structure, then partition Functional: Partition function, then implement
Enables better size/performance tradeoffs Uses fewer objects, better for algorithms/humans Permits hardware/software solutions But, its harder than graph partitioning
System partitioning
105 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Alternative methods for specifying functionality Natural languages common in practice Executable languages becoming popular
Automated estimation/partitioning explores solutions Early verication reduces costly late changes Precision eases integration
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Granularity Metrics and estimations Partitioning algorithms Objective and closeness functions Systemcomponent allocation
Output
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
A Cost B
Number of moves
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
User interface
Input Model
Output
Algorithms
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Clustering and multi-stage clustering [Joh67, LT91] Group migration (a.k.a. min-cut or Kernighan/Lin) [KL70, FM82] Ratio cut [KC91] Simulated annealing [KGV83] Genetic evolution Integer linear programming
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Hierarchical clustering
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
end loop /* Compute closenesses between objects */ for each loop for each loop ComputeCloseness( ) end loop end loop
for each
return
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
o
30
1 10
25
o1
20
o1 o3 o2
10
o o3 o2
o2
10
15
o3
10
o2
10 10
o3 o4
o4
o4
o4
Avg(10,10) = 10 Avg(15,25) = 20
o1 o2 o3 o4 (a)
o1 o2 o3 o4 (b)
o1 o2 o3 o4 (c)
o1 o2 o3 o4 (d)
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Simulated annealing
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
initial temperature Objfct( ) while not Frozen loop while not Equilibrium loop Move( ) Objfct(
if (Accept(
)
"
$%&
'
where:
() '
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
"
UC Irvine
Goal: incorporate area/time into synthesis [MK90] Clusters CDFG operations into datapath modules Closeness metrics:
Interconnecting wires Concurrency Shared hardware
System partitioning
118 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
BUD example
start
(bitwidths = 4)
+ =
x cond x := a + b; if (a = b) c := ((x y) < z); 0 x 1 y z cond
38 .
+
0
.2
.7
<
4
<
c
System partitioning
119 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
.2
UC Irvine
+
.2
+
AVG(.19,.12) =
=
g( 0, .2 4)
g(
+=<
.1
Av
<
.035
=<
<
(a)
<
<
Chip area A Expected cycle time T 17.5 15.8 13.8 16.4 (b) 36 26 26 26
Chip
+
Controller
<
(c)
=
3 clusters
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Closeness metrics:
Control transfer reduction Data transfer reduction Hardware sharing
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Aparty example
o1 o 12 o2 o4 o3
23 21 17
o 12 o3 o4 o3
o4
o1 o2 o3 o4 (a) (b)
o 12
o3 o4 (c)
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Hardware/software partitioning
Combined hardware/software systems are common Software is cheap, modiable, and quick to design Hardware is fast Special algorithms are needed to favor software Proposed algorithms
Greedy [GD92] Hill climbing [EHB94] Binary-constraint search with hill climbing [VGG93]
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Vulcan [GD90]I
Partitions CDFG operations among hardware only Group migration and simulated annealing algorithms
Vulcan II [GD93]
Partitions operations among hardware/software Architecture: processor, hardware, memory, bus All communication through memory Uses greedy algorithm, extracts behaviors from hardware
Cosyma [EHB94]
Partitions statement blocks among hardware/software Architecture: processor, hardware, memory, bus Simulated annealing, extracts behaviors from software
System partitioning
124 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Uses fast incremental-update estimators Covers both hardware and hardware/software partitioning [GVN94, VG92]
System partitioning
125 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
performance (microseconds)
Each line represents a different vendors chip set Each point represents an allocation and partition Many designs quickly examined
800.0
600.0
400.0 C A 200.0 0.0 20.0 40.0 B 60.0 80.0 100.0 cost (dollars) 120.0 140.0
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Summary
Partitioning heavily inuences design quality Functional partitioning is necessary Executable specication enables:
Automation Exploration Documentation
System partitioning
127 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Future directions
Metrics from real design to guide partitioning Comparison of functional partitioning algorithms Impact of metric selections and orderings Impact of of granularity on partition quality Exploitation of regularity in partitioning
System partitioning
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Estimation
Estimates allow
Evaluation of design quality Design space exploration
Design model
Represents degree of design detail computed Simple vs. complex models
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Outline
Estimation
130 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Estimation Error
Computation Time
Simple Model
Actual Design
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
Estimation
131 of 214
UC Irvine
Fidelity
Estimates must predict quality metrics for different design alternatives Fidelity: % of correct predictions for pairs of design implementations Higher delity correct decisions based on estimates
E(A) > E(B), M(A) < M(B) E(B) < E(C), M(B) > M(C) E(A) < E(C), M(A) < M(C)
Estimation
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UC Irvine
Quality metrics
Performance Metrics
Clock cycle, control steps, execution time, communication rates
Cost Metrics
Hardware: manufacturing cost (area), packaging cost(pin) Software: program size, data memory size
Other metrics
Power, testability, design time, time to market
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Memory p 1
DR
AR
Control Logic
n2
Control Register
R1 RF
n
Muxes
R2
n 1
State Reg.
n6
p 3
Muxes
n 4
NextState Logic
n 5
p 2
Functional Units
Control Unit
Datapath
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
x
80
80
+
80
x
80
+
150
80
x
80
+
80
+
80
+
150
+ +
80 80 80
150
x
o1
+
150
+ +
o2 o2 o1
x
o1
o2
: 380 ns : 380 ns : 2 x, 4 +
: 150 ns : 600 ns : 1 x, 1 +
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Clock utilization
1 x CLK
2 x CLK
3 x CLK
100 Slack
150 Clock = 65 ns
time (ns)
6x32
x
ave_slack(65 ns) = 6 +
2x9
2 x 17
+
2
+
+
+
2
= 24.4 ns
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
for
loop
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
140.0 120.0
1000.0
100.0 80.0 60.0 40.0 20.0 0.0 0.0 20.0 40.0 60.0 Utilization (%) 80.0
92% 56 ns
800.0
600.0
560 ns 92%
400.0 0.0
20.0
80.0
100.0
100.0
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Operations in the specication assigned to control step Number of control steps determines:
Execution time of design Complexity of control unit
Scheduling
Granularity is operations in a dataow graph Computationally expensive
Estimation
140 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Operator-use method
num(t i ) clocks(t i ) 1 2 1 1 4 1
u2 := 5 x w u3 := 3 x y y1 := i x dx w := w + dx
u1 := u x dx u2 := 5 x w n u3 := 3 x y 1 y1 := i x dx w := w + dx
u1 := u x dx ; u2 := 5 x w ; u3 := 3 x y ; y1 := i x dx ; w := w + dx ; u4 := u1 x u2 ; u5 := dx x u3 ; y := y + y1 ; u6 := u u4 ; u := u6 u5 ;
n u4 := u1 x u2 u5 := dx x u3 y := y + y1 u6 := u u4 u := u6 u5 n n
u4 := u1 x u2 2 u5 := dx x u3 y := y + y1
add: (1/1)*1= 1 mult: (2/2)*4= 4 max (1 , 4) = 4 sub: (1/1)*1= 1 max (1 ) = 1 sub: (1/1)*1= 1 max (1 ) = 1 Estimated total control steps = 14
3 u6 := u u4 4 u := u6 u5
Estimation
141 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Branching in behaviors
B 2 o3 o4 o5 B 4
B 3 o6 o7
s4 s5
o4 o5 o8 (b)
o7
s4 s5 s8
o4 o5 o8 (c)
o8 (a)
s6
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Probability-based ow analysis
B1
A := A + 1;
V 1
e 12
V
0.5
2
0.5
e 24
D>A
3
D := D + 2;
4
V3
23
V 4
e 45 e 52
e 35
5 E := D * 2 ;
(I =< 10) (I > 10) B: = B * A; C := 3;
V 5
e 56
0.9 0.1
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Probability-based ow analysis
Flow equations:
10 10 10 05 05 10 01
09
10
10 50 10 0
10 0 50 10
Estimation
145 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Communication rates
bits sent over channel C
200
400
600
800
1000
time (ns)
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Estimation
147 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Area estimation
Two tasks:
Determining number and type of components required Estimating component size for a specic technology (FSMD, gate arrays etc.)
We will discuss
Datapath component estimation Control unit estimation Layout area for a custom implementation
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Clique-partitioning
Let
be a graph,
and
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Clique-partitioning
Edge e s s 1 v
1 1,3 1,4 2,3 2,5 3,4 4,5
Common neighbors 1 1 0 0 1 0 v3 s 4 s 13 v
1
2 v2
Edge e e e
13,4 2,5 4,5
Common neighbors 0 0 0
2 v2
e e e s 5
v3 s 3 s 4
v4
e e
v4
s v
1
2 v2
Edge e
2,5
Common neighbors 0 v3 s
v2
25
v4
v3 s 134
134 s Cliques:
v4
134 s 25
= =
{v1 , v 3 , v 4 } {v2 , v 5 }
Estimation
150 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Storage-unit estimation
Variables not used concurrently maybe mapped same storage-unit To use clique-partitioning, construct a graph where
Each variable represented by a vertex Variables with non-overlapping lifetimes have an edge between] their vertices
v1 v2 v 3 v4 v5 v6 v7 v8 v9 v10 v11 s s v v10 v1 v9 s
2 8 0
Storage unit = = = = = R
1
R2 R
3
v11 s
3
v3
v5
R4 R5
v4
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Clique-partitioning can be applied For determining the number of FUs required, construct a graph where
Each operation in behavior represented by a vertex Edge connects two vertices if Corresponding operations assigned different control steps There exists an FU that can implement both operations
Estimation
152 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Bit-sliced datapath
bit
Control lines
H cell H bit
rt Datapath components
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Pin estimation
channel ch1
channel ch2
Estimation
154 of 214
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
8086 instructions
68000 instructions
MIPS instructions
Generic instructions
MIPS instruction timing & size information
8086 Estimator
68000 Estimator
MIPS Estimator
Estimator
Software Metrics
Software Metrics
Generic model
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
8086 instructions
instruction mov ax, word ptr[bp+offset1] add ax, word ptr[bp+offset2] mov word ptr[bp+offset3], ax clocks
(10) (9 + EA1) (10)
68020 instructions
bytes
3 4 3
instruction
mov a6@(offset1), d0 add a6@(offset2), d0 mov d0, a6@(offset3)
clocks
(7) (2 + EA2) (5)
bytes
2 2 2
execution time
execution time
size
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Software estimation
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Future directions:
Incorporating synthesis/compilation optimizations New metrics for testability, power, integration cost, etc. New architectural features for the estimation model
Estimation
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Renement
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UC Irvine
Outline
Rening variable groups Channel renement Resolving access conicts Rening incompatible interfaces
Renement
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UC Irvine
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UC Irvine
Variable folding
variable variable variable variable A: B: C: D: bit_vector( 3 downto 0) ; bit_vector(15 downto 0) ; bit_vector(11 downto 0) ; bit_vector(11 downto 0) ;
11 8 7 0
A( 3 downto 0) B( 7 downto 0) B(15 downto 8) C( 7 downto 0) C(11 downto 8) D( 5 downto 0) D(11 downto 6)
... ... 11
to variable C in memory
6x1
5..0
8bit Memory
to variable D in memory
Renement
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V (63 downto 0)
Assigning addresses to V
variable J, K : integer := 0; variable MEM : IntArray (255 downto 0); .... MEM(K +100) := 3; X := MEM(136); MEM(J+100) := X; .... for J in 0 to 63 loop SUM := SUM + MEM(J +100); end loop; .... Refined specification
variable J : integer := 100; variable K : integer := 0; variable MEM : IntArray (255 downto 0); .... MEM(K + 100) := 3; X := MEM(136); MEM(J) := X; .... for J in 100 to 163 loop SUM := SUM + MEM(J); end loop; .... Refined specification without offsets for index J
Renement
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UC Irvine
Channels are virtual entities over which messages are transferred Bus is a physical medium that implements groups of channels Bus consists of:
wires representing data and control lines protocol dening sequence of assignments to data and control lines
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UC Irvine
: number of bits in each message : number of times transfers data over : rate of data transfer of over lifetime of behavior : rate of transfer of single message
channel X
t=0
8 X3 400
X1
time (ns)
8 bits
24 400 8 100
60 80
Renement
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Characterizing buses
: number of data lines in : delay for single message transfer over bus : rate of data transfer over over lifetime of system : maximum rate of transfer of data on bus
Renement
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UC Irvine
Idle slots of a channel used for messages of other channels To ensure that channel average rates are unaffected by bus
Average rate
8 8 X2 16 Y2 16 Y3
channel X
X1 16
channel Y
8
Y1
16 Y1
16 Y2
8 X2
16 Y3
bus B
t=0
X1
(4 + 12 bits/s) = 16 bits/s
4s
1s
2s
3s
time
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UC Irvine
Buswidth: affects number of pins on chip boundaries Channel average rates: affects execution time of behaviors Channel peak rates: affects time required for single message transfer
16 16 X2
channel X
X1
averate(X) = 8 bits/s
8 X1
8 X2
bus B
16
16 X2
bus B
t=0
X1
1s
time
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UC Irvine
loop
end loop if ( ) then /* feasible solution, determine minimal cost */ ComputeCost( ) if ( ) then , end if end if end loop return( )
Renement
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UC Irvine
For
if
Renement
if
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then
1,
loop
then
Max
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
2 behavior accessing 16 bit data over two channels Constraints specied for channel peak rates
9000.0 8000.0 7000.0 6000.0 5000.0 4000.0 3000.0 2000.0 1000.0 0.0 -1000.0 0.0
selected buswidth
4.0
8.0
20.0
24.0
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UC Irvine
7000.0 6000.0 5000.0 4000.0 3000.0 2000.0 1000.0 0.0 0.0 4.0 8.0 12.0 16.0 Buswidth (pins) 20.0 24.0
Renement
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UC Irvine
Protocol generation
All channels mapped to bus share these lines Number of data lines determined by bus generation algorithm Protocol generation consists of six steps
Renement
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UC Irvine
Protocol generation
1. Protocol selection: full handshake, half-handshake etc. 2. ID assignment: channels require ID lines 2
behavior P variable AD; begin ..... X <= 32 ; ..... MEM(AD) := X + 7; ..... end ; behavior Q variable COUNT; begin ..... MEM(60) := COUNT ; ..... end ;
CH0 CH1
"00" "00"
variable X : bit_vector(15 downto 0) ;
CH2 CH3
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UC Irvine
Protocol generation
type HandShakeBus is record START, DONE : bit ; ID : bit_vector(1 downto 0) ; DATA : bit_vector(7 downto 0) ; end record ; signal B : HandShakeBus ;
procedure ReceiveCH0( rxdata : out bit_vector) is begin for J in 1 to 2 loop wait until (B.START = 1) and (B.ID = "00") ; rxdata (8*J1 downto 8*(J1)) <= B.DATA ; B.DONE <= 1 ; wait until (B.START = 0) ; B.DONE <= 0 ; end loop; end ReceiveCH0; procedure SendCH0( txdata : in bit_vector) is begin bus B.ID <= "00" ; for J in 1 to 2 loop B.data <= txdata(8*J1 downto 8*(J1)) ; B.START <= 1 ; wait until (B.DONE = 1) ; B.START <= 0 ; wait until (B.DONE = 0) ; end loop; end SendCH0;
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UC Irvine
Protocol generation
bus B
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UC Irvine
Renement
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UC Irvine
Arbitration models
addr / data addr / data
MemArbiter
req, grant req, grant
port1
port2
memory MEM
Static
behavior P
behavior Q
behavior R
Dynamic
MemArbiter
req, grant req, grant req, grant
port1
port2
memory MEM
behavior P
behavior Q
behavior R
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UC Irvine
Arbiter generation
and
process B_arbiter
begin wait until (Req_P=1) or (Req_Q = 1); if (Req_P = 1) then Grant_P = 1; wait unitl (Req_P = 0); Grant_P = 0"; elsif (Req_Q = 1) then Grant_Q <= 1; wait until (Req_Q = 0); Grant_Q <= 0; end if; end process;
Req_P Grant_P
process P variable AD Xtemp; begin ..... Req_P <= 1; wait until (Grant_P = 1); SendCH0(32) ; Req_P <= 0; ..... end process ; process Q variable COUNT; begin ..... Req_Q <= 1; wait until (Grant_Q = 1); SendCH3(60, COUNT); Req_Q <= 0; ..... end process;
bus B
process Xproc variable X ; begin wait on B.ID; if (B.ID="00") then receiveCH0(X); elsif (B.ID="01" ) then sendCH1(X); end if; end process;
Req_Q Grant_Q
process MEMproc variable MEM: array(0 to 63); begin wait on B.ID; if (B.ID="10") then receiveCH2(MEM); elsif (B.ID="11" ) then receiveCH3(MEM); end if; end process;
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UC Irvine
behavior A protocol
Custom
Channel X
Pa Pb
behavior B protocol
Standard
behavior X
Channel X
Pa Pb
behavior B
Standard
Standard
behavior A
Pa
Interface Process
Pb
behavior B
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UC Irvine
Protocol operations
Renement
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Protocol operations ordered by sequencing between states Constraints between events may be specied using timing arcs Conditional & repetitive event sequences require extra states, transitions
start start
ADDRp <= AddrVar(7 downto 0); a1 ARDYp <= 1; (ARCVp = 1 ) ADDRp <= AddrVar(15 downto 8); a2 AREQp <= 1; (DRDYp = 1 ) a3 DataVar <= DATAp (100 ns) (RDp = 1)
b1
b2
MAddrVar := MADDRp
b3
Protocol Pa
Protocol Pb
Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
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UC Irvine
Advantages:
Ease of comprehension, representation of timing constraints
Disadvantages:
Lack of action language, not simulatable Difcult to specify conditional and repetitive event sequences
ARDYp ADDRp ARCVp DREQp DRDYp 100ns DATAp 15..0 15..0 7..0 15..8 15..0 MADDRp RDp MDATAp
Protocol Pa
Protocol Pb
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UC Irvine
Advantages:
Functionality can be veried by simulation Easy to specify conditional and repetitive event sequences
Disadvantages:
Cumbersome to represent timing constraints between events
port ADDRp : out bit_vector(7 downto 0); port DATAp : in bit_vector(15 downto 0); port ARDYp : out bit; port ARCVp : in bit; port DREQp : out bit; port DRDYp : in bit; ADDRp <= AddrVar(7 downto 0); ARDYp <= 1; wait until (ARCVp = 1 ); ADDRp <= AddrVar(15 downto 8); DREQp <= 1; wait until (DRDYp = 1); DataVar <= DATAp; 8 ADDRp DATAp 16 ARDYp ARCVp DREQp DRDYp RDp MADDRp MDATAp 16 port MADDRp : in bit_vector(15 downto 0); port MDATAp : out bit_vector(15 downto 0); port RDp : in bit; wait until (RDp = 1); MAddrVar := MADDRp ; wait for 100 ns; MDATAp <= MemVar (MAddrVar);
16
Protocol Pa
Protocol Pb
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UC Irvine
Input: HDL description of two xed, but incompatible protocols Output: HDL process that translates one protocol to the other
i.e. responds to their control signals and sequence their data transfers
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Protocol Pa
ADDRp <= AddrVar(7 downto 0); ARDYp <= 1; wait until (ARCVp = 1 ); ADDRp <= AddrVar(15 downto 8); DREQp <= 1; wait until (DRDYp = 1); DataVar <= DATAp;
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UC Irvine
Partition the set of relations from both protocols into groups. Group represents a unit of data transfer
Protocol Pa A1 (8 bits out) B1 (16 bits in) A2 (8 bits out) G1 Protocol Pb
G2
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UC Irvine
For each operation in a group, add its dual to interface process Dual of an operation represents the complementary operation Temporary variable may be required to hold data values
Interface Process
Atomic operation wait until (Cp = 1) Cp <= 1 var <= Dp Dp <= var wait for 100 ns
Dual operation Cp <= 1 wait until (Cp = 1) Dp <= TempVar TempVar := Dp wait for 100 ns
/* (group G1) */ wait until (ARDYp = 1); 8 TempVar1(7 downto 0) := ADDRp ; ADDRp ARCVp <= 1 ; DATAp wait until (DREQp = 1); 16 TempVar1(15 downto 8) := ADDRp ; ARDYp RDp <= 1 ; MADDRp <= TempVar1; ARCVp /* (group G2) */ DREQp wait for 100 ns; DRDYp TempVar2 := MDATAp ; DRDYp <= 1 ; DATAp <= TempVar2 ;
16
MADDRp MDATAp 16
RDp
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UC Irvine
DREQp DRDYp
wait until (ARDYp = 1); TempVar1(7 downto 0) := ADDRp ; ARCVp <= 1 ; wait until (DREQp = 1); TempVar1(15 downto 8) := ADDRp ; RDp <= 1 ; MADDRp <= TempVar1; wait for 100 ns; DRDYp <= 1 ;
16
MADDRp 16 RDp
DATAp
MDATAp
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UC Irvine
Input: Timing diagram description of two xed protocols Output: Logic circuit description of transducer
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UC Irvine
Ri L Ro Ao Ai L
Ri L Ro Ao Ai E L
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UC Irvine
Ao Ri L Ao Ri L Ao Ro L Ao Ro L
Ri Ro L Ri Ro L
S Q R
Ro
S R Q
L
Ai Ro L Ai Ro
S Q R
Ai
Advantages:
Synthesizes logic for transducer circuit directly Accounts for min/max timing constraints between events
Disadvantages:
Cannot interface protocols with different data port sizes Transducer not simulatable with timing diagram description of protocols
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UC Irvine
v2
Software partition v1 v2
Hardware partition v3 s1 v4 s2
v1
Processor
Memory
Data access
B1
B2 p1 v3 Buffer s1 v4 s2 p2 Ports
B1
B2
B3
B4
p1
p2
p3 ASIC B3 B4
p3
Renement
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Data access (e.g., behavior accessing variable) renement Control access (e.g., behavior starting behavior) renement Select bus to satisfy data transfer rate and reduce interfacing cost Interface software/hardware components to standard buses Schedule software behaviors to satisfy data input/output rate Distribute variables to reduce ASIC cost and satisfy performance
Renement
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UC Irvine
Renement
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Methodology
Past design effort focused on lower levels Higher levels lack well-dened methodology and tools Paradigm shift to higher levels can increase productivity Need methodology and tools for system level
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UC Irvine
Outline
Basic concepts in design methodology Example A design methodology A generic synthesis system Conceptualization environment
Methodology
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Syntax and semantics of input and output Algorithms for transforming input to output Components to be used in the design implementation Denition and ranges of constraints Mechanism for selection of architectural styles Control strategies (scenarios or scripts)
Methodology
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UC Irvine
InteractiveTvProcessor audio_in Analog subsystem video_in av_cmd video audio + commands button
keypad receiver IC
audio
Main computer
Methodology
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UC Irvine
ProcessAVCmd
StoreGenerateVideo
av_cmd[8]
OverlayCharacters
fonts[128][16][16]
Methodology
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UC Irvine
audio_in video_in
audio_out video_out
av_cmd
main_cmds
button
Methodology
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UC Irvine
Functional specification
System design
Memory Variables
Component implementation
detailed bus protocol Processor ASIC ASIC Memory mapped address space
C code
RTL struct.
RTL struct.
Methodology
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UC Irvine
System-design tasks
Systemdesign tasks Allocation Partitioning Variables to memories Behaviors to processors Channels to buses Refinement Address assignment Interfacing Arbitration/protocols
Functional objects
Methodology
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UC Irvine
Memory allocation
Variabletomemory partitioning
Bus allocation
BehaviortoASIC/processor partitioning
Interface synthesis
Methodology
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UC Irvine
Completeness
All levels of design, all implementation styles
Extensibility
Allow addition of new algorithms and tools
Controllability
User control of tools, design-quality feedback
Interactivity
Partial design, design modication
Upgradability
Evolve to describe-and-synthesize method
Methodology
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UC Irvine
System synthesis
Compilation
Logic/Sequential synthesis
CDB
Assembly code
Methodology
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Conceptualization environment
Verification/simulation suite
Software synthesis
Description generators
ASIC synthesis
SDB
Intermediate forms
UC Irvine
Compiler
Allocator
Transformer
SR
Estimators
Partitioner
To software synthesis
To chip synthesis
Methodology
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UC Irvine
Compiler
Scheduler
Component selector CDFG Storage binder Functional unit binder Interconnection binder Module selector
Logic/Sequential synthesis
To physical design
Methodology
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UC Irvine
State minimization
Memory synthesis
State encoding
Interface synthesis
Logic minimization
Technology mapping
Physical design
Methodology
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UC Irvine
Conceptualization environment
Methodology
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Copyright (c) 1994 Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong
UC Irvine
Module type
$ 105 /100* 30
Pins
Instr
X100
GenerateAudio ASIC2 CaptureGenerateVideo CaptureAVCmd Memory1 audio_array1 audio_array2 Memory2 video_array Processor1 ProcessRemoteButtons ProcessMiscCmds Cost: 5.43 View options Y900 25 V1000 10
6000 /5000*
Partition/Allocate
Refine
Methodology
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UC Irvine
Quality metric $(System) Executiontime(CaptureAudio) Executiontime(GenerateAudio) Executiontime(CaptureGenerateVideo) Executiontime(CaptureAVCmd) Area(ASIC1) Area(ASIC2) Pins(ASIC1) Pins(ASIC2) Instr(Processor1)
Estimate/ Constraint 105/100 100/110 100/110 100/110 100/110 16000/20000 18000/20000 56/60 58/60 6000/5000 0
Violation?
constraint
Methodology
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UC Irvine
Summary
Methodology
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UC Irvine
Future directions
Advanced estimation methods Formal verication Testability Frameworks and databases Regularity exploiting System-level transformations Feedback incorporation
Methodology
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UC Irvine
References
[BHS91] F. Belina, D. Hogrefe, and A. Sarma. SDL with Applications from Protocol Specications. Prentice Hall, 1991. [BK87] G. Borriello and R.H. Katz. \Synthesis and optimization of interface transducer logic,". In Proceedings of the International Conference on Computer-Aided Design, 1987. [CS86] C.Tseng and D.P. Siewiorek. \Automated synthesis of datapaths in digital systems,". IEEE Transactions on Computer-Aided Design, pages 379{395, July 1986. [EHB94] R. Ernst, J. Henkel, and T. Benner. \Hardware-software cosynthesis for microcontrollers,". In IEEE Design & Test of Computers, pages 64{75, December 1994. [FM82] C.M. Fiduccia and R.M. Mattheyses. \A linear-time heuristic for improving network partitions,". In Proceedings of the Design Automation Conference, 1982. [GD90] R. Gupta and G. DeMicheli. \Partitioning of functional models of synchronous digital systems,". In Proceedings of the International Conference on Computer-Aided Design, pages 216{219, 1990. [GD92] R. Gupta and G. DeMicheli. \System-level synthesis using re-programmable components,". In Proceedings of the European Conference on Design Automation (EDAC), pages 2{7, 1992. [GD93] R. Gupta and G. DeMicheli. \Hardware-software cosynthesis for digital systems,". In IEEE Design & Test of Computers, pages 29{41, October 1993. [GVN94] D.D. Gajski, F. Vahid, and S. Narayan. \A system-design methodology: Executable-specication renement,". In Proceedings of the European Conference on Design Automation (EDAC), 1994. [Hal93] Nicolas Halbwachs. Synchronous Programming of Reactive Systems. Kluwer Academic Publishers, 1993. [Hoa78] C.A.R. Hoare. \Communicating sequential processes,". Communications of the ACM, 21(8): 666{677, 1978. [IEE88] IEEE Inc., N.Y. IEEE Standard VHDL Language Reference Manual, 1988. [JMP88] R. Jain, M. Mlinar, and A. Parker. \Area-time model for synthesis of non-pipelined designs,". In Proceedings of the International Conference on Computer-Aided Design, 1988. [Joh67] S.C. Johnson. \Hierarchical clustering schemes,". Psychometrika, pages 241{254, September 1967.
[KC91] Y.C. Kirkpatrick and C.K. Cheng. \Ratio cut partitioning for hierarchical designs,". IEEE Transactions on Computer-Aided Design, 10(7): 911{921, 1991. [KGV83] S. Kirkpatrick, C.D. Gelatt, and M. P. Vecchi. \Optimization by simulated annealing,". Science, 220(4598): 671{680, 1983. [KL70] B.W. Kernighan and S. Lin. \An efcient heuristic procedure for partitioning graphs,". Bell System Technical Journal, February 1970. [LT91] E.D. Lagnese and D.E. Thomas. \Architectural partitioning for system level synthesis of integrated circuits,". IEEE Transactions on Computer-Aided Design, July 1991. [MK90] M.C. McFarland and T.J. Kowalski. \Incorporating bottom-up design into hardware synthesis,". IEEE Transactions on Computer-Aided Design, September 1990. [NG92] S. Narayan and D.D. Gajski. \System clock estimation based on clock slack minimization,". In Proceedings of the European Design Automation Conference (EuroDAC), 1992. [NG94] S. Narayan and D.D. Gajski. \Synthesis of system-level bus interfaces,". In Proceedings of the European Conference on Design Automation (EDAC), 1994. [NVG92] S. Narayan, F. Vahid, and D.D. Gajski. \System specication with the SpecCharts language,". In IEEE Design & Test of Computers, Dec. 1992. [PK89] P.G. Paulin and J.P. Knight. \Algorithms for high-level synthesis,". In IEEE Design & Test of Computers, Dec. 1989. [PPM86] A.C. Parker, T. Pizzaro, and M. Mlinar. \MAHA: A program for datapath synthesis,". In Proceedings of the Design Automation Conference, 1986. [TM91] D.E. Thomas and P. Moorby. The Verilog Hardware Description Language. Kluwer Academic Publishers, 1991. [VG92] F. Vahid and D.D. Gajski. \Specication partitioning for system design,". In Proceedings of the Design Automation Conference, 1992. [VGG93] F. Vahid, J. Gong, and D.D. Gajski. \A hardware-software partitioning algorithm for minimizing hardware,". UC Irvine, Dept. of ICS, Technical Report 93-38,1993.